src/inc/9S12XDP512.h

   1 /*      9S12XDP512.h
   2
   3         Copyright 2008 Fred Cooke
   4
   5         This file is part of the FreeEMS project.
   6
   7         FreeEMS software is free software: you can redistribute it and/or modify
   8         it under the terms of the GNU General Public License as published by
   9         the Free Software Foundation, either version 3 of the License, or
  10         (at your option) any later version.
  11
  12         FreeEMS software is distributed in the hope that it will be useful,
  13         but WITHOUT ANY WARRANTY; without even the implied warranty of
  14         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15         GNU General Public License for more details.
  16
  17         You should have received a copy of the GNU General Public License
  18         along with any FreeEMS software.  If not, see <http://www.gnu.org/licenses/>.
  19
  20         We ask that if you make any changes to this file you send them upstream to us at admin@diyefi.org
  21
  22         Thank you for choosing FreeEMS to run your engine! */
  23
  24 /* Full basic register definitions for the Freescale S912XDP512 processor */
  25 /* MC9S12XDP512V2.pdf Appendix G */
  26
  27
  28 /* see if we've seen this, if not, mark seen and process */
  29 #ifndef FILE_9S12XDP512_H_SEEN
  30 #define FILE_9S12XDP512_H_SEEN
  31
  32
  33 /* shortcuts to speed formatting */
  34 /* www.atmel.com/dyn/resources/prod_documents/avr_3_04.pdf First page, second column */
  35 /* http://www.ee.nmt.edu/~rison/ee308_spr06/homepage.html */
  36 /* extra parentheses for clarity and guarantee of precedence */
  37
  38 /* Dereferenced Volatile Unsigned Char Pointer */
  39 #define DVUCP(address) (*((volatile unsigned char*)(address)))
  40 /* Dereferenced Volatile Unsigned Short Pointer */
  41 #define DVUSP(address) (*((volatile unsigned short*)(address)))
  42
  43 /* Address Volatile Unsigned Char Pointer */
  44 #define AVUCP(address) ((volatile unsigned char*)(address))
  45 /* Address Volatile Unsigned Short Pointer */
  46 #define AVUSP(address) ((volatile unsigned short*)(address))
  47
  48
  49
  50 /* Port Integration Module - Reordered within sections for clarity */
  51 /* PIM information from 5 tables the last of which is spread over three pages */
  52
  53 /* Plain ports output switch, input state registers */
  54 #define PORTS_BA DVUSP(0x0001) /* Both A and B combined as a 16 bit register for ignition access */
  55 #define PORTA DVUCP(0x0000)
  56 #define PORTB DVUCP(0x0001)
  57 #define PORTE DVUCP(0x0008)
  58 #define PORTK DVUCP(0x0032)
  59 /* #define PORTC DVUCP(0x0004) these pins are not bonded on the 112 pin package */
  60 /* #define PORTD DVUCP(0x0005) these pins are not bonded on the 112 pin package */
  61
  62
  63 /* Plain ports Data Direction Registers */
  64 #define DDRA DVUCP(0x0002)
  65 #define DDRB DVUCP(0x0003)
  66 #define DDRE DVUCP(0x0009)
  67 #define DDRK DVUCP(0x0033)
  68
  69
  70 #define DDRC DVUCP(0x0006) /* these pins are not bonded on the 112 pin package but need switching to output */
  71 #define DDRD DVUCP(0x0007) /* these pins are not bonded on the 112 pin package but need switching to output */
  72
  73
  74 /* 0b1//1//00 */
  75 /* --K//E//BA */
  76 /* TODO NOTE: the sixth bit controls pull up on BKGD and VREGEN pins set this to ???? */
  77 /* NOTE: pull up on port E is for 0-4 and 7, ports 5 and 6 are pulled down during reset and never pulled up. */
  78 #define PUCR DVUCP(0x000C) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
  79
  80
  81 /* 0b1//0//00 */
  82 /* --K//E//BA */
  83 /* NOTE: reduced drive affects all pins of all ports listed above. */
  84 #define RDRIV DVUCP(0x000D) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
  85
  86
  87 #define ECLKCTL DVUCP(0x001C) /* Comes up 0b_1100_0000 = both pins off in normal single chip mode */
  88 #define IRQCR DVUCP(0x001E) /* 0 in bit 7 makes it ultra sensitive, 1 makes it falling edge sensitive. 0 in bit 6 turns interrupts off, 1 in bit 6 turns them on. */
  89
  90
  91 /* Port T registers */
  92 #define PTT DVUCP(0x0240) /* GPIO output register, can not be read from reliably, use PTIT instead */
  93 #define PORTT DVUCP(0x0240) /* Duplicate definition for consistency */
  94 #define PTIT DVUCP(0x0241) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */
  95 #define DDRT DVUCP(0x0242) /* TODO configure all IO as outputs until we need it */
  96 #define RDRT DVUCP(0x0243) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
  97 #define PERT DVUCP(0x0244) /* pull up/down enable when used as an input, 0 = no pull up, 1 = pull up on */
  98 #define PPST DVUCP(0x0245) /* 0 = pull up, 1 = pull down */
  99
 100
 101 /* Port S registers */
 102 #define PTS DVUCP(0x0248)
 103 #define PORTS DVUCP(0x0248) /* Duplicate definition for consistency */
 104 #define PTIS DVUCP(0x0249) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */
 105 #define DDRS DVUCP(0x024A) /* TODO configure all IO as outputs until we need it */
 106 #define RDRS DVUCP(0x024B) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
 107 #define PERS DVUCP(0x024C) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
 108 #define PPSS DVUCP(0x024D) /* 0 = pull up, 1 = pull down */
 109 #define WOMS DVUCP(0x024E) /* wired OR mode TODO find out what this actually means in real terms. */
 110
 111
 112 /* Port M registers */
 113 #define PTM DVUCP(0x0250)
 114 #define PORTM DVUCP(0x0250) /* Duplicate definition for consistency */
 115 #define PTIM DVUCP(0x0251) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */
 116 #define DDRM DVUCP(0x0252) /* TODO configure all IO as outputs until we need it */
 117 #define RDRM DVUCP(0x0253) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
 118 #define PERM DVUCP(0x0254) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
 119 #define PPSM DVUCP(0x0255) /* 0 = pull up, 1 = pull down */
 120 #define WOMM DVUCP(0x0256) /* wired OR mode TODO find out what this actually means in real terms. */
 121
 122
 123 /* this should be set to the following bit mask xx????00 */
 124 #define MODRR DVUCP(0x0257)
 125
 126
 127 /* Port P registers */
 128 #define PTP DVUCP(0x0258)
 129 #define PORTP DVUCP(0x0258) /* Duplicate definition for consistency */
 130 #define PTIP DVUCP(0x0259) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */
 131 #define DDRP DVUCP(0x025A) /* TODO configure all IO as outputs until we need it */
 132 #define RDRP DVUCP(0x025B) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
 133 #define PERP DVUCP(0x025C) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
 134 #define PPSP DVUCP(0x025D) /* 0 = pull up, 1 = pull down AND when IE pull down means I on rising edge and pull up means I on falling edge */
 135 #define PIEP DVUCP(0x025E) /* interrupt enable, turns on interrupts */
 136 #define PIFP DVUCP(0x025F) /* interrupt flag, write a 1 to clear it */
 137
 138
 139 /* Port H registers */
 140 #define PTH DVUCP(0x0260)
 141 #define PORTH DVUCP(0x0260) /* Duplicate definition for consistency */
 142 #define PTIH DVUCP(0x0261) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */
 143 #define DDRH DVUCP(0x0262) /* TODO configure all IO as outputs until we need it */
 144 #define RDRH DVUCP(0x0263) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
 145 #define PERH DVUCP(0x0264) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
 146 #define PPSH DVUCP(0x0265) /* 0 = pull up, 1 = pull down AND when IE pull down means I on rising edge and pull up means I on falling edge */
 147 #define PIEH DVUCP(0x0266) /* interrupt enable, turns on interrupts */
 148 #define PIFH DVUCP(0x0267) /* interrupt flag, write a 1 to clear it */
 149
 150
 151 /* Port J registers */
 152 #define PTJ DVUCP(0x0268)
 153 #define PORTJ DVUCP(0x0268) /* Duplicate definition for consistency */
 154 #define PTIJ DVUCP(0x0269) /* read only port state bits, always return the state of the pin, can be used to detect overload on outputs */
 155 #define DDRJ DVUCP(0x026A) /* TODO configure all IO as outputs until we need it */
 156 #define RDRJ DVUCP(0x026B) /* reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
 157 #define PERJ DVUCP(0x026C) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
 158 #define PPSJ DVUCP(0x026D) /* 0 = pull up, 1 = pull down AND when IE pull down means I on rising edge and pull up means I on falling edge */
 159 #define PIEJ DVUCP(0x026E) /* interrupt enable, turns on interrupts */
 160 #define PIFJ DVUCP(0x026F) /* interrupt flag, write a 1 to clear it */
 161
 162
 163 /* #define ATD0PT1 DVUCP(0x0271)        we don't want to use valuable ATD pins as normal IO, but if we did, r/w here */
 164 /* #define ATD0DDR1 DVUCP(0x0273) for use as an input, ATD0DIEN has to be set to 1. for use as an output? */
 165 /* #define ATD0RDR1 DVUCP(0x0275) reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
 166 #define ATD0PER1 DVUCP(0x0277) /* pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
 167
 168 /* #define ATD1PT1 DVUCP(0x0279)        we don't want to use valuable ATD pins as normal IO, but if we did, r/w here */
 169 /* #define ATD1DDR1 DVUCP(0x027B)       for use as an input, ATD1DIEN1 has to be set to 1. for use as an output? */
 170 /* #define ATD1RDR1 DVUCP(0x027D)       reduced drive register when used as output, 0 = full drive, 1 = reduced drive */
 171 /* #define ATD1PER1 DVUCP(0x027F)       pull up enable when used as an input, 0 = no pull up, 1 = pull up on */
 172
 173 /* Not available on 112 pin version     */
 174 /* #define ATD1DDR0 DVUCP(0x027A) */
 175 /* 0x0278 #define ATD1PT0 DVUCP() */
 176 /* 0x027C #define ATD1RDR0 DVUCP() */
 177 /* 0x027E #define ATD1PER0 DVUCP() */
 178
 179
 180 /* Memory Mapping Control registers TODO configure these to suit our application. */
 181 /* MMC 1/4 */
 182 //0x000B MODE DVUCP()
 183 //0x000A MMCCTL0 DVUCP()
 184 //0x0013 MMCCTL1 DVUCP()
 185
 186
 187 /* Page control registers */
 188 #define RPAGE DVUCP(0x0016) /* Used to page table data in and out of visible memory. */
 189 //0x0017 EPAGE DVUCP() /* /* TODO similar to above if we need another 2k of eeprom. what are advantages/disadvantages of eeprom over flash?? */
 190 #define PPAGE DVUCP(0x0030) /* TODO look at the best way to use the flash space in a complete system with a lot of code and data. used by compiler and maybe us to switch flash pages for loading/unloading data. */
 191 //0x0010 GPAGE DVUCP() /* /* Global page register for global instruction addressing. I doubt we will use this. */
 192 //0x0011 DIRECT DVUCP() /* /* Direct addressing mode control register. I doubt we will use this. */
 193
 194
 195 //// MMC 4/4
 196 //0x011C RAMWPC /* RAM Write Protection register, the pdf document appears to be incorrect for this, best not to touch it. */
 197 //0x011D RAMXGU /* XGATE Upper region limit, this defines how much RAM we give the xgate to work with. */
 198 //0x011E RAMSHL /* Shared memory lower boundary register, this defines the lower limit of the overlap between XGATE RAM and CPU RAM */
 199 //0x011F RAMSHU /* Shared memory upper boundary register, this defines the upper limit of the overlap between XGATE RAM and CPU RAM */
 200
 201
 202 //// EBI
 203 //0x000E EBICTL0 DVUCP() /*
 204 //0x000F EBICTL1 DVUCP() /*
 205
 206
 207 //// Misc Peripheral
 208 //0x001A PARTIDH DVUCP() /*
 209 //0x001B PARTIDL DVUCP() /*
 210
 211
 212 /* Clock and Reset Generator */
 213 #define SYNR DVUCP(0x0034) /* Multiplier of result of division by REFDV below, output is new PLL/Bus freqency. */
 214 #define REFDV DVUCP(0x0035) /* Divisor of external clock frequency pre being multiplied by SYNR above. */
 215 //0x0036 CTFLG DVUCP() /*
 216 #define CRGFLG DVUCP(0x0037) /* Clock and Reset Generator flags, we use this to determine when the PLL is stable and ready to use. Also to reset the RTI flag. */
 217 #define CRGINT DVUCP(0x0038) /* Bit 7 is RTIE RTI enable bit. */
 218 #define CLKSEL DVUCP(0x0039) /* Clock select register, choose PLL or external clock with this. */
 219 #define PLLCTL DVUCP(0x003A) /* PLL frequency generator control register, used for setting the bus frequency. */
 220 #define RTICTL DVUCP(0x003B) /* Divider select register */
 221 #define COPCTL DVUCP(0x003C) /* COP watch dog control register */
 222 //0x003D FORBYP DVUCP() /*
 223 #define ARMCOP DVUCP(0x003F) /* Computer operating properly timer, we won't be using this at least until we have profiled the running application. it will just cause headaches otherwise. */
 224
 225
 226 /* Enhanced Capture Timer */
 227 /* see reference document from Huang course overview/notes : http://www.ee.nmt.edu/~rison/ee308_spr06/lectures.html */
 228 /* see this link for a discussion of the old 68hc12 timer http://www.seattlerobotics.org/encoder/nov97/68hc12.html */
 229
 230 #define TCNT DVUSP(0x0044) /* Timer counter 16 bit (0x0044 TCNT (hi), 0x0045 TCNT (lo)) */
 231
 232 /* Behavioural control registers (dual purpose) */
 233 #define TIOS DVUCP(0x0040) /* Selects input capture or output compare mode for each timer pin */
 234 #define TIE DVUCP(0x004C) /* Timer channel interrupt enable register */
 235 #define TSCR1 DVUCP(0x0046) /* Timer System Control Register 1 */
 236 #define TSCR2 DVUCP(0x004D) /* Timer System Control Register 2 */
 237 #define TFLG DVUCP(0x004E) /* Timer channel flags */
 238 #define TFLGOF DVUCP(0x004F) /* Timer over flow flag */
 239 #define PTPSR DVUCP(0x006E) /* Precision prescaler for the main timer */
 240
 241 /* Output compare control registers */
 242 #define TTOV DVUCP(0x0047) /* Timer Toggle on Overflow output compare control */
 243 #define CFORC DVUCP(0x0041) /* Output compare force, write a 1 to make the programmed action occur now */
 244 #define OC7M DVUCP(0x0042) /* Channel 7 output compare other pins control mask */
 245 #define OC7D DVUCP(0x0043) /* Channel 7 output compare other pins states */
 246
 247 /*      Timer output compare action control registers
 248  *      OMx     OLx     Action
 249  *      0       0       Timer disconnected from output pin logic
 250  *      0       1       Toggle OCx output line
 251  *      1       0       Clear OCx output line to zero
 252  *      1       1       Set OCx output line to one */
 253 #define TCTL1 DVUCP(0x0048) /* (M,L) 77,66,55,44 */
 254 #define TCTL2 DVUCP(0x0049) /* (M,L) 33,22,11,00 */
 255 #define TCTL1_ADDR AVUCP(0x0048) /* (M,L) 77,66,55,44 */
 256 #define TCTL2_ADDR AVUCP(0x0049) /* (M,L) 33,22,11,00 */
 257
 258
 259 /* Input capture control registers */
 260 #define DLYCT DVUCP(0x0069) /* Delay counter control register (minimum tooth width) */
 261 #define ICSYS DVUCP(0x006B) /* Input capture behaviour control register */
 262 #define ICOVW DVUCP(0x006A) /* Input capture overwrite allow */
 263
 264 /*      Timer input capture edge detection control registers
 265  *      EDGxB   EDGxA   Configuration
 266  *      0               0               Capture disabled
 267  *      0               1               Capture on rising edges only
 268  *      1               0               Capture on falling edges only
 269  *      1               1               Capture on any edge (rising or falling) */
 270 #define TCTL3 DVUCP(0x004A) /* (B,A) 77,66,55,44 */
 271 #define TCTL4 DVUCP(0x004B) /* (B,A) 33,22,11,00 */
 272
 273 /* Input capture holding registers for 0 - 3 */
 274 #define TC0H DVUSP(0x0078) /* 16 bit (0x0078 TC0H (hi), 0x0079 TC0H (lo)) */
 275 #define TC1H DVUSP(0x007A) /* 16 bit (0x007A TC1H (hi), 0x007B TC1H (lo)) */
 276 #define TC2H DVUSP(0x007C) /* 16 bit (0x007C TC2H (hi), 0x007D TC2H (lo)) */
 277 #define TC3H DVUSP(0x007E) /* 16 bit (0x007E TC3H (hi), 0x007F TC3H (lo)) */
 278
 279 /* Time value comparison/storage registers for each timer channel */
 280 #define TC0 DVUSP(0x0050) /* 16 bit (0x0050 TC0 (hi), 0x0051 TC0 (lo)) */
 281 #define TC1 DVUSP(0x0052) /* 16 bit (0x0052 TC1 (hi), 0x0053 TC1 (lo)) */
 282 #define TC2 DVUSP(0x0054) /* 16 bit (0x0054 TC2 (hi), 0x0055 TC2 (lo)) */
 283 #define TC3 DVUSP(0x0056) /* 16 bit (0x0056 TC3 (hi), 0x0057 TC3 (lo)) */
 284 #define TC4 DVUSP(0x0058) /* 16 bit (0x0058 TC4 (hi), 0x0059 TC4 (lo)) */
 285 #define TC5 DVUSP(0x005A) /* 16 bit (0x005A TC5 (hi), 0x005B TC5 (lo)) */
 286 #define TC6 DVUSP(0x005C) /* 16 bit (0x005C TC6 (hi), 0x005D TC6 (lo)) */
 287 #define TC7 DVUSP(0x005E) /* 16 bit (0x005E TC7 (hi), 0x005F TC7 (lo)) */
 288
 289 #define TC2_ADDR AVUSP(0x0054) /* 16 bit (0x0054 TC2 (hi), 0x0055 TC2 (lo)) */
 290 #define TC3_ADDR AVUSP(0x0056) /* 16 bit (0x0056 TC3 (hi), 0x0057 TC3 (lo)) */
 291 #define TC4_ADDR AVUSP(0x0058) /* 16 bit (0x0058 TC4 (hi), 0x0059 TC4 (lo)) */
 292 #define TC5_ADDR AVUSP(0x005A) /* 16 bit (0x005A TC5 (hi), 0x005B TC5 (lo)) */
 293 #define TC6_ADDR AVUSP(0x005C) /* 16 bit (0x005C TC6 (hi), 0x005D TC6 (lo)) */
 294 #define TC7_ADDR AVUSP(0x005E) /* 16 bit (0x005E TC7 (hi), 0x005F TC7 (lo)) */
 295
 296
 297
 298 /* Pulse accumulator control registers */
 299 //0x0068 ICPAR DVUCP() /*
 300 //0x0060 PACTL DVUCP() /*
 301 //0x0061 PAFLG DVUCP() /*
 302 //0x0070 PBCTL DVUCP() /*
 303 //0x0071 PBFLG DVUCP() /*
 304 // one short for each hi lo par based on hi address.
 305 /* Pulse accumulator registers */
 306 //0x0062 PACN3 (hi)
 307 //0x0063 PACN2 (lo)
 308 //0x0064 PACN1 (hi)
 309 //0x0065 PACN0 (lo)
 310 /* Pulse accumulator holding registers */
 311 //0x0072 PA3H DVUCP() /* hi?
 312 //0x0073 PA2H DVUCP() /* lo?
 313 //0x0074 PA1H DVUCP() /* hi?
 314 //0x0075 PA0H DVUCP() /* lo?
 315
 316
 317 /* Modulus down counter control registers */
 318 #define MCCTL DVUCP(0x0066) /* Modulus control register */
 319 #define MCFLG DVUCP(0x0067) /* Modulus flag (high bit) and input edge indicators (low 4 bits) */
 320 #define MCCNT DVUSP(0x0076) /* 16 bit (0x0076 MCCNT (hi), 0x0077 MCCNT (lo)) */
 321 #define PTMCPSR DVUCP(0x006F) /* Precision prescaler for the modulus down counter */
 322
 323
 324 /* Analog To Digital converter 1 */
 325 /* TODO Configure these and disable the non functional 16 - 23 144 pin section! */
 326 #define ATD1CTL0 DVUCP(0x0080) /* 0 - 3 define which ADC channel to wrap on when doing multiple channels */
 327 #define ATD1CTL1 DVUCP(0x0081) /* External trigger select when enabled in other control register */
 328 #define ATD1CTL2 DVUCP(0x0082) /* bit 7 turns the ADC block on. */
 329 #define ATD1CTL3 DVUCP(0x0083) /* bit 6 means conversion length is 8, bit 2 controls how the registers are used, bits 0 - 1 define freeze mode behaviour */
 330 #define ATD1CTL4 DVUCP(0x0084) /* bit 7 should be zero meaning 10bit ADC, bits 6,5 are the sample period, and 4,3,2,1,0 are the sample frequency clock scaler */
 331 #define ATD1CTL5 DVUCP(0x0085) /* bit 7 sets right justify, bit 5 sets scan mode, bit 4 sets multiplex mode */
 332 //0x0086 ATD1STAT0 DVUCP() /*
 333 //0x0088 ATD1TEST0 DVUCP() /*
 334 //0x0089 ATD1TEST1 DVUCP() /*
 335 //0x008A ATD1STAT2 DVUCP() /*
 336 //0x008B ATD1STAT1 DVUCP() /*
 337 #define ATD1DIEN0 DVUCP(0x008C) /* Digital input enable - these pins are not bonded on the 112 pin package */
 338 #define ATD1DIEN1 DVUCP(0x008D) /* Digital input enable */
 339 //0x008E ATD1PTAD0 DVUCP() /* digital use only */
 340 //0x008F ATD1PTAD1 DVUCP() /* digital use only */
 341 // one short for each hi lo par based on hi address. label with WORD for consistency
 342 #define ATD1_BASE 0x0090
 343 #define ATD1DR0 DVUSP(ATD1_BASE + 0x0) /* 16 bit (0x0090 ATD1DR0H, 0x0091 ATD1DR0L) */ /* SpareADC (NC)         */
 344 #define ATD1DR1 DVUSP(ATD1_BASE + 0x2) /* 16 bit (0x0092 ATD1DR1H, 0x0093 ATD1DR1L) */ /* SpareADC (NC)         */
 345 #define ATD1DR2 DVUSP(ATD1_BASE + 0x4) /* 16 bit (0x0094 ATD1DR2H, 0x0095 ATD1DR2L) */ /* SpareADC (NC)         */
 346 #define ATD1DR3 DVUSP(ATD1_BASE + 0x6) /* 16 bit (0x0096 ATD1DR3H, 0x0097 ATD1DR3L) */ /* SpareADC (NC)         */
 347 #define ATD1DR4 DVUSP(ATD1_BASE + 0x8) /* 16 bit (0x0098 ATD1DR4H, 0x0099 ATD1DR4L) */ /* SpareADC (NC)         */
 348 #define ATD1DR5 DVUSP(ATD1_BASE + 0xA) /* 16 bit (0x009A ATD1DR5H, 0x009B ATD1DR5L) */ /* SpareADC (NC)         */
 349 #define ATD1DR6 DVUSP(ATD1_BASE + 0xC) /* 16 bit (0x009C ATD1DR6H, 0x009D ATD1DR6L) */ /* SpareADC (NC)         */
 350 #define ATD1DR7 DVUSP(ATD1_BASE + 0xE) /* 16 bit (0x009E ATD1DR7H, 0x009F ATD1DR7L) */ /* SpareADC (NC)         */
 351
 352
 353 /* NOT bonded on the 112 pin package!! Left here in case of 144 pin FreeEMS later on. */
 354 //0x00A0 ATD1DR8H
 355 //0x00A1 ATD1DR8L
 356 //0x00A2 ATD1DR9H
 357 //0x00A3 ATD1DR9L
 358 //0x00A4 ATD1DR10H
 359 //0x00A5 ATD1DR10L
 360 //0x00A6 ATD1DR11H
 361 //0x00A7 ATD1DR11L
 362 //0x00A8 ATD1DR12H
 363 //0x00A9 ATD1DR12L
 364 //0x00AA ATD1DR13H
 365 //0x00AB ATD1DR13L
 366 //0x00AC ATD1DR14H
 367 //0x00AD ATD1DR14L
 368 //0x00AE ATD1DR15H
 369 //0x00AF ATD1DR15L
 370 /* NOT bonded on the 112 pin package!! Left here in case of 144 pin FreeEMS later on. */
 371
 372
 373 /* IIC1 - Inter Intergrated Circuit interface 1 TODO configure and use */
 374 //0x00B0 IBAD DVUCP() /*
 375 //0x00B1 IBFD DVUCP() /*
 376 //0x00B2 IBCR DVUCP() /*
 377 //0x00B3 IBSR DVUCP() /*
 378 //0x00B4 IBDR DVUCP() /*
 379
 380
 381 /* SCI2 */
 382 //0x00B8 SCI2BDH
 383 //0x00B8 SCI2ASR1
 384 //0x00B9 SCI2BDL
 385 //0x00B9 SCI2ACR1
 386 //0x00BA SCI2CR1
 387 //0x00BA SCI2ACR2
 388 //0x00BB SCI2CR2
 389 //0x00BC SCI2SR1
 390 //0x00BD SCI2SR2
 391 //0x00BE SCI2DRH
 392 //0x00BF SCI2DRL
 393
 394
 395 /* SCI3 */
 396 //0x00C0 SCI3BDH
 397 //0x00C0 SCI3ASR1
 398 //0x00C1 SCI3BDL
 399 //0x00C1 SCI3ACR1
 400 //0x00C2 SCI3CR1
 401 //0x00C2 SCI3ACR2
 402 //0x00C3 SCI3CR2
 403 //0x00C4 SCI3SR1
 404 //0x00C5 SCI3SR2
 405 //0x00C6 SCI3DRH
 406 //0x00C7 SCI3DRL
 407
 408
 409 /* SCI0 debug/comms/datalogging TODO this is our primary serial interface for flash loading, setup serial comms software to communicate with MTX or similar for testing. */
 410 #define SCI0_BASE 0x00C8
 411
 412 #define SCI0BD DVUSP(SCI0_BASE + 0x0)           /* #define SCI0BDH DVUCP(0x00C8), #define SCI0BDL DVUCP(0x00C9) (IR and baud control) */
 413 #define SCI0CR1 DVUCP(SCI0_BASE + 0x2)  /* Control reg 1 */
 414
 415 #define SCI0ASR1 DVUCP(SCI0_BASE + 0x0) /* Status reg 1a (rx flags) */
 416 #define SCI0ACR1 DVUCP(SCI0_BASE + 0x1) /* Control reg 1a (rx conf) */
 417 #define SCI0ACR2 DVUCP(SCI0_BASE + 0x2) /* Control reg 2a (rx conf) */
 418
 419 #define SCI0CR2 DVUCP(SCI0_BASE + 0x3)  /* Control reg 2 */
 420 #define SCI0SR1 DVUCP(SCI0_BASE + 0x4)  /* Status reg 1 (isr flags) */
 421 #define SCI0SR2 DVUCP(SCI0_BASE + 0x5)  /* Status reg 2 (config/control) */
 422 #define SCI0DRH DVUCP(SCI0_BASE + 0x6)  /* Data reg high (9th bit bit 7 receive bit 6 send) */
 423 #define SCI0DRL DVUCP(SCI0_BASE + 0x7)  /* Data reg low (read and write for receive and send respectively)*/
 424
 425
 426 /* SCI1 debug/comms/datalogging TODO this is our secondary serial interface, setup serial comms software to communicate with MTX or similar for testing. */
 427 //0x00D0 SCI1BDH
 428 //0x00D1 SCI1BDL
 429 //0x00D2 SCI1CR1
 430
 431 //0x00D0 SCI1ASR1
 432 //0x00D1 SCI1ACR1
 433 //0x00D2 SCI1ACR2
 434
 435 //0x00D3 SCI1CR2
 436 //0x00D4 SCI1SR1
 437 //0x00D5 SCI1SR2
 438 //0x00D6 SCI1DRH
 439 //0x00D7 SCI1DRL
 440
 441
 442 /* SPI0 */
 443 //0x00D8 SPI0CR1
 444 //0x00D9 SPI0CR2
 445 //0x00DA SPI0BR
 446 //0x00DB SPI0SR
 447 //0x00DD SPI0DR
 448
 449
 450 /* IIC0  */
 451 //0x00E0 IBAD
 452 //0x00E1 IBFD
 453 //0x00E2 IBCR
 454 //0x00E3 IBSR
 455 //0x00E4 IBDR
 456
 457
 458 /* SPI1 */
 459 //0x00F0 SPI1CR1
 460 //0x00F1 SPI1CR2
 461 //0x00F2 SPI1BR
 462 //0x00F3 SPI1SR
 463 //0x00F5 SPI1DR
 464
 465
 466 /* SPI2 */
 467 //0x00F8 SPI2CR1
 468 //0x00F9 SPI2CR2
 469 //0x00FA SPI2BR
 470 //0x00FB SPI2SR
 471 //0x00FD SPI2DR
 472
 473
 474 /* Flash Control Registers */
 475 #define FCLKDIV DVUCP(0x0100)   /* Flash Clock Divider Register R/W             */
 476 #define FSEC DVUCP(0x0101)              /* Flash Security Register R                    */
 477 #define FCNFG DVUCP(0x0103)             /* Flash Configuration Register R/W             */
 478 #define FPROT DVUCP(0x0104)             /* Flash Protection Register R/W                */
 479 #define FSTAT DVUCP(0x0105)             /* Flash Status Register R/W                    */
 480 #define FCMD DVUCP(0x0106)              /* Flash Command Register R/W                   */
 481 #define FCTL DVUCP(0x0107)              /* Flash Control Register R                             */
 482
 483 #define FADDR DVUSP(0x0108)             /* Flash Low Address Register R (0x0108 FADDRHI, 0x0109 FADDRLO)        */
 484 #define FDATA DVUSP(0x010A)             /* Flash High Data Register R (0x010A FDATAHI, 0x010B FDATALO)          */
 485
 486
 487 /* EEPROM Control Registers TODO learn how to use these to write data to the eeprom through serial comms. */
 488 //0x0110 ECLKDIV
 489 //0x0113 ECNFG
 490 //0x0114 EPROT
 491 //0x0115 ESTAT
 492 //0x0116 ECMD
 493 //0x0118 EADDRHI
 494 //0x0119 EADDRLO
 495 //0x011A EDATAHI
 496 //0x011B EDATALO
 497
 498
 499 //// IM
 500 #define IVBR DVUCP(0x0121) /* Interrupt vector table base location first byte (second is always 0x00) */
 501 //0x0126 INT_XGPRIO
 502 //0x0127 INT_CFADDR
 503 //0x0128 INT_CFDATA0
 504 //0x0129 INT_CFDATA1
 505 //0x012A INT_CFDATA2
 506 //0x012B INT_CFDATA3
 507 //0x012C INT_CFDATA4
 508 //0x012D INT_CFDATA5
 509 //0x012E INT_CFDATA6
 510 //0x012F INT_CFDATA7
 511
 512
 513 /* SCI4 */
 514 //0x0130 SCI4BDH
 515 //0x0130 SCI4ASR1
 516 //0x0131 SCI4BDL
 517 //0x0131 SCI4ACR1
 518 //0x0132 SCI4CR1
 519 //0x0132 SCI4ACR2
 520 //0x0133 SCI4CR2
 521 //0x0134 SCI4SR1
 522 //0x0135 SCI4SR2
 523 //0x0136 SCI4DRH
 524 //0x0137 SCI4DRL
 525
 526
 527 /* SCI5 */
 528 //0x0138 SCI5BDH
 529 //0x0138 SCI5ASR1
 530 //0x0139 SCI5BDL
 531 //0x0139 SCI5ACR1
 532 //0x013A SCI5CR1
 533 //0x013A SCI5ACR2
 534 //0x013B SCI5CR2
 535 //0x013C SCI5SR1
 536 //0x013D SCI5SR2
 537 //0x013E SCI5DRH
 538 //0x013F SCI5DRL
 539
 540
 541 /* CAN0 don't want this for now, leave it disabled too. CAN0CTL1 bit 7 should be set to zero to disable this. */
 542 //0x0140 CAN0CTL0
 543 #define CAN0CTL1 DVUCP(0x0141)
 544 //0x0142 CAN0BTR0
 545 //0x0143 CAN0BTR1
 546 //0x0144 CAN0RFLG
 547 //0x0145 CAN0RIER
 548 //0x0146 CAN0TFLG
 549 //0x0147 CAN0TIER
 550 //0x0148 CAN0TARQ
 551 //0x0149 CAN0TAAK
 552 //0x014A CAN0TBSEL
 553 //0x014B CAN0IDAC
 554 //0x014D CAN0MISC
 555 //0x014E CAN0RXERR
 556 //0x014F CAN0TXERR
 557 //0x0150 – 0x0153 : CAN0IDAR0 – CAN0IDAR3
 558 //0x0154 – 0x0157 : CAN0IDMR0 – CAN0IDMR3
 559 //0x0158 – 0x015B : CAN0IDAR4 – CAN0IDAR7
 560 //0x015C – 0x015F : CAN0IDMR4 – CAN0IDMR7
 561 //0x0160 – 0x016F : CAN0RXFG
 562 //0x0170 – 0x017F : CAN0TXFG
 563
 564
 565 //&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&
 566 //this block applies to all can maps!!!
 567 //
 568 //0xXXX0
 569 //Extended ID
 570 //Standard ID
 571 //CANxRIDR0
 572 //0xXXX1
 573 //Extended ID
 574 //Standard ID
 575 //CANxRIDR1
 576 //0xXXX2
 577 //Extended ID
 578 //Standard ID
 579 //CANxRIDR2
 580 //0xXXX3
 581 //Extended ID
 582 //Standard ID
 583 //CANxRIDR3
 584 //
 585 //0xXXX4–
 586 //0xXXXB
 587 //CANxRDSR0–
 588 //CANxRDSR7
 589 //0xXXXC CANRxDLR
 590 //0xXXXD Reserved
 591 //0xXXXE CANxRTSRH
 592 //0xXXXF CANxRTSRL
 593 //0xXX10
 594 //Extended ID
 595 //CANxTIDR0
 596 //Standard ID
 597 //
 598 //0xXX0x
 599 //XX10
 600 //Extended ID
 601 //CANxTIDR1
 602 //Standard ID
 603 //0xXX12
 604 //Extended ID
 605 //CANxTIDR2
 606 //Standard ID
 607 //0xXX13
 608 //Extended ID
 609 //CANxTIDR3
 610 //Standard ID
 611 //
 612 //0xXX14–
 613 //0xXX1B
 614 //CANxTDSR0–
 615 //CANxTDSR7
 616 //
 617 //0xXX1C CANxTDLR
 618 //0xXX1D CANxTTBPR
 619 //0xXX1E CANxTTSRH
 620 //0xXX1F CANxTTSRL
 621
 622 //&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&77
 623
 624
 625 /* CAN1 don't want this for now, leave it disabled too. CAN1CTL1 bit 7 should be set to zero to disable this. */
 626 //0x0180 CAN1CTL0
 627 #define CAN1CTL1 DVUCP(0x0181)
 628 //0x0182 CAN1BTR0
 629 //0x0183 CAN1BTR1
 630 //0x0184 CAN1RFLG
 631 //0x0185 CAN1RIER
 632 //0x0186 CAN1TFLG
 633 //0x0187 CAN1TIER
 634 //0x0188 CAN1TARQ
 635 //0x0189 CAN1TAAK
 636 //0x018A CAN1TBSEL
 637 //0x018B CAN1IDAC
 638 //0x018D CAN1MISC
 639 //0x018E CAN1RXERR
 640 //0x018F CAN1TXERR
 641 //0x0190 CAN1IDAR0
 642 //0x0191 CAN1IDAR1
 643 //0x0192 CAN1IDAR2
 644 //0x0193 CAN1IDAR3
 645 //0x0194 CAN1IDMR0
 646 //0x0195 CAN1IDMR1
 647 //0x0196 CAN1IDMR2
 648 //0x0197 CAN1IDMR3
 649 //0x0198 CAN1IDAR4
 650 //0x0199 CAN1IDAR5
 651 //0x019A CAN1IDAR6
 652 //0x019B CAN1IDAR7
 653 //0x019C CAN1IDMR4
 654 //0x019D CAN1IDMR5
 655 //0x019E CAN1IDMR6
 656 //0x019F CAN1IDMR7
 657 //0x01A0 – 0x01AF : CAN1RXFG
 658 //0x01B0 – 0x01BF : CAN1TXFG
 659
 660
 661 /* CAN2 CAN2CTL1 bit 7 should be set to zero to disable this. */
 662 //0x01C0 CAN2CTL0
 663 //0x01C1 CAN2CTL1
 664 //0x01C2 CAN2BTR0
 665 //0x01C3 CAN2BTR1
 666 //0x01C4 CAN2RFLG
 667 //0x01C5 CAN2RIER
 668 //0x01C6 CAN2TFLG
 669 //0x01C7 CAN2TIER
 670 //0x01C8 CAN2TARQ
 671 //0x01C9 CAN2TAAK
 672 //0x01CA CAN2TBSEL
 673 //0x01CB CAN2IDAC
 674 //0x01CD CAN2MISC
 675 //0x01CE CAN2RXERR
 676 //0x01CF CAN2TXERR
 677 //0x01D0 CAN2IDAR0
 678 //0x01D1 CAN2IDAR1
 679 //0x01D2 CAN2IDAR2
 680 //0x01D3 CAN2IDAR3
 681 //0x01D4 CAN2IDMR0
 682 //0x01D5 CAN2IDMR1
 683 //0x01D6 CAN2IDMR2
 684 //0x01D7 CAN2IDMR3
 685 //0x01D8 CAN2IDAR4
 686 //0x01D9 CAN2IDAR5
 687 //0x01DA CAN2IDAR6
 688 //0x01DB CAN2IDAR7
 689 //0x01DC CAN2IDMR4
 690 //0x01DD CAN2IDMR5
 691 //0x01DE CAN2IDMR6
 692 //0x01DF CAN2IDMR7
 693 //0x01E0 – 0x01EF : CAN2RXFG
 694 //0x01F0 – 0x01FF : CAN2TXFG
 695
 696
 697 /* CAN3 CAN3CTL1 bit 7 should be set to zero to disable this. */
 698 //0x0200 CAN3CTL0
 699 #define CAN3CTL1 DVUCP(0x0201)
 700 //0x0202 CAN3BTR0
 701 //0x0203 CAN3BTR1
 702 //0x0204 CAN3RFLG
 703 //0x0205 CAN3RIER
 704 //0x0206 CAN3TFLG
 705 //0x0207 CAN3TIER
 706 //0x0208 CAN3TARQ
 707 //0x0209 CAN3TAAK
 708 //0x020A CAN3TBSEL
 709 //0x020B CAN3IDAC
 710 //0x020E CAN3RXERR
 711 //0x020F CAN3TXERR
 712 //0x0210 CAN3IDAR0
 713 //0x0211 CAN3IDAR1
 714 //0x0212 CAN3IDAR2
 715 //0x0213 CAN3IDAR3
 716 //0x0214 CAN3IDMR0
 717 //0x0215 CAN3IDMR1
 718 //0x0216 CAN3IDMR2
 719 //0x0217 CAN3IDMR3
 720 //0x0218 CAN3IDAR4
 721 //0x0219 CAN3IDAR5
 722 //0x021A CAN3IDAR6
 723 //0x021B CAN3IDAR7
 724 //0x021C CAN3IDMR4
 725 //0x021D CAN3IDMR5
 726 //0x021E CAN3IDMR6
 727 //0x021F CAN3IDMR7
 728 //0x0220 – 0x022F : CAN3RXFG
 729 //0x0230 – 0x023F : CAN3TXFG
 730
 731
 732 /* CAN4 CAN4CTL1 bit 7 should be set to zero to disable this. */
 733 //0x0280 CAN4CTL0
 734 #define CAN4CTL1 DVUCP(0x0281)
 735 //0x0282 CAN4BTR0
 736 //0x0283 CAN4BTR1
 737 //0x0284 CAN4RFLG
 738 //0x0285 CAN4RIER
 739 //0x0286 CAN4TFLG
 740 //0x0287 CAN4TIER
 741 //0x0288 CAN4TARQ
 742 //0x0289 CAN4TAAK
 743 //0x028A CAN4TBSEL
 744 //0x028B CAN4IDAC
 745 //0x028D CAN4MISC
 746 //0x028E CAN4RXERR
 747 //0x028F CAN4TXERR
 748 //0x0290 CAN4IDAR0
 749 //0x0291 CAN4IDAR1
 750 //0x0292 CAN4IDAR2
 751 //0x0293 CAN4IDAR3
 752 //0x0294 CAN4IDMR0
 753 //0x0295 CAN4IDMR1
 754 //0x0296 CAN4IDMR2
 755 //0x0297 CAN4IDMR3
 756 //0x0298 CAN4IDAR4
 757 //0x0299 CAN4IDAR5
 758 //0x029A CAN4IDAR6
 759 //0x029B CAN4IDAR7
 760 //0x029C CAN4IDMR4
 761 //0x029D CAN4IDMR5
 762 //0x029E CAN4IDMR6
 763 //0x029F CAN4IDMR7
 764 //0x02A0 – 0x02AF : CAN4RXFG
 765 //0x02B0 – 0x02BF : CAN4TXFG
 766
 767
 768 /* ATD0 TODO configure this as ATD inputs and try them out to control rate of flashing of leds etc, or even, which LED's are flashing etc */
 769 #define ATD0CTL0 DVUCP(0x02C0) /* 0 - 2 define which ADC channel to wrap on when doing multiple channels */
 770 #define ATD0CTL1 DVUCP(0x02C1) /* External trigger select when enabled in other control register */
 771 #define ATD0CTL2 DVUCP(0x02C2) /* bit 7 turns the ADC block on. */
 772 #define ATD0CTL3 DVUCP(0x02C3) /* bit 6 means conversion length is 8, bit 2 controls how the registers are used, bits 0 - 1 define freeze mode behaviour */
 773 #define ATD0CTL4 DVUCP(0x02C4) /* bit 7 should be zero meaning 10bit ADC, bits 6,5 are the sample period, and 4,3,2,1,0 are the sample frequency clock scaler */
 774 #define ATD0CTL5 DVUCP(0x02C5) /* bit 7 sets right justify, bit 5 sets scan mode, bit 4 sets multiplex mode */
 775 //0x02C6 ATD0STAT0
 776 //0x02CB ATD0STAT1
 777 #define ATD0DIEN DVUCP(0x02CD) /* Digital input enable */
 778 //0x02CF ATD0PTAD0 digital use only
 779 #define ATD0_BASE 0x02D0 /* Maybe use this with a loop to sample them in a compact way. */
 780 #define ATD0DR0 DVUSP(ATD0_BASE + 0x0) /* 16 bit (0x02D0 ATD0DR0H, 0x02D1 ATD0DR0L) */ /* IAT/MAT on my JimStim setup                   */
 781 #define ATD0DR1 DVUSP(ATD0_BASE + 0x2) /* 16 bit (0x02D2 ATD0DR1H, 0x02D3 ATD0DR1L) */ /* CHT/CLT on my JimStim setup                   */
 782 #define ATD0DR2 DVUSP(ATD0_BASE + 0x4) /* 16 bit (0x02D4 ATD0DR2H, 0x02D5 ATD0DR2L) */ /* TPS/TPS on my JimStim setup                   */
 783 #define ATD0DR3 DVUSP(ATD0_BASE + 0x6) /* 16 bit (0x02D6 ATD0DR3H, 0x02D7 ATD0DR3L) */ /* EGO/O2 on my JimStim setup                            */
 784 #define ATD0DR4 DVUSP(ATD0_BASE + 0x8) /* 16 bit (0x02D8 ATD0DR4H, 0x02D9 ATD0DR4L) */ /* BRV  left of 3 one end of my h1 board */
 785 #define ATD0DR5 DVUSP(ATD0_BASE + 0xA) /* 16 bit (0x02DA ATD0DR5H, 0x02DB ATD0DR5L) */ /* MAP   mid of 3 one end of my h1 board */
 786 #define ATD0DR6 DVUSP(ATD0_BASE + 0xC) /* 16 bit (0x02DC ATD0DR6H, 0x02DD ATD0DR6L) */ /* AAP right of 3 one end of my h1 board */
 787 #define ATD0DR7 DVUSP(ATD0_BASE + 0xE) /* 16 bit (0x02DE ATD0DR7H, 0x02DF ATD0DR7L) */ /* SpareADC/SPARE on my JimStim setup            */
 788
 789
 790 /* VREG unit, Low Voltage Interrupt and Autonomous Periodical Interrupt */
 791 #define VREGCTRL DVUCP(0x02F1) /* VReg Control Register */
 792 #define VREGAPICL DVUCP(0x02F2) /* Autonomous Periodical Interrupt Control Register */
 793 #define VREGAPITR DVUCP(0x02F3) /* Autonomous Periodical Interrupt Trimming Register */
 794 #define VREGAPIR DVUSP(0x02F4) /* Autonomous Periodical Interrupt Rate High and Low Registers (VREGAPIRH DVUCP(0x02F4), VREGAPIRL DVUCP(0x02F5)) */
 795
 796
 797 #define PWME DVUCP(0x0300) /* PWM enable register */
 798 #define PWMPOL DVUCP(0x0301) /* PWM polarity register */
 799 #define PWMCLK DVUCP(0x0302) /* PWM clock choice register */
 800 #define PWMPRCLK DVUCP(0x0303) /* PWM Clock prescalers (bits 0,1,2 and bits 4,5,6 control 4 pins each) */
 801 #define PWMCAE DVUCP(0x0304) /* PWM Center Align Enable Register */
 802 #define PWMCTL DVUCP(0x0305) /* PWM Concatenate, stop, wait, freeze register */
 803 #define PWMSCLA DVUCP(0x0308) /* PWM Scale A register */
 804 #define PWMSCLB DVUCP(0x0309) /* PWM Scale B register */
 805 #define PWMCNT0 DVUCP(0x030C) /* PWM 8 bit counter      */
 806 #define PWMCNT1 DVUCP(0x030D) /*                                        */
 807 #define PWMCNT2 DVUCP(0x030E) /*                                        */
 808 #define PWMCNT3 DVUCP(0x030F) /*                                        */
 809 #define PWMCNT4 DVUCP(0x0310) /*                                        */
 810 #define PWMCNT5 DVUCP(0x0311) /*                                        */
 811 #define PWMCNT6 DVUCP(0x0312) /*                                        */
 812 #define PWMCNT7 DVUCP(0x0313) /* PWM 8 bit counter      */
 813 #define PWMPER0 DVUCP(0x0314) /* PWM period value       */ /* Ign LED 6 on my JimStim */
 814 #define PWMPER1 DVUCP(0x0315) /*                                        */ /* Ign LED 4 on my JimStim */
 815 #define PWMPER2 DVUCP(0x0316) /*                                        */ /* Ign LED 2 on my JimStim */
 816 #define PWMPER3 DVUCP(0x0317) /*                                        */ /* Ign LED 1 on my JimStim */
 817 #define PWMPER4 DVUCP(0x0318) /*                                        */ /* Ign LED 3 on my JimStim */
 818 #define PWMPER5 DVUCP(0x0319) /*                                        */ /* Ign LED 5 on my JimStim */
 819 #define PWMPER6 DVUCP(0x031A) /*                                        */ /* NC yet */
 820 #define PWMPER7 DVUCP(0x031B) /* PWM period value       */ /* NC yet */
 821 #define PWMDTY0 DVUCP(0x031C) /* PWM duty cycle value   */
 822 #define PWMDTY1 DVUCP(0x031D) /*                                                */
 823 #define PWMDTY2 DVUCP(0x031E) /*                                                */
 824 #define PWMDTY3 DVUCP(0x031F) /*                                                */
 825 #define PWMDTY4 DVUCP(0x0320) /*                                                */
 826 #define PWMDTY5 DVUCP(0x0321) /*                                                */
 827 #define PWMDTY6 DVUCP(0x0322) /*                                                */
 828 #define PWMDTY7 DVUCP(0x0323) /* PWM duty cycle value   */
 829 #define PWMSDN DVUCP(0x0324) /* PWM shutdown behaviour register */
 830
 831
 832 /* Periodic Interupt Timer with down counter */
 833 #define PITCFLMT DVUCP(0x0340)  /* PIT Control and Force Load Micro Timer Register, high bit enables, low 2 bits force load micro timers */
 834 #define PITFLT DVUCP(0x0341)    /* PIT Force Load Timer Register, low 4 bits force load timers */
 835 #define PITCE DVUCP(0x0342)             /* PIT Channel Enable Register, low 4 bits let the channel count */
 836 #define PITMUX DVUCP(0x0343)    /* PIT Multiplex Register, low 4 bits set which micro time base is used */
 837 #define PITINTE DVUCP(0x0344)   /* PIT Interrupt Enable Register, low four bits control the ISRs */
 838 #define PITTF DVUCP(0x0345)             /* PIT Time-Out Flag Register, low 4 bits set when each counter reaches 0 */
 839 #define PITMTLD0 DVUCP(0x0346)  /* PIT Micro Timer Load Register 0, time to start counting from when reaching zero */
 840 #define PITMTLD1 DVUCP(0x0347)  /* PIT Micro Timer Load Register 1, time to start counting from when reaching zero */
 841 #define PITLD0 DVUSP(0x0348)    /* PIT Load Register 0, time to start counting from when reaching zero (0x0348 PITLD0 (hi), 0x0349 PITLD0 (lo)) */
 842 #define PITLD1 DVUSP(0x034C)    /* PIT Load Register 1, time to start counting from when reaching zero (0x034C PITLD1 (hi), 0x034D PITLD1 (lo)) */
 843 #define PITLD2 DVUSP(0x0350)    /* PIT Load Register 2, time to start counting from when reaching zero (0x0350 PITLD2 (hi), 0x0351 PITLD2 (lo)) */
 844 #define PITLD3 DVUSP(0x0354)    /* PIT Load Register 3, time to start counting from when reaching zero (0x0354 PITLD3 (hi), 0x0355 PITLD3 (lo)) */
 845 #define PITCNT0 DVUSP(0x034A)   /* PIT Count Register 0, current value of down counter (0x034A PITCNT0 (hi), 0x034B PITCNT0 (lo)) */
 846 #define PITCNT1 DVUSP(0x034E)   /* PIT Count Register 1, current value of down counter (0x034E PITCNT1 (hi), 0x034F PITCNT1 (lo)) */
 847 #define PITCNT2 DVUSP(0x0352)   /* PIT Count Register 2, current value of down counter (0x0352 PITCNT2 (hi), 0x0353 PITCNT2 (lo)) */
 848 #define PITCNT3 DVUSP(0x0356)   /* PIT Count Register 3, current value of down counter (0x0356 PITCNT3 (hi), 0x0357 PITCNT3 (lo)) */
 849
 850
 851 // TODO XGATE Set up stuff
 852 #define XGMCTL DVUSP(0x0380) /* TODO: 7th bit of this should be set to 0 for now to turn the XGATE off */
 853 #define XGMCTLHI DVUCP(0x0380)
 854 #define XGMCTLLO DVUCP(0x0381) /* TODO: or 7th bit of this should be set to 0 for now to turn the XGATE off */
 855 //0x0382 XGCHID
 856 //0x0384 XGVBR
 857 //0x0385 XGVBR
 858 //0x0386 XGVBR
 859 //0x0387 XGVBR
 860 //0x0388 XGIF
 861 //0x0389 XGIF
 862 //0x038A XGIF
 863 //0x023B XGIF /* TODO WRONG value 0x023B stated in the manual as being both xgate and can3!!!!! should be 0x038B i believe!!!!! */
 864 //0x023C XGIF /* TODO WRONG value 0x023C stated in the manual as being both xgate and can3!!!!! should be 0x038C i believe!!!!! */
 865 //0x038D XGIF
 866 //0x038E XGIF
 867 //0x038F XGIF
 868 //0x0390 XGIF
 869 //0x0391 XGIF
 870 //0x0392 XGIF
 871 //0x0393 XGIF
 872 //0x0394 XGIF
 873 //0x0395 XGIF
 874 //0x0396 XGIF
 875 //0x0397 XGIF
 876 //0x0398 XGSWT (hi)
 877 //0x0399 XGSWT (lo)
 878 //0x039A XGSEM (hi)
 879 //0x039B XGSEM (lo)
 880 //0x039D XGCCR
 881 //0x039E XGPC (hi)
 882 //0x039F XGPC (lo)
 883 //0x03A2 XGR1 (hi)
 884 //0x03A3 XGR1 (lo)
 885 //0x03A4 XGR2 (hi)
 886 //0x03A5 XGR2 (lo)
 887 //0x03A6 XGR3 (hi)
 888 //0x03A7 XGR3 (lo)
 889 //0x03A8 XGR4 (hi)
 890 //0x03A9 XGR4 (lo)
 891 //0x03AA XGR5 (hi)
 892 //0x03AB XGR5(lo)
 893 //0x03AC XGR6 (hi)
 894 //0x03AD XGR6 (lo)
 895 //0x03AE XGR7 (hi)
 896 //0x03AF XGR7 (lo)
 897
 898
 899 //// DBG
 900 //0x0020 DBGC1 DVUCP() /*
 901 //0x0021 DBGSR DVUCP() /*
 902 //0x0022 DBGTCR DVUCP() /*
 903 //0x0023 DBGC2 DVUCP() /*
 904 //0x0024 DBGTBH DVUCP() /*
 905 //0x0025 DBGTBL DVUCP() /*
 906 //0x0026 DBGCNT DVUCP() /*
 907 //0x0027 DBGSCRX DVUCP() /*
 908 //COMPA 0x0028 DVUCP() /*
 909 //COMPC 0x0028 DVUCP() /*
 910 //DBGXCTL 0x0028 DVUCP() /*
 911 //COMPB 0x0028 DVUCP() /*
 912 //COMPD 0x0028 DVUCP() /*
 913 //0x0029 DBGXAH DVUCP() /*
 914 //0x002A DBGXAM DVUCP() /*
 915 //0x002B DBGXAL DVUCP() /*
 916 //0x002C DBGXDH DVUCP() /*
 917 //0x002D DBGXDL DVUCP() /*
 918 //0x002E DBGXDHM DVUCP() /*
 919 //0x002F DBGXDLM DVUCP() /*
 920
 921
 922 /* All reserved registers/blocks are listed here for reference */
 923
 924 /* 0x003E CTCTL COP test register */
 925 /* 0x006D TIMTST Timer test register */
 926 /* 0x0102 FTSTMOD Flash test register */
 927 /* 0x02C8 ATD0TEST0 ADC test register */
 928 /* 0x02C9 ATD0TEST1 ADC test register */
 929 /* 0x02F0 VREGHTCL VReg test register */
 930 /* 0x0306 PWMTST PWM test register */
 931 /* 0x0307 PWMPRSC PWM test register 2 */
 932 /* 0x030A PWMSCNTA PWM test register 3 */
 933 /* 0x030B PWMSCNTB PWM test register 4 */
 934
 935
 936 /* 0x001D Reserved                              */
 937 /* 0x001F Reserved                              */
 938 /* 0x0012 Reserved                              */
 939 /* 0x0014 - 0x0015 : Reserved   */
 940 /* 0x0018 - 0x0019 : Reserved   */
 941 /* 0x0031 Reserved                              */
 942 /* 0x006C Reserved                              */
 943 /* 0x00B5 - 0x00B7 : Reserved   */
 944 /* 0x0087 Reserved                              */
 945 /* 0x00DC Reserved                              */
 946 /* 0x00DE - 0x00DF : Reserved   */
 947 /* 0x00E5 - 0x00EF : Reserved   */
 948 /* 0x00F4 Reserved                              */
 949 /* 0x00F6 Reserved                              */
 950 /* 0x00F7 Reserved                              */
 951 /* 0x00FC Reserved                              */
 952 /* 0x00FE - 0x00FF : Reserved   */
 953 /* 0x010C - 0x010F : Reserved   */
 954 /* 0x0111 Reserved                              */
 955 /* 0x0112 Reserved                              */
 956 /* 0x0117 Reserved                              */
 957 /* 0x0120 Reserved                              */
 958 /* 0x0122 - 0x0125 : Reserved   */
 959 /* 0x014C Reserved                              */
 960 /* 0x018C Reserved                              */
 961 /* 0x01CC Reserved                              */
 962 /* 0x020C - 0x020D : Reserved   */
 963 /* 0x0246 - 0x0247 : Reserved   */
 964 /* 0x024F Reserved                              */
 965 /* 0x0270 Reserved                              */
 966 /* 0x0272 Reserved                              */
 967 /* 0x0274 Reserved                              */
 968 /* 0x0276 Reserved                              */
 969 /* 0x028C Reserved                              */
 970 /* 0x02C7 Reserved                              */
 971 /* 0x02CA Reserved                              */
 972 /* 0x02CC Reserved                              */
 973 /* 0x02CE Reserved                              */
 974 /* 0x02E0 – 0x02EF : Reserved */
 975 /* 0x02F6 – 0x02FF : Reserved */
 976 /* 0x0325 – 0x033F : Reserved */
 977 /* 0x0358 – 0x037F : Reserved */
 978 /* 0x0383 Reserved                              */
 979 /* 0x039C Reserved                              */
 980 /* 0x03A0 Reserved                              */
 981 /* 0x03A1 Reserved                              */
 982 /* 0x03B0 – 0x07FF : Reserved */
 983
 984
 985 /* Clear any accidental use of Reserved from typing mistakes. */
 986 #ifdef Reserved
 987         #error "We have accidentally defined reserved as Reserved in here, find it and fix it."
 988 #endif
 989
 990 #else
 991         /* let us know if we are being untidy with headers */
 992         #warning "Header file 9S12XDP512_H seen before, sort it out!"
 993 /* end of the wrapper ifdef from the very top */
 994 #endif