tree-vect.h

   1 /* Check if system supports SIMD */
   2 #include <signal.h>
   3
   4 #if defined(__i386__) || defined(__x86_64__)
   5 # include "cpuid.h"
   6 #endif
   7
   8 extern void abort (void);
   9 extern void exit (int);
  10
  11 static void
  12 sig_ill_handler (int sig)
  13 {
  14   exit(0);
  15 }
  16
  17 static void __attribute__((noinline))
  18 check_vect (void)
  19 {
  20   signal(SIGILL, sig_ill_handler);
  21 #if defined(__PAIRED__)
  22   /* 750CL paired-single instruction, 'ps_mul %v0,%v0,%v0'.  */
  23  asm volatile (".long 0x10000032");
  24 #elif defined(__ppc__) || defined(__ppc64__) || defined(__powerpc__) || defined(powerpc)
  25   /* Altivec instruction, 'vor %v0,%v0,%v0'.  */
  26   asm volatile (".long 0x10000484");
  27 #elif defined(__i386__) || defined(__x86_64__)
  28   {
  29     int a, b, c, d, want_level, want_c, want_d;
  30
  31     /* Determine what instruction set we've been compiled for, and detect
  32        that we're running with it.  This allows us to at least do a compile
  33        check for, e.g. SSE4.1 when the machine only supports SSE2.  */
  34 # ifdef __XOP__
  35     want_level = 0x80000001, want_c = bit_XOP, want_d = 0;
  36 # elif defined(__AVX__)
  37     want_level = 1, want_c = bit_AVX, want_d = 0;
  38 # elif defined(__SSE4_1__)
  39     want_level = 1, want_c = bit_SSE4_1, want_d = 0;
  40 # elif defined(__SSSE3__)
  41     want_level = 1, want_c = bit_SSSE3, want_d = 0;
  42 # else
  43     want_level = 1, want_c = 0, want_d = bit_SSE2;
  44 #  if defined(__sun__) && defined(__svr4__)
  45     /* Before Solaris 9 4/04, trying to execute an SSE2 instruction gives
  46        SIGILL even if the CPU can handle them.  */
  47     asm volatile ("unpcklpd %xmm0,%xmm2");
  48 #  endif
  49 # endif
  50
  51     if (!__get_cpuid (want_level, &a, &b, &c, &d)
  52         || ((c & want_c) | (d & want_d)) == 0)
  53       exit (0);
  54   }
  55 #elif defined(__sparc__)
  56   asm volatile (".word\t0x81b007c0");
  57 #elif defined(__arm__)
  58   {
  59     /* On some processors without NEON support, this instruction may
  60        be a no-op, on others it may trap, so check that it executes
  61        correctly.  */
  62     long long a = 0, b = 1;
  63     asm ("vorr %P0, %P1, %P2"
  64          : "=w" (a)
  65          : "0" (a), "w" (b));
  66     if (a != 1)
  67       exit (0);
  68   }
  69 #endif
  70   signal (SIGILL, SIG_DFL);
  71 }