| blob | 89b8a4d6ad154725bec590bbbe7d36d238283215 |
1 2025-02-05 Jeff Law <jlaw@ventanamicro.com>
3 * config/bfin/bfin.md (abssi): Disable pattern.
5 2025-02-05 Vladimir N. Makarov <vmakarov@redhat.com>
7 PR rtl-optimization/115568
8 * lra-remat.cc (create_cands): Check that output reload insn is
9 adjacent to given insn. Update a comment.
11 2025-02-05 Richard Sandiford <richard.sandiford@arm.com>
13 * config/aarch64/aarch64.cc (aarch64_insn_cost): Give PARALLELs
14 the same cost as the costliest SET.
16 2025-02-05 Jakub Jelinek <jakub@redhat.com>
18 PR rtl-optimization/117239
19 * cselib.cc (cselib_init): Remove spurious closing paren in
20 the #ifdef STACK_ADDRESS_OFFSET specific code.
22 2025-02-05 Jakub Jelinek <jakub@redhat.com>
24 PR rtl-optimization/117239
25 * cselib.cc: Include predict.h.
26 (callmem): Change type from rtx to rtx[2].
27 (cselib_preserve_only_values): Use callmem[0] rather than callmem.
28 (cselib_invalidate_mem): Optimize and don't try to invalidate
29 for the mem_rtx == callmem[1] case MEMs which clearly can't be
30 below the stack pointer.
31 (cselib_process_insn): Use callmem[0] rather than callmem.
32 For const/pure calls also call cselib_invalidate_mem (callmem[1])
33 in !ACCUMULATE_OUTGOING_ARGS or cfun->calls_alloca functions.
34 (cselib_init): Initialize callmem[0] rather than callmem and also
35 initialize callmem[1].
37 2025-02-05 Richard Earnshaw <rearnsha@arm.com>
39 PR target/118089
40 * config/arm/arm.cc (thumb2_expand_return): Use LDM SP!, {PC}
41 when optimizing for size, or when there's no performance benefit over
42 LDR PC, [SP], #4.
43 (arm_expand_epilogue): Likewise.
45 2025-02-05 Richard Earnshaw <rearnsha@arm.com>
47 * config/arm/arm.md (*pop_multiple_with_writeback_and_return): Remove
48 constraints. Don't validate the first transfer register here.
50 2025-02-05 Richard Earnshaw <rearnsha@arm.com>
52 * config/arm/arm.cc (decompose_addr_for_ldm_stm): New function.
53 (ldm_stm_operation_p): Rework to clarify logic. Allow single
54 registers to be pushed or popped using LDM/STM.
56 2025-02-05 Xi Ruoyao <xry111@xry111.site>
58 PR tree-optimization/118727
59 * tree-vect-patterns.cc (vect_recog_sad_pattern): Don't call
60 vect_look_through_possible_promotion on ABD inputs.
62 2025-02-05 Sebastian Huber <sebastian.huber@embedded-brains.de>
64 * config/arm/t-rtems: Add Cortex-M33 multilib.
66 2025-02-04 Andi Kleen <ak@gcc.gnu.org>
68 * doc/invoke.texi: Document file cache tunables.
69 * params.opt: Move auto tuning description to lines.
71 2025-02-04 Ilya Leoshkevich <iii@linux.ibm.com>
73 * config/s390/s390.cc (print_operand): Remove the no longer
74 necessary 31-bit and weak symbol handling.
75 * config/s390/s390.md (*movdi_64): Do not use @PLT with larl.
76 (*movsi_larl): Likewise.
77 (main_base_64): Likewise.
78 (reload_base_64): Likewise.
80 2025-02-04 Richard Biener <rguenther@suse.de>
82 PR tree-optimization/117113
83 * gimple-loop-jam.cc (unroll_jam_possible_p): Detect when
84 we cannot handle virtual SSA update.
86 2025-02-04 Andrew Pinski <quic_apinski@quicinc.com>
88 PR middle-end/116926
89 * optabs-query.cc (find_widening_optab_handler_and_mode): Fix
90 limit for `vec-mode -> scalar-mode` case.
92 2025-02-04 Richard Biener <rguenther@suse.de>
94 PR rtl-optimization/117611
95 * combine.cc (simplify_shift_const_1): Bail if not
96 scalar int mode.
98 2025-02-04 Richard Biener <rguenther@suse.de>
100 PR lto/113207
101 * ipa-free-lang-data.cc (free_lang_data_in_type): First drop
102 const/volatile qualifiers from function argument types,
103 then build a simplified type.
105 2025-02-03 Uros Bizjak <ubizjak@gmail.com>
107 * config/i386/i386.md (*sibcall_pop_memory):
108 Disable for TARGET_INDIRECT_BRANCH_REGISTER
109 * config/i386/predicates.md (call_insn_operand): Enable when
110 "satisfies_constraint_Bw (op)" is true, instead of open-coding
111 constraint here.
112 (sibcall_insn_operand): Ditto with "satisfies_constraint_Bs (op)"
114 2025-02-03 Richard Sandiford <richard.sandiford@arm.com>
116 * config/aarch64/aarch64.cc (aarch64_choose_vector_init_constant):
117 New function, split out from...
118 (aarch64_expand_vector_init_fallback): ...here. Use a bit-
119 reversed increment to find a constant index. Add support for
120 stepped constants.
122 2025-02-03 John David Anglin <danglin@gcc.gnu.org>
124 PR rtl-optimization/117248
125 * config/pa/predicates.md (r25_operand): New predicate.
126 (r26_operand): Likewise.
127 * config/pa/pa.md: Use match_operand for r25 and r26 hard
128 register operands in mult, div, udiv, mod and umod millicode
129 patterns.
131 2025-02-03 Richard Biener <rguenther@suse.de>
133 PR tree-optimization/118717
134 * tree-ssa-phiopt.cc (cond_if_else_store_replacement_1):
135 Do not common stores referencing abnormal SSA names.
136 * tree-ssa-sink.cc (sink_common_stores_to_bb): Likewise.
138 2025-02-03 Andi Kleen <ak@gcc.gnu.org>
140 * input.cc (check_line): New.
141 (test_replacement): New function to test line caching.
142 (input_cc_tests): Call test_replacement
144 2025-02-03 Andi Kleen <ak@gcc.gnu.org>
146 PR preprocessor/118168
147 * input.cc (file_cache_slot::get_next_line): Implement
148 dynamic sizing of m_line_record based on input length.
149 * params.opt: (param_file_cache_lines): Set to 0 to size
150 dynamically.
152 2025-02-03 Andi Kleen <ak@gcc.gnu.org>
154 PR preprocessor/118168
155 * input.cc (total_lines_num): Remove.
156 (file_cache_slot::evict): Ditto.
157 (file_cache_slot::create): Ditto.
158 (file_cache_slot::set_content): Ditto.
159 (file_cache_slot::file_cache_slot): Ditto.
160 (file_cache_slot::dump): Ditto.
162 2025-02-03 Andi Kleen <ak@gcc.gnu.org>
164 PR preprocessor/118168
165 * input.cc (file_cache_slot::get_next_line): Use new algorithm
166 to maintain
167 (file_cache_slot::read_line_num): Use binary search for lookup.
169 2025-02-03 Andi Kleen <ak@gcc.gnu.org>
171 PR preprocessor/118168
172 * input.cc (file_cache::tune): New function.
173 * input.h (class file_cache): Make tunables non const.
174 * params.opt: Add new tunables.
175 * toplev.cc (toplev::main): Initialize input buffer context
176 tunables.
178 2025-02-02 Gaius Mulley <gaiusmod2@gmail.com>
180 PR modula2/117411
181 * doc/gm2.texi (Exception handling): New section.
182 (The ISO system module): Add description of COFF_T.
183 (Assembler language): Tidy up last sentance.
185 2025-02-02 Lewis Hyatt <lhyatt@gmail.com>
187 PR middle-end/115913
188 * optc-save-gen.awk (cl_optimization_compare): Skip options with
189 CL_WARNING flag.
191 2025-02-01 H.J. Lu <hjl.tools@gmail.com>
193 PR target/118713
194 * config/i386/i386-expand.cc (ix86_expand_call): Change "if
195 (TARGET_X32 ...)" back to "else if (TARGET_X32 ...)".
197 2025-02-01 H.J. Lu <hjl.tools@gmail.com>
199 PR target/118713
200 * config/i386/constraints.md (Bs): Always disable if
201 TARGET_INDIRECT_BRANCH_REGISTER is true.
202 (Bw): Likewise.
203 * config/i386/i386-expand.cc (ix86_expand_call): Force indirect
204 call via register for x32 GOT slot call if
205 TARGET_INDIRECT_BRANCH_REGISTER is true.
206 * config/i386/i386-protos.h (ix86_nopic_noplt_attribute_p): New.
207 * config/i386/i386.cc (ix86_nopic_noplt_attribute_p): Make it
208 global.
209 * config/i386/i386.md (*call_got_x32): Disable indirect call via
210 memory for TARGET_INDIRECT_BRANCH_REGISTER.
211 (*call_value_got_x32): Likewise.
212 (*sibcall_value_pop_memory): Likewise.
213 * config/i386/predicates.md (constant_call_address_operand):
214 Return false if both TARGET_INDIRECT_BRANCH_REGISTER and
215 ix86_nopic_noplt_attribute_p are true.
217 2025-02-01 David Malcolm <dmalcolm@redhat.com>
219 * libsarifreplay.cc (sarif_replayer::handle_run_obj): Pass run to
220 handle_result_obj.
221 (sarif_replayer::handle_result_obj): Add run_obj param and pass it
222 to handle_location_object and handle_thread_flow_object.
223 (sarif_replayer::handle_thread_flow_object): Add run_obj param and
224 pass it to handle_thread_flow_location_object.
225 (sarif_replayer::handle_thread_flow_location_object): Add run_obj
226 param and pass it to handle_location_object.
227 (sarif_replayer::handle_location_object): Add run_obj param and
228 pass it to handle_logical_location_object.
229 (sarif_replayer::handle_logical_location_object): Add run_obj
230 param. If the run_obj is non-null and has "logicalLocations",
231 then use these "cached" logical locations if we see an "index"
232 property, as per ยง3.33.3
234 2025-02-01 Jeff Law <jlaw@ventanamicro.com>
236 PR tree-optimization/114277
237 * match.pd (a * (a || b) -> a): New pattern.
238 (a * !(a || b) -> 0): Likewise.
240 2025-01-31 Jakub Jelinek <jakub@redhat.com>
242 PR ipa/117432
243 * ipa-icf-gimple.cc (func_checker::compare_asm_inputs_outputs):
244 Also return_false if operands have incompatible types.
245 (func_checker::compare_gimple_call): Check fntype1 vs. fntype2
246 compatibility for all non-internal calls and assume fntype1 and
247 fntype2 are non-NULL for those. For calls to non-prototyped
248 calls or for stdarg_p functions after the last named argument (if any)
249 check type compatibility of call arguments.
251 2025-01-31 Vladimir N. Makarov <vmakarov@redhat.com>
253 PR rtl-optimization/116234
254 * lra-constraints.cc (multiple_insn_refs_p): New function.
255 (curr_insn_transform): Use it.
257 2025-01-31 Richard Biener <rguenther@suse.de>
259 PR debug/100530
260 * dwarf2out.cc (modified_type_die): Do not claim we handle
261 address-space qualification with dwarf_qual_info[].
263 2025-01-31 Jakub Jelinek <jakub@redhat.com>
265 PR tree-optimization/118689
266 PR modula2/115032
267 * tree-ssa-loop-niter.cc (build_cltz_expr): Return NULL_TREE if fn is
268 NULL and use_ifn is false.
270 2025-01-31 Richard Biener <rguenther@suse.de>
272 * tree-vect-loop.cc (vect_analyze_loop_operations): Only
273 call vectorizable_lc_phi when not PURE_SLP.
274 (vectorizable_reduction): Do not claim having handled
275 the inner loop LC PHI for outer loop vectorization.
277 2025-01-30 Georg-Johann Lay <avr@gjlay.de>
279 * config/avr/builtins.def (STRLEN_FLASH, STRLEN_FLASHX)
280 (STRLEN_MEMX): New DEF_BUILTIN's.
281 * config/avr/avr.cc (avr_ftype_strlen): New static function.
282 (avr_builtin_supported_p): New built-ins are not for AVR_TINY.
283 (avr_init_builtins) <strlen_flash_node, strlen_flashx_node,
284 strlen_memx_node>: Provide new fntypes.
285 (avr_fold_builtin) [AVR_BUILTIN_STRLEN_FLASH]
286 [AVR_BUILTIN_STRLEN_FLASHX, AVR_BUILTIN_STRLEN_MEMX]: Fold if
287 possible.
288 * doc/extend.texi (AVR Built-in Functions): Document
289 __builtin_avr_strlen_flash, __builtin_avr_strlen_flashx,
290 __builtin_avr_strlen_memx.
292 2025-01-30 Georg-Johann Lay <avr@gjlay.de>
294 * config/avr/builtins.def (AVR_FIRST_C_ONLY_BUILTIN_ID): New macro.
295 * config/avr/avr-protos.h (avr_builtin_supported_p): New.
296 * config/avr/avr.cc (avr_builtin_supported_p): New function.
297 (avr_init_builtins): Only provide a built-in when it is supported.
298 * config/avr/avr-c.cc (avr_cpu_cpp_builtins): Only define the
299 __BUILTIN_AVR_<NAME> build-in defines when the associated built-in
300 function is supported.
301 * doc/extend.texi (AVR Built-in Functions): Add a note that
302 following built-ins are supported for only for GNU-C.
304 2025-01-30 Jakub Jelinek <jakub@redhat.com>
305 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
307 PR target/118696
308 * config/s390/vector.md (*vec_cmpgt<mode><mode>_nocc_emu,
309 *vec_cmpgtu<mode><mode>_nocc_emu): Duplicate the first rather than
310 second V2DImode element.
312 2025-01-30 Richard Biener <rguenther@suse.de>
314 PR middle-end/118695
315 * expr.cc (expand_expr_real_1): When expanding a MEM_REF
316 to a non-MEM by committing it to a stack temporary make
317 sure to handle misaligned accesses correctly.
319 2025-01-30 Tobias Burnus <tburnus@baylibre.com>
321 * gimplify.cc (gimplify_call_expr): For OpenMP's append_args clause
322 processed by 'omp dispatch', update for internal-representation
323 changes; fix handling of hidden arguments, add some comments and
324 handle Fortran's value dummy and optional/pointer/allocatable actual
325 args.
327 2025-01-30 Richard Biener <rguenther@suse.de>
329 PR middle-end/118692
330 * expr.cc (expand_expr_real_1): When expanding a MEM_REF
331 as BIT_FIELD_REF avoid large offsets for accesses not
332 overlapping the base object.
334 2025-01-30 Richard Biener <rguenther@suse.de>
336 PR tree-optimization/114052
337 * tree-ssa-loop-niter.cc (maybe_lower_iteration_bound): Check
338 for infinite subloops we might not exit.
340 2025-01-30 Richard Sandiford <richard.sandiford@arm.com>
342 PR rtl-optimization/118320
343 * pair-fusion.cc (pair_fusion_bb_info::fuse_pair): Commonize
344 the merge of input_uses and return early if it fails.
346 2025-01-29 Gaius Mulley <gaiusmod2@gmail.com>
348 PR modula2/118010
349 PR modula2/118183
350 PR modula2/116073
351 * doc/gm2.texi (-fm2-file-offset-bits=): Change the default size
352 description to CSSIZE_T.
353 Add COFF_T to the list of data types exported by SYSTEM.def.
355 2025-01-29 Richard Sandiford <richard.sandiford@arm.com>
357 PR rtl-optimization/118429
358 * pair-fusion.cc (latest_hazard_before): Add an extra parameter
359 to say whether the instruction is a load or a store. If the
360 instruction is not a load or store and has memory side effects,
361 prevent it from being moved earlier.
362 (pair_fusion::find_trailing_add): Update call accordingly.
363 (pair_fusion_bb_info::fuse_pair): If the trailng addition had
364 a memory side-effect, use a tombstone to preserve it.
366 2025-01-29 Georg-Johann Lay <avr@gjlay.de>
368 * config/avr/avr.md (*negsi2.libgcc): New insn.
370 2025-01-29 Yoshinori Sato <ysato@users.sourceforge.jp>
372 * config/rx/constraints.md (Q): Also check that the address
373 passes rx_is_restricted_memory-address.
375 2025-01-29 Andrew Pinski <quic_apinski@quicinc.com>
377 PR tree-optimization/118505
378 * gimple-ssa-split-paths.cc (poor_ifcvt_pred): Return
379 true for trapping statements.
381 2025-01-29 Andrew Pinski <quic_apinski@quicinc.com>
383 * gimple-ssa-split-paths.cc (poor_ifcvt_candidate_code): Remove CALL_EXPR handling.
385 2025-01-29 Martin Jambor <mjambor@suse.cz>
386 Michal Jireลก <mjires@suse.cz>
388 PR tree-optimization/117892
389 * tree-ssa-dse.cc (dse_optimize_call): Leave control-altering
390 noreturn calls alone.
392 2025-01-29 Pan Li <pan2.li@intel.com>
394 PR target/117688
395 * config/riscv/riscv.cc (riscv_expand_sstrunc): Leverage the helper
396 riscv_extend_to_xmode_reg with SIGN_EXTEND.
398 2025-01-29 Pan Li <pan2.li@intel.com>
400 PR target/117688
401 * config/riscv/riscv.cc (riscv_expand_sssub): Leverage the helper
402 riscv_extend_to_xmode_reg with SIGN_EXTEND.
404 2025-01-29 Pan Li <pan2.li@intel.com>
406 PR target/117688
407 * config/riscv/riscv.cc (riscv_expand_ssadd): Leverage the helper
408 riscv_extend_to_xmode_reg with SIGN_EXTEND.
410 2025-01-29 Pan Li <pan2.li@intel.com>
412 * config/riscv/riscv.cc (riscv_gen_zero_extend_rtx): Rename from ...
413 (riscv_extend_to_xmode_reg): Rename to and add rtx_code for
414 zero/sign extend if non-Xmode.
415 (riscv_expand_usadd): Leverage the renamed function with ZERO_EXTEND.
416 (riscv_expand_ussub): Ditto.
418 2025-01-29 Richard Biener <rguenther@suse.de>
420 PR middle-end/118684
421 * expr.cc (expand_expr_real_1): When creating a stack local
422 during expansion of a handled component, when the base is
423 a SSA_NAME use its type alignment and avoid calling
424 get_object_alignment.
426 2025-01-28 Richard Biener <rguenther@suse.de>
428 PR middle-end/118684
429 * expr.cc (expand_expr_real_1): When expanding a reference
430 based on a register and we end up needing a MEM make sure
431 that's aligned as the original reference required.
433 2025-01-28 David Malcolm <dmalcolm@redhat.com>
435 * input.cc (file_cache_slot::dump): Show indices within
436 m_line_record when dumping entries.
438 2025-01-28 David Malcolm <dmalcolm@redhat.com>
440 PR other/118675
441 * diagnostic-format-sarif.cc: Define INCLUDE_STRING.
442 (escape_braces): New.
443 (set_string_property_escaping_braces): New.
444 (sarif_builder::make_message_object): Escape braces in the "text"
445 property.
446 (sarif_builder::make_message_object_for_diagram): Likewise, and
447 for the "markdown" property.
448 (sarif_builder::make_multiformat_message_string): Likewise for the
449 "text" property.
450 (xelftest::test_message_with_braces): New.
451 (selftest::diagnostic_format_sarif_cc_tests): Call it.
453 2025-01-28 Richard Sandiford <richard.sandiford@arm.com>
455 PR tree-optimization/117270
456 * tree-vect-slp.cc (vectorizable_slp_permutation_1): Make nperms
457 account for the number of times that each permutation will be used
458 during transformation.
460 2025-01-28 Richard Biener <rguenther@suse.de>
462 PR tree-optimization/112859
463 * tree-loop-distribution.cc
464 (loop_distribution::pg_add_dependence_edges): Add comment.
466 2025-01-28 Vladimir N. Makarov <vmakarov@redhat.com>
468 PR target/118663
469 * lra-constraints.cc (invalid_mode_reg_p): Check empty
470 reg_class_contents.
472 2025-01-28 Richard Biener <rguenther@suse.de>
474 PR tree-optimization/117424
475 * tree-eh.cc (tree_could_trap_p): Verify the base is
476 fully contained within a decl.
478 2025-01-28 Thomas Schwinge <tschwinge@baylibre.com>
480 * tree-pretty-print.cc (dump_omp_clause): Clarify
481 'OMP_CLAUSE_MAP_RUNTIME_IMPLICIT_P'.
483 2025-01-28 Jakub Jelinek <jakub@redhat.com>
485 PR rtl-optimization/118638
486 * combine.cc (make_extraction): Only optimize (mult x 2^n) if len is
487 larger than 1.
489 2025-01-28 Richard Sandiford <richard.sandiford@arm.com>
491 * tree-vect-slp.cc (vectorizable_slp_permutation_1): Remove
492 extra newline from dump message.
494 2025-01-28 Jeff Law <jlaw@ventanamicro.com>
496 PR target/114085
497 * config/h8300/constraints.md (U): No longer accept REGs.
498 * config/h8300/logical.md (andqi3_2): Use "rU" rather than "U".
499 (andqi3_2_clobber_flags, andqi3_1, <code>qi3_1): Likewise.
500 * config/h8300/testcompare.md (tst_extzv_1_n): Likewise.
502 2025-01-27 Robin Dapp <rdapp@ventanamicro.com>
504 PR target/117173
505 * config/riscv/riscv-v.cc (shuffle_generic_patterns): Only
506 support single-source permutes by default.
507 * config/riscv/riscv.opt: New param "riscv-two-source-permutes".
509 2025-01-27 John David Anglin <danglin@gcc.gnu.org>
511 PR c++/116524
512 * configure.ac: Check for munmap and msync.
513 * configure: Regenerate.
514 * config.in: Regenerate.
516 2025-01-27 Richard Biener <rguenther@suse.de>
518 PR tree-optimization/118653
519 * tree-vect-loop.cc (vectorizable_live_operation): Also allow
520 out-of-loop debug uses.
522 2025-01-27 Richard Biener <rguenther@suse.de>
524 PR rtl-optimization/118662
525 * combine.cc (try_combine): When re-materializing a load
526 from an extended reg by a lowpart subreg make sure we're
527 not dealing with vector or complex modes.
529 2025-01-27 Richard Biener <rguenther@suse.de>
531 PR middle-end/118643
532 * expr.cc (expand_expr_real_1): Avoid falling back to BIT_FIELD_REF
533 expansion for negative offset.
535 2025-01-27 Richard Biener <rguenther@suse.de>
537 PR tree-optimization/112859
538 PR tree-optimization/115347
539 * tree-loop-distribution.cc
540 (loop_distribution::pg_add_dependence_edges): For a zero
541 distance vector still make sure to not have an inner
542 loop with zero distance.
544 2025-01-27 Jakub Jelinek <jakub@redhat.com>
546 PR tree-optimization/118637
547 * match.pd: Canonicalize unsigned division by power of two to
548 right shift.
550 2025-01-27 Soumya AR <soumyaa@nvidia.com>
552 PR target/118490
553 * match.pd: Added ! to verify that log/exp (CST) can be constant folded.
555 2025-01-26 Ilya Leoshkevich <iii@linux.ibm.com>
557 * asan.cc (asan_emit_stack_protection): Always zero the flag
558 unless it is cleared by the __asan_stack_free_N() libcall.
560 2025-01-26 Pan Li <pan2.li@intel.com>
562 PR target/118103
563 * config/riscv/riscv.cc (riscv_conditional_register_usage): Add
564 the FRM as the global_regs.
566 2025-01-25 Andi Kleen <ak@gcc.gnu.org>
568 PR preprocessor/118168
569 * input.cc (file_cache_slot::m_error): New field.
570 (file_cache_slot::create): Clear m_error.
571 (file_cache_slot::file_cache_slot): Clear m_error.
572 (file_cache_slot::read_data): Set m_error on error.
573 (file_cache_slot::get_next_line): Use m_error instead of ferror.
575 2025-01-25 Jeff Law <jlaw@ventanamicro.com>
577 PR target/116256
578 * config/riscv/riscv.md (mvconst_internal): Reject single bit
579 constants.
580 * config/riscv/riscv.cc (riscv_gen_zero_extend_rtx): Improve
581 handling constants.
583 2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
585 * config/aarch64/aarch64-arches.def (V9_5A): Add CPA.
586 * config/aarch64/aarch64-option-extensions.def (CPA): New.
587 * doc/invoke.texi: Document +cpa.
589 2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
591 * doc/invoke.texi: Add +wfxt and +xs to armv9.2-a
593 2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
595 * config/aarch64/aarch64-arches.def (V9_5A): New.
596 * doc/invoke.texi: Document armv9.5-a option.
598 2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
600 * common/config/aarch64/aarch64-common.cc: Assert that CRYPTO
601 bit is not set.
602 * config/aarch64/aarch64-feature-deps.h
603 (info<FEAT>.explicit_on): Unset CRYPTO bit.
604 (cpu_##CORE_IDENT): Ditto.
606 2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
608 * common/config/aarch64/aarch64-common.cc
609 (aarch64_rewrite_selected_cpu): Refactor and inline into...
610 (aarch64_rewrite_mcpu): this.
611 * config/aarch64/aarch64-protos.h
612 (aarch64_rewrite_selected_cpu): Delete.
614 2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
616 * common/config/aarch64/aarch64-common.cc
617 (aarch64_get_arch_string_for_assembler): New.
618 (aarch64_rewrite_march): New.
619 (aarch64_rewrite_selected_cpu): Call new function.
620 * config/aarch64/aarch64-elf.h (ASM_SPEC): Remove identity mapping.
621 * config/aarch64/aarch64-protos.h
622 (aarch64_get_arch_string_for_assembler): New.
623 * config/aarch64/aarch64.cc
624 (aarch64_declare_function_name): Call new function.
625 (aarch64_start_file): Ditto.
626 * config/aarch64/aarch64.h
627 (EXTRA_SPEC_FUNCTIONS): Use new macro name.
628 (MCPU_TO_MARCH_SPEC): Rename to...
629 (MARCH_REWRITE_SPEC): ...this, and extend the spec rule.
630 (aarch64_rewrite_march): New declaration.
631 (MCPU_TO_MARCH_SPEC_FUNCTIONS): Rename to...
632 (AARCH64_BASE_SPEC_FUNCTIONS): ...this, and add new function.
633 (ASM_CPU_SPEC): Use new macro name.
635 2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
637 * common/config/aarch64/aarch64-common.cc
638 (aarch64_get_all_extension_candidates): Inline into...
639 (aarch64_print_hint_for_extensions): ...this.
641 2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
643 * common/config/aarch64/aarch64-common.cc
644 (aarch64_get_all_extension_candidates): Move within file.
645 (aarch64_print_hint_candidates): Move from aarch64.cc.
646 (aarch64_print_hint_for_extensions): Ditto.
647 (aarch64_print_hint_for_arch): Ditto.
648 (aarch64_print_hint_for_core): Ditto.
649 (enum aarch_parse_opt_result): Ditto.
650 (aarch64_parse_arch): Ditto.
651 (aarch64_parse_cpu): Ditto.
652 (aarch64_parse_tune): Ditto.
653 (aarch64_validate_march): Ditto.
654 (aarch64_validate_mcpu): Ditto.
655 (aarch64_validate_mtune): Ditto.
656 * config/aarch64/aarch64-protos.h
657 (aarch64_rewrite_selected_cpu): Move within file.
658 (aarch64_print_hint_for_extensions): Share function prototype.
659 (aarch64_print_hint_for_arch): Ditto.
660 (aarch64_print_hint_for_core): Ditto.
661 (enum aarch_parse_opt_result): Ditto.
662 (aarch64_validate_march): Ditto.
663 (aarch64_validate_mcpu): Ditto.
664 (aarch64_validate_mtune): Ditto.
665 (aarch64_get_all_extension_candidates): Unshare prototype.
666 * config/aarch64/aarch64.cc
667 (aarch64_parse_arch): Move to aarch64-common.cc.
668 (aarch64_parse_cpu): Ditto.
669 (aarch64_parse_tune): Ditto.
670 (aarch64_print_hint_candidates): Ditto.
671 (aarch64_print_hint_for_core): Ditto.
672 (aarch64_print_hint_for_arch): Ditto.
673 (aarch64_print_hint_for_extensions): Ditto.
674 (aarch64_validate_mcpu): Ditto.
675 (aarch64_validate_march): Ditto.
676 (aarch64_validate_mtune): Ditto.
678 2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
680 * config/aarch64/aarch64.cc
681 (aarch64_print_hint_candidates): New helper function.
682 (aarch64_print_hint_for_core_or_arch): Inline into callers.
683 (aarch64_print_hint_for_core): Inline callee and use new helper.
684 (aarch64_print_hint_for_arch): Ditto.
685 (aarch64_print_hint_for_extensions): Use new helper.
687 2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
689 * config/aarch64/aarch64.cc
690 (aarch64_print_hint_for_extensions): Receive string as a char *.
691 (aarch64_parse_arch): Don't return a const struct processor *.
692 (aarch64_parse_cpu): Ditto.
693 (aarch64_parse_tune): Ditto.
694 (aarch64_validate_mtune): Ditto.
695 (aarch64_validate_mcpu): Ditto, and use temporary variables for
696 march/mcpu cross-check.
697 (aarch64_validate_march): Ditto.
698 (aarch64_override_options): Adjust for changed parameter types.
699 (aarch64_handle_attr_arch): Ditto.
700 (aarch64_handle_attr_cpu): Ditto.
701 (aarch64_handle_attr_tune): Ditto.
703 2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
705 * common/config/aarch64/aarch64-common.cc
706 (struct aarch64_option_extension): Rename to..
707 (struct aarch64_extension_info): ...this.
708 (all_extensions): Update type name.
709 (struct arch_to_arch_name): Rename to...
710 (struct aarch64_arch_info): ...this, and rename name field.
711 (all_architectures): Update type names, and move before...
712 (struct processor_name_to_arch): ...this. Rename to...
713 (struct aarch64_processor_info): ...this, rename name field and
714 add cpu field.
715 (all_cores): Update type name, and set new field.
716 (aarch64_parse_extension): Update names.
717 (aarch64_get_all_extension_candidates): Ditto.
718 (aarch64_rewrite_selected_cpu): Ditto.
720 2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
722 * common/config/aarch64/aarch64-common.cc
723 (all_cores): Remove explicit generic entry.
725 2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
727 * config/aarch64/aarch64-opts.h
728 (enum aarch64_processor): Rename to...
729 (enum aarch64_cpu): ...this, and rename the entries.
730 * config/aarch64/aarch64.cc
731 (aarch64_type): Rename type and initial value.
732 (struct processor): Rename member types.
733 (all_architectures): Rename enum members.
734 (all_cores): Ditto.
735 (aarch64_get_tune_cpu): Rename type and enum member.
736 * config/aarch64/aarch64.h (enum target_cpus): Remove.
737 (TARGET_CPU_DEFAULT): Rename default value.
738 (aarch64_tune): Rename type.
739 * config/aarch64/aarch64.opt:
740 (selected_tune): Rename type and default value.
742 2025-01-24 Andrew Carlotti <andrew.carlotti@arm.com>
744 * config/aarch64/aarch64.cc (aarch64_override_options): Compare
745 returned feature masks directly.
747 2025-01-24 Vladimir N. Makarov <vmakarov@redhat.com>
749 PR target/118497
750 * ira-int.h (target_ira_int): Add x_ira_hard_regno_nrefs.
751 (ira_hard_regno_nrefs): New macro.
752 * ira.cc (setup_hard_regno_aclass): Remove unused code. Modify
753 the comment.
754 (setup_hard_regno_nrefs): New function.
755 (ira): Call it.
756 * ira-color.cc (calculate_saved_nregs): Check
757 ira_hard_regno_nrefs.
759 2025-01-24 yxj-github-437 <2457369732@qq.com>
761 * config/aarch64/aarch64.cc (aarch64_build_builtin_va_list): Mark
762 __builtin_va_list as TREE_PUBLIC.
763 * config/arm/arm.cc (arm_build_builtin_va_list): Likewise.
765 2025-01-24 David Malcolm <dmalcolm@redhat.com>
767 PR sarif-replay/117670
768 * Makefile.in (SARIF_REPLAY_INSTALL_NAME): New.
769 (install-libgdiagnostics): Use it,and exeext, rather than just
770 sarif-replay.
772 2025-01-24 Richard Biener <rguenther@suse.de>
774 PR tree-optimization/116010
775 * tree-data-ref.cc (contains_ssa_ref_p_1): New function.
776 (contains_ssa_ref_p): Likewise.
777 (dr_may_alias_p): Avoid treating unanalyzed base parts without
778 SSA reference conservatively.
780 2025-01-24 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
782 * config/s390/s390.h (S390_TDC_POSITIVE_ZERO): Remove.
783 (S390_TDC_NEGATIVE_ZERO): Remove.
784 (S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER): Remove.
785 (S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER): Remove.
786 (S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER): Remove.
787 (S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER): Remove.
788 (S390_TDC_POSITIVE_INFINITY): Remove.
789 (S390_TDC_NEGATIVE_INFINITY): Remove.
790 (S390_TDC_POSITIVE_QUIET_NAN): Remove.
791 (S390_TDC_NEGATIVE_QUIET_NAN): Remove.
792 (S390_TDC_POSITIVE_SIGNALING_NAN): Remove.
793 (S390_TDC_NEGATIVE_SIGNALING_NAN): Remove.
794 (S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER): Remove.
795 (S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER): Remove.
796 (S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER): Remove.
797 (S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER): Remove.
798 (S390_TDC_SIGNBIT_SET): Remove.
799 (S390_TDC_INFINITY): Remove.
800 * config/s390/s390.md (signbit<mode>2<tf_fpr>): Merge this one
801 (isinf<mode>2<tf_fpr>): and this one into
802 (<TDC_CLASS:tdc_insn><mode>2<tf_fpr>): new expander.
803 (isnormal<mode>2<tf_fpr>): New BFP expander.
804 (isnormal<mode>2): New DFP expander.
805 * config/s390/vector.md (signbittf2_vr): Merge this one
806 (isinftf2_vr): and this one into
807 (<tdc_insn>tf2_vr): new expander.
808 (signbittf2): Merge this one
809 (isinftf2): and this one into
810 (<tdc_insn>tf2): new expander.
812 2025-01-24 Richard Biener <rguenther@suse.de>
814 PR tree-optimization/118634
815 * tree-ssa-loop-ivcanon.cc (try_unroll_loop_completely):
816 Dump the number of estimated eliminated insns.
818 2025-01-24 Saurabh Jha <saurabh.jha@arm.com>
820 * config/aarch64/aarch64-sve2.md:
821 (*aarch64_pred_faminmax_fused): Fix to use the correct flags.
822 * config/aarch64/aarch64.h
823 (TARGET_SVE_FAMINMAX): Remove.
824 * config/aarch64/iterators.md: Fix iterators so that famax and
825 famin use correct flags.
827 2025-01-24 Alexandre Oliva <oliva@adacore.com>
829 PR tree-optimization/118572
830 * gimple-fold.cc (fold_truth_andor_for_ifcombine): Compare as
831 unsigned the variables whose extension bits are masked out.
833 2025-01-24 Alexandre Oliva <oliva@adacore.com>
835 * gimple-fold.cc (fold_truth_andor_for_ifcombine): Document
836 reversep's absence of effects on range tests. Don't reject
837 reversep mismatches before trying compare swapping.
839 2025-01-24 Alexandre Oliva <oliva@adacore.com>
841 PR tree-optimization/118514
842 * tree-eh.cc (bit_field_ref_in_bounds_p): New.
843 (tree_could_trap_p) <BIT_FIELD_REF>: Call it.
844 * gimple-fold.cc (make_bit_field_load): Check trapping status
845 of replacement load against original load.
847 2025-01-23 John David Anglin <danglin@gcc.gnu.org>
849 * config/pa/pa32-regs.h (ADDITIONAL_REGISTER_NAMES): Change
850 register 86 name to "%fr31L".
852 2025-01-23 Jakub Jelinek <jakub@redhat.com>
854 PR tree-optimization/118628
855 * tree-vect-stmts.cc (vectorizable_store, vectorizable_load):
856 Initialize offvar to NULL_TREE.
858 2025-01-23 Georg-Johann Lay <avr@gjlay.de>
860 PR tree-optimization/118012
861 PR tree-optimization/118360
862 * config/avr/avr.opt (-mpr118012): New undocumented option.
863 * config/avr/avr-protos.h (avr_out_sextr)
864 (avr_emit_skip_pixop, avr_emit_skip_clear): New protos.
865 * config/avr/avr.cc (avr_adjust_insn_length)
866 [case ADJUST_LEN_SEXTR]: Handle case.
867 (avr_rtx_costs_1) [NEG]: Costs for NEG (ZERO_EXTEND (ZERO_EXTRACT)).
868 [MULT && avropt_pr118012]: Costs for MULT (x AND 1).
869 (avr_out_sextr, avr_emit_skip_pixop, avr_emit_skip_clear): New
870 functions.
871 * config/avr/avr.md [avropt_pr118012]: Add combine patterns with
872 that condition that try to work around PR118012.
873 (adjust_len) <sextr>: Add insn attr value.
874 (pixop): New code iterator.
875 (mulsi3) [avropt_pr118012 && !AVR_TINY]: Allow these in insn condition.
877 2025-01-23 Richard Sandiford <richard.sandiford@arm.com>
879 PR rtl-optimization/118562
880 * rtl-ssa/blocks.cc (function_info::replace_phi): When converting
881 to a degenerate phi, make sure to remove all uses of the previous
882 inputs.
884 2025-01-23 Richard Sandiford <richard.sandiford@arm.com>
886 * config/aarch64/aarch64-tuning-flags.def
887 (AARCH64_EXTRA_TUNE_CHEAP_FPMR_WRITE): New tuning flag.
888 * config/aarch64/aarch64.h (TARGET_CHEAP_FPMR_WRITE): New macro.
889 * config/aarch64/aarch64.md: Split moves into FPMR into a test
890 and branch around.
891 (aarch64_write_fpmr): New pattern.
893 2025-01-23 Richard Sandiford <richard.sandiford@arm.com>
895 * config/aarch64/aarch64.cc (aarch64_memory_move_cost): Account
896 for the cost of moving in and out of GENERAL_SYSREGS.
898 2025-01-23 Richard Sandiford <richard.sandiford@arm.com>
900 * config/aarch64/aarch64.md (*mov<SHORT:mode>_aarch64)
901 (*movsi_aarch64, *movdi_aarch64): Allow the source of an MSR
902 to be zero.
904 2025-01-23 Jakub Jelinek <jakub@redhat.com>
906 PR tree-optimization/118605
907 * tree-assume.cc (assume_query::m_parm_list): Change type
908 from bitmap & to bitmap.
910 2025-01-23 Tejas Belagod <tejas.belagod@arm.com>
912 * omp-low.cc (use_pointer_for_field): Use pointer if the OMP data
913 structure's field type is a poly-int.
915 2025-01-23 Jakub Jelinek <jakub@redhat.com>
917 PR middle-end/114877
918 * builtins.cc (fold_builtin_frexp): Handle rvc_nan and rvc_inf cases
919 like rvc_zero, return passed in arg and set *exp = 0.
921 2025-01-23 Torbjรถrn SVENSSON <torbjorn.svensson@foss.st.com>
923 * doc/sourcebuild.texi (Effective-Target Keywords): Document
924 'alarm'.
926 2025-01-23 Georg-Johann Lay <avr@gjlay.de>
928 PR target/117726
929 * config/avr/avr.cc (avr_ld_regno_p): New function.
930 (ashlsi3_out) [case 25,26,27,28,29,30]: Handle and tweak.
931 (lshrsi3_out): Same.
932 (avr_rtx_costs_1) [SImode, ASHIFT, LSHIFTRT]: Adjust costs.
933 * config/avr/avr.md (ashlsi3, *ashlsi3, *ashlsi3_const):
934 Add "r,r,C4L" alternative.
935 (lshrsi3, *lshrsi3, *lshrsi3_const): Add "r,r,C4R" alternative.
936 * config/avr/constraints.md (C4R, C4L): New,
938 2025-01-23 Richard Biener <rguenther@suse.de>
940 PR tree-optimization/118558
941 * tree-vectorizer.h (vect_known_alignment_in_bytes): Pass
942 through offset to dr_misalignment.
943 * tree-vect-stmts.cc (get_group_load_store_type): Compute
944 offset applied for negative stride and use it when querying
945 alignment of accesses.
946 (vectorizable_load): Likewise.
948 2025-01-23 Nathaniel Shead <nathanieloshead@gmail.com>
950 PR c++/107741
951 * common.opt: Add -fabi-version=20.
952 * doc/invoke.texi: Likewise.
954 2025-01-23 Xi Ruoyao <xry111@xry111.site>
956 PR target/118501
957 * config/loongarch/loongarch.md (@xorsign<mode>3): Use
958 force_lowpart_subreg.
960 2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
962 * config/i386/avx10_2-512convertintrin.h:
963 Omit "p" for packed for FP8.
964 * config/i386/avx10_2convertintrin.h: Ditto.
966 2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
968 PR target/118270
969 * config/i386/avx10_2-512satcvtintrin.h: Change intrin and
970 builtin name according to new mnemonics.
971 * config/i386/avx10_2satcvtintrin.h: Ditto.
972 * config/i386/i386-builtin.def (BDESC): Ditto.
973 * config/i386/sse.md
974 (UNSPEC_VCVTBF162IBS): Rename from UNSPEC_VCVTNEBF162IBS.
975 (UNSPEC_VCVTBF162IUBS): Rename from UNSPEC_VCVTNEBF162IUBS.
976 (UNSPEC_VCVTTBF162IBS): Rename from UNSPEC_VCVTTNEBF162IBS.
977 (UNSPEC_VCVTTBF162IUBS): Rename from UNSPEC_VCVTTNEBF162IUBS.
978 (UNSPEC_CVTNE_BF16_IBS_ITER): Rename to...
979 (UNSPEC_CVT_BF16_IBS_ITER): ...this. Adjust UNSPEC name.
980 (sat_cvt_sign_prefix): Adjust UNSPEC name.
981 (sat_cvt_trunc_prefix): Ditto.
982 (avx10_2_cvt<sat_cvt_trunc_prefix>nebf162i<sat_cvt_sign_prefix>bs<mode><mask_name>):
983 Rename to...
984 (avx10_2_cvt<sat_cvt_trunc_prefix>bf162i<sat_cvt_sign_prefix>bs<mode><mask_name>):
985 ...this. Change instruction name output.
987 2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
989 PR target/118270
990 * config/i386/avx10_2-512convertintrin.h: Change intrin and
991 builtin name according to new mnemonics.
992 * config/i386/avx10_2convertintrin.h: Ditto.
993 * config/i386/i386-builtin.def (BDESC): Ditto.
994 * config/i386/sse.md
995 (UNSPEC_VCVTPH2BF8): Rename from UNSPEC_VCVTNEPH2BF8.
996 (UNSPEC_VCVTPH2BF8S): Rename from UNSPEC_VCVTNEPH2BF8S.
997 (UNSPEC_VCVTPH2HF8): Rename from UNSPEC_VCVTNEPH2HF8.
998 (UNSPEC_VCVTPH2HF8S): Rename from UNSPEC_VCVTNEPH2HF8S.
999 (UNSPEC_CONVERTPH2FP8): Rename from UNSPEC_NECONVERTPH2FP8.
1000 Adjust UNSPEC name.
1001 (convertph2fp8): Rename from neconvertph2fp8. Adjust
1002 iterator map.
1003 (vcvt<neconvertph2fp8>v8hf): Rename to...
1004 (vcvt<neconvertph2fp8>v8hf): ...this.
1005 (*vcvt<neconvertph2fp8>v8hf): Rename to...
1006 (*vcvt<neconvertph2fp8>v8hf): ...this.
1007 (vcvt<neconvertph2fp8>v8hf_mask): Rename to...
1008 (vcvt<neconvertph2fp8>v8hf_mask): ...this.
1009 (*vcvt<neconvertph2fp8>v8hf_mask): Rename to...
1010 (*vcvt<neconvertph2fp8>v8hf_mask): ...this.
1011 (vcvt<neconvertph2fp8><mode><mask_name>): Rename to...
1012 (vcvt<convertph2fp8><mode><mask_name>): ...this.
1014 2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
1016 PR target/118270
1017 * config/i386/avx10_2-512convertintrin.h: Change intrin and
1018 builtin name according to new mnemonics.
1019 * config/i386/avx10_2convertintrin.h: Ditto.
1020 * config/i386/i386-builtin.def (BDESC): Ditto.
1021 * config/i386/sse.md
1022 (UNSPEC_VCVT2PH2BF8): Rename from UNSPEC_VCVTNE2PH2BF8.
1023 (UNSPEC_VCVT2PH2BF8S): Rename from UNSPEC_VCVTNE2PH2BF8S.
1024 (UNSPEC_VCVT2PH2HF8): Rename from UNSPEC_VCVTNE2PH2HF8.
1025 (UNSPEC_VCVT2PH2HF8S): Rename from UNSPEC_VCVTNE2PH2HF8S.
1026 (UNSPEC_CONVERTFP8_PACK): Rename from UNSPEC_NECONVERTFP8_PACK.
1027 Adjust UNSPEC name.
1028 (convertfp8_pack): Rename from neconvertfp8_pack. Adjust
1029 iterator map.
1030 (vcvt<neconvertfp8_pack><mode><mask_name>): Rename to...
1031 (vcvt<convertfp8_pack><mode><mask_name>): ...this.
1033 2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
1035 PR target/118270
1036 * config/i386/avx10_2bf16intrin.h: Change intrin and builtin
1037 name according to new mnemonics.
1038 * config/i386/i386-builtin.def (BDESC): Ditto.
1039 * config/i386/i386-expand.cc
1040 (ix86_expand_fp_compare): Adjust comments.
1041 (ix86_expand_builtin): Adjust switch case.
1042 * config/i386/i386.md (cmpibf): Change instruction name output.
1043 * config/i386/sse.md (UNSPEC_VCOMSBF16): Removed.
1044 (avx10_2_comisbf16_v8bf): New.
1045 (avx10_2_comsbf16_v8bf): Removed.
1047 2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
1049 PR target/118270
1050 * config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
1051 name according to new mnemonics.
1052 * config/i386/avx10_2bf16intrin.h: Ditto.
1053 * config/i386/i386-builtin.def (BDESC): Ditto.
1054 * config/i386/sse.md
1055 (UNSPEC_VFPCLASSBF16); Rename from UNSPEC_VFPCLASSPBF16.
1056 (avx10_2_getexppbf16_<mode><mask_name>): Rename to...
1057 (avx10_2_getexpbf16_<mode><mask_name>): ...this.
1058 Change instruction name output.
1059 (avx10_2_fpclasspbf16_<mode><mask_scalar_merge_name>):
1060 Rename to...
1061 (avx10_2_fpclassbf16_<mode><mask_scalar_merge_name>): ...this.
1062 Change instruction name output.
1064 2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
1066 PR target/118270
1067 * config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
1068 name according to new mnemonics.
1069 * config/i386/avx10_2bf16intrin.h: Ditto.
1070 * config/i386/i386-builtin.def (BDESC): Ditto.
1071 * config/i386/sse.md
1072 (UNSPEC_VSCALEFBF16): Rename from UNSPEC_VSCALEFPBF16.
1073 (avx10_2_scalefpbf16_<mode><mask_name>): Rename to...
1074 (avx10_2_scalefbf16_<mode><mask_name>): ...this.
1075 Change instruction name output.
1076 (avx10_2_rsqrtpbf16_<mode><mask_name>): Rename to...
1077 (avx10_2_rsqrtbf16_<mode><mask_name>): ...this.
1078 Change instruction name output.
1079 (avx10_2_sqrtnepbf16_<mode><mask_name>): Rename to...
1080 (avx10_2_sqrtbf16_<mode><mask_name>): ...this.
1081 Change instruction name output.
1083 2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
1085 PR target/118270
1086 * config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
1087 name according to new mnemonics.
1088 * config/i386/avx10_2bf16intrin.h: Ditto.
1089 * config/i386/i386-builtin.def (BDESC): Ditto.
1090 * config/i386/sse.md
1091 (UNSPEC_VRNDSCALEBF16): Rename from UNSPEC_VRNDSCALENEPBF16.
1092 (UNSPEC_VREDUCEBF16): Rename from UNSPEC_VREDUCENEPBF16.
1093 (UNSPEC_VGETMANTBF16): Rename from UNSPEC_VGETMANTPBF16.
1094 (BF16IMMOP): Adjust iterator due to UNSPEC name change.
1095 (bf16immop): Ditto.
1096 (avx10_2_<bf16immop>pbf16_<mode><mask_name>): Rename to...
1097 (avx10_2_<bf16immop>bf16_<mode><mask_name>): ...this. Change
1098 instruction name output.
1100 2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
1102 PR target/118270
1103 * config/i386/avx10_2-512minmaxintrin.h: Change intrin and
1104 builtin name according to new mnemonics.
1105 * config/i386/avx10_2minmaxintrin.h: Ditto.
1106 * config/i386/i386-builtin.def (BDESC): Ditto.
1107 * config/i386/sse.md
1108 (UNSPEC_MINMAXBF16): Rename from UNSPEC_MINMAXNEPBF16.
1109 (avx10_2_minmaxnepbf16_<mode><mask_name>): Rename to...
1110 (avx10_2_minmaxbf16_<mode><mask_name>): ...this. Change
1111 instruction name output.
1113 2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
1115 PR target/118270
1116 * config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
1117 name according to new mnemonics.
1118 * config/i386/avx10_2bf16intrin.h: Ditto.
1119 * config/i386/i386-builtin.def (BDESC): Ditto.
1120 * config/i386/sse.md
1121 (avx10_2_<code>pbf16_<mode><mask_name>): Rename to...
1122 (avx10_2_<code>bf16_<mode><mask_name>): ...this.
1123 Change instruction name output.
1124 (avx10_2_cmppbf16_<mode><mask_scalar_merge_name>): Rename to...
1125 (avx10_2_cmpbf16_<mode><mask_scalar_merge_name>): ...this.
1126 Change instruction name output.
1128 2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
1130 PR target/118270
1131 * config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
1132 names according to new mnemonics.
1133 * config/i386/avx10_2bf16intrin.h: Ditto.
1134 * config/i386/i386-builtin.def (BDESC): Ditto.
1135 * config/i386/sse.md
1136 (avx10_2_fmaddnepbf16_<mode>_maskz): Rename to...
1137 (avx10_2_fmaddbf16_<mode>_maskz): ...this. Adjust emit_insn.
1138 (avx10_2_fmaddnepbf16_<mode><sd_maskz_name>): Rename to...
1139 (avx10_2_fmaddbf16_<mode><sd_maskz_name>): ...this.
1140 Change instruction name output.
1141 (avx10_2_fmaddnepbf16_<mode>_mask): Rename to...
1142 (avx10_2_fmaddbf16_<mode>_mask): ...this.
1143 Change instruction name output.
1144 (avx10_2_fmaddnepbf16_<mode>_mask3): Rename to...
1145 (avx10_2_fmaddbf16_<mode>_mask3): ...this.
1146 Change instruction name output.
1147 (avx10_2_fnmaddnepbf16_<mode>_maskz): Rename to...
1148 (avx10_2_fnmaddbf16_<mode>_maskz): ...this. Adjust emit_insn.
1149 (avx10_2_fnmaddnepbf16_<mode><sd_maskz_name>): Rename to...
1150 (avx10_2_fnmaddbf16_<mode><sd_maskz_name>): ...this.
1151 Change instruction name output.
1152 (avx10_2_fnmaddnepbf16_<mode>_mask): Rename to...
1153 (avx10_2_fnmaddbf16_<mode>_mask): ...this.
1154 Change instruction name output.
1155 (avx10_2_fnmaddnepbf16_<mode>_mask3): Rename to...
1156 (avx10_2_fnmaddbf16_<mode>_mask3): ...this.
1157 Change instruction name output.
1158 (avx10_2_fmsubnepbf16_<mode>_maskz): Rename to...
1159 (avx10_2_fmsubbf16_<mode>_maskz): ...this. Adjust emit_insn.
1160 (avx10_2_fmsubnepbf16_<mode><sd_maskz_name>): Rename to...
1161 (avx10_2_fmsubbf16_<mode><sd_maskz_name>): ...this.
1162 Change instruction name output.
1163 (avx10_2_fmsubnepbf16_<mode>_mask): Rename to...
1164 (avx10_2_fmsubbf16_<mode>_mask): ...this.
1165 Change instruction name output.
1166 (avx10_2_fmsubnepbf16_<mode>_mask3): Rename to...
1167 (avx10_2_fmsubbf16_<mode>_mask3): ...this.
1168 Change instruction name output.
1169 (avx10_2_fnmsubnepbf16_<mode>_maskz): Rename to...
1170 (avx10_2_fnmsubbf16_<mode>_maskz): ...this. Adjust emit_insn.
1171 (avx10_2_fnmsubnepbf16_<mode><sd_maskz_name>): Rename to...
1172 (avx10_2_fnmsubbf16_<mode><sd_maskz_name>): ...this.
1173 Change instruction name output.
1174 (avx10_2_fnmsubnepbf16_<mode>_mask): Rename to...
1175 (avx10_2_fnmsubbf16_<mode>_mask): ...this.
1176 Change instruction name output.
1177 (avx10_2_fnmsubnepbf16_<mode>_mask3): Rename to...
1178 (avx10_2_fnmsubbf16_<mode>_mask3): ...this.
1179 Change instruction name output.
1181 2025-01-23 Haochen Jiang <haochen.jiang@intel.com>
1183 PR target/118270
1184 * config/i386/avx10_2-512bf16intrin.h: Change intrin and builtin
1185 name according to new mnemonics.
1186 * config/i386/avx10_2bf16intrin.h: Ditto.
1187 * config/i386/i386-builtin.def (BDESC): Ditto.
1188 * config/i386/sse.md (div<mode>3): Adjust emit_insn.
1189 (avx10_2_<insn>nepbf16_<mode><mask_name>): Rename to...
1190 (avx10_2_<insn>bf16_<mode><mask_name>): ...this. Change
1191 instruction name output.
1192 (avx10_2_rcppbf16_<mode><mask_name>): Rename to...
1193 (avx10_2_rcpbf16_<mode><mask_name>):...this. Change
1194 instruction name output.
1196 2025-01-22 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
1198 * config/s390/s390.cc: Fix arch15 machine string which must not
1199 be empty.
1201 2025-01-22 Richard Sandiford <richard.sandiford@arm.com>
1203 * config/aarch64/aarch64.md (aarch64_read_sysregti): Change
1204 the source predicate to aarch64_reg_or_zero.
1206 2025-01-22 Xi Ruoyao <xry111@xry111.site>
1208 * config/loongarch/loongarch.md
1209 (<optab>_alsl_reversesi_extended): Add '&' to the destination
1210 register constraint and append '0' to the first source register
1211 constraint to indicate the destination register cannot be same
1212 as the second source register, and change the split condition to
1213 reload_completed so that the insn will be split only after RA in
1214 order to obtain allocated registers that satisfy the above
1215 constraints.
1217 2025-01-21 Jeff Law <jlaw@ventanamicro.com>
1219 Revert:
1220 2024-10-29 yulong <shiyulong@iscas.ac.cn>
1222 * config.gcc: Add riscv_cmo.h.
1223 * config/riscv/riscv_cmo.h: New file.
1225 2025-01-21 Andrew Pinski <quic_apinski@quicinc.com>
1227 PR tree-optimization/118483
1228 * match.pd (`x ==/!= ~x`): Allow for an optional convert
1229 and use itwise_inverted_equal_p/maybe_bit_not instead of
1230 directly matching bit_not.
1232 2025-01-21 Robin Dapp <rdapp@ventanamicro.com>
1234 * config/riscv/riscv.cc (riscv_file_end): Fix format string.
1235 (riscv_lshift_subword): Mark MODE as unused.
1237 2025-01-21 Georg-Johann Lay <avr@gjlay.de>
1239 * config/avr/avr-passes.cc (avr_emit_shift) [ASHIFT,HImode]:
1240 Allow offsets 5 and 6 as 3op provided have MUL and a scratch.
1241 * config/avr/avr.cc (avr_optimize_size_max_p): New function.
1242 (avr_out_ashlhi3_mul): New function.
1243 (ashlhi3_out) [case 4, 5, 6]: Better speed for -Os.
1244 * config/avr/avr.md (isa) <mul, no_mul>: New attr values.
1245 (*ashlhi3_const): Add alternative for offsets 5 and 6.
1247 2025-01-21 Jin Ma <jinma@linux.alibaba.com>
1249 PR target/116593
1250 * config/riscv/constraints.md (vl): New.
1251 * config/riscv/thead-vector.md: Replacing rK with rvl.
1252 * config/riscv/vector.md: Likewise.
1254 2025-01-21 Denis Chertykov <chertykov@gmail.com>
1256 * lra-spills.cc (assign_stack_slot_num_and_sort_pseudos): Use known_ge
1257 to compare sizes.
1259 2025-01-21 Jeff Law <jlaw@ventanamicro.com>
1261 PR target/116256
1262 * config/riscv/predicates.md (consecutive_bits_operand): Properly
1263 handle (const_int 0).
1265 2025-01-21 Alfie Richards <alfie.richards@arm.com>
1267 * config/aarch64/aarch64.opt.urls: Regenerate
1269 2025-01-21 Richard Biener <rguenther@suse.de>
1271 PR tree-optimization/118569
1272 * cfgloopmanip.cc (fix_loop_placement): When the loops
1273 nesting parents changed, mark all blocks to be scanned
1274 for LC PHI uses.
1275 (fix_bb_placements): Remove code moved into fix_loop_placement.
1277 2025-01-21 Vladimir Miloserdov <vladimir.miloserdov@arm.com>
1279 * config/aarch64/aarch64-c.cc
1280 (aarch64_update_cpp_builtins): Add new flag TARGET_LUT.
1281 * config/aarch64/aarch64-sve-builtins-shapes.cc
1282 (struct luti_base): Shape for lut intrinsics.
1283 (SHAPE): Specializations for lut shapes for luti2 and luti4..
1284 * config/aarch64/aarch64-sve-builtins-shapes.h: Declare lut
1285 intrinsics.
1286 * config/aarch64/aarch64-sve-builtins-sve2.cc
1287 (class svluti_lane_impl): Define expand for lut intrinsics.
1288 (FUNCTION): Define expand for lut intrinsics.
1289 * config/aarch64/aarch64-sve-builtins-sve2.def
1290 (REQUIRED_EXTENSIONS): Declare lut intrinsics behind lut flag.
1291 (svluti2_lane): Define intrinsic behind flag.
1292 (svluti4_lane): Define intrinsic behind flag.
1293 * config/aarch64/aarch64-sve-builtins-sve2.h: Declare lut
1294 intrinsics.
1295 * config/aarch64/aarch64-sve-builtins.cc
1296 (TYPES_bh_data): New type for byte and halfword.
1297 (bh_data): Type array for byte and halfword.
1298 (h_data): Type array for halfword.
1299 * config/aarch64/aarch64-sve2.md
1300 (@aarch64_sve_luti<LUTI_BITS><mode>): Instruction patterns for
1301 lut intrinsics.
1302 * config/aarch64/iterators.md: Iterators and attributes for lut
1303 intrinsics.
1305 2025-01-21 Tamar Christina <tamar.christina@arm.com>
1307 PR middle-end/118273
1308 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use nvectors when
1309 doing mask registrations.
1311 2025-01-21 Tamar Christina <tamar.christina@arm.com>
1313 * config.gcc (aarch64-*-elf): Drop ILP32 from default multilibs.
1315 2025-01-21 Lulu Cheng <chenglulu@loongson.cn>
1317 * config/loongarch/loongarch-protos.h
1318 (loongarch_reset_previous_fndecl): Add function declaration.
1319 (loongarch_save_restore_target_globals): Likewise.
1320 (loongarch_register_pragmas): Likewise.
1321 * config/loongarch/loongarch-target-attr.cc
1322 (loongarch_option_valid_attribute_p): Optimize the processing
1323 of attributes.
1324 (loongarch_pragma_target_parse): New functions.
1325 (loongarch_register_pragmas): Likewise.
1326 * config/loongarch/loongarch.cc
1327 (loongarch_reset_previous_fndecl): New functions.
1328 (loongarch_set_current_function): When the old_tree is the same
1329 as the new_tree, the rules for using registers, etc.,
1330 are set according to the option values to ensure that the
1331 pragma can be processed correctly.
1332 * config/loongarch/loongarch.h (REGISTER_TARGET_PRAGMAS):
1333 Define macro.
1334 * doc/extend.texi: Supplemental Documentation.
1336 2025-01-21 Lulu Cheng <chenglulu@loongson.cn>
1338 * attr-urls.def: Regenerate.
1339 * config.gcc: Add loongarch-target-attr.o to extra_objs.
1340 * config/loongarch/loongarch-protos.h
1341 (loongarch_option_valid_attribute_p): Function declaration.
1342 (loongarch_option_override_internal): Likewise.
1343 * config/loongarch/loongarch.cc
1344 (loongarch_option_override_internal): Delete the modifications
1345 to target_option_default_node and target_option_current_node.
1346 (loongarch_set_current_function): Add annotation information.
1347 (loongarch_option_override): add assignment operations to
1348 target_option_default_node and target_option_current_node.
1349 (TARGET_OPTION_VALID_ATTRIBUTE_P): Define.
1350 * config/loongarch/t-loongarch: Add compilation of target file
1351 loongarch-target-attr.o.
1352 * doc/extend.texi: Add description information of LoongArch
1353 Function Attributes.
1354 * config/loongarch/loongarch-target-attr.cc: New file.
1356 2025-01-21 Alfie Richards <alfie.richards@arm.com>
1358 * config/aarch64/aarch64.cc
1359 (aarch64_process_target_version_attr): Add experimental warning.
1360 * config/aarch64/aarch64.opt: Add command line option to disable
1361 warning.
1362 * doc/invoke.texi: Add documentation for -W[no-]experimental-fmv-target.
1364 2025-01-20 Vladimir N. Makarov <vmakarov@redhat.com>
1366 PR target/118560
1367 * lra-constraints.cc (invalid_mode_reg_p): Exchange args in
1368 hard_reg_set_subset_p call.
1370 2025-01-20 Jeff Law <jlaw@ventanamicro.com>
1372 PR target/114442
1373 * config/riscv/xiangshan.md: Add missing insn types to a
1374 new dummy insn reservation.
1376 2025-01-20 Jeff Law <jlaw@ventanamicro.com>
1378 PR target/116256
1379 * config/riscv/riscv.md (reassocating constant addition): Adjust
1380 condition to avoid creating an unrecognizable insn.
1382 2025-01-20 Denis Chertykov <chertykov@gmail.com>
1384 PR rtl-optimization/117868
1385 * lra-spills.cc (assign_stack_slot_num_and_sort_pseudos): Reuse slots
1386 only without allocated memory or only with equal or smaller registers
1387 with equal or smaller alignment.
1388 (lra_spill): Print slot size as width.
1390 2025-01-20 Richard Sandiford <richard.sandiford@arm.com>
1392 PR tree-optimization/118348
1393 * tree-vectorizer.cc (vec_info::move_dr): Copy
1394 STMT_VINFO_SIMD_LANE_ACCESS_P.
1396 2025-01-20 Richard Sandiford <richard.sandiford@arm.com>
1398 Revert:
1399 2025-01-20 Richard Sandiford <richard.sandiford@arm.com>
1401 PR tree-optimization/118384
1402 * tree-vectorizer.cc (vec_info::move_dr): Copy
1403 STMT_VINFO_SIMD_LANE_ACCESS_P.
1405 2025-01-20 Richard Sandiford <richard.sandiford@arm.com>
1407 PR tree-optimization/118384
1408 * tree-vectorizer.cc (vec_info::move_dr): Copy
1409 STMT_VINFO_SIMD_LANE_ACCESS_P.
1411 2025-01-20 Richard Sandiford <richard.sandiford@arm.com>
1413 PR target/118501
1414 * config/aarch64/aarch64.md (@xorsign<mode>3): Use
1415 force_lowpart_subreg.
1417 2025-01-20 Richard Sandiford <richard.sandiford@arm.com>
1419 PR target/118531
1420 * config/aarch64/aarch64.md (*insv_reg<mode>_<SUBDI_BITS>)
1421 (*aarch64_bfi<GPI:mode><ALLX:mode>_<SUBDI_BITS>)
1422 (*aarch64_bfidi<ALLX:mode>_subreg_<SUBDI_BITS>): Add missing
1423 simd requirements.
1425 2025-01-20 Jin Ma <jinma@linux.alibaba.com>
1427 * config/riscv/thead.md (*th_cond_mov<GPR:mode><GPR2:mode>):
1428 Change GPR2 to X.
1429 (*th_cond_mov<GPR:mode>): Likewise.
1431 2025-01-20 Andrew Pinski <quic_apinski@quicinc.com>
1433 PR tree-optimization/118077
1434 PR tree-optimization/117668
1435 * tree-inline.cc (fold_marked_statements): Purge abnormal edges
1436 as needed.
1438 2025-01-20 Richard Biener <rguenther@suse.de>
1440 PR tree-optimization/117875
1441 * tree-vect-slp.cc (vect_build_slp_tree_1): Handle SSA copies.
1443 2025-01-20 Xi Ruoyao <xry111@xry111.site>
1445 PR target/115921
1446 * config/loongarch/loongarch-protos.h
1447 (loongarch_reassoc_shift_bitwise): New function prototype.
1448 * config/loongarch/loongarch.cc
1449 (loongarch_reassoc_shift_bitwise): Implement.
1450 * config/loongarch/loongarch.md
1451 (*alslsi3_extend_subreg): New define_insn_and_split.
1452 (<any_bitwise:optab>_shift_reverse<X:mode>): New
1453 define_insn_and_split.
1454 (<any_bitwise:optab>_alsl_reversesi_extended): New
1455 define_insn_and_split.
1456 (zero_extend_ashift): Remove as it's just a special case of
1457 and_shift_reversedi, and it does not make too much sense to
1458 write "alsl.d rd,rs,r0,shamt" instead of "slli.d rd,rs,shamt".
1459 (bstrpick_alsl_paired): Remove as it is already done by
1460 splitting and_shift_reversedi into and + ashift first, then
1461 late combining the ashift and a further add.
1463 2025-01-20 Xi Ruoyao <xry111@xry111.site>
1465 * config/loongarch/constraints.md (Yy): New define_constriant.
1466 * config/loongarch/loongarch.cc (loongarch_print_operand):
1467 For "%M", output the index of bits to be used with
1468 bstrins/bstrpick.
1469 * config/loongarch/predicates.md (ins_zero_bitmask_operand):
1470 Exclude low_bitmask_operand as for low_bitmask_operand it's
1471 always better to use bstrpick instead of bstrins.
1472 (and_operand): New define_predicate.
1473 * config/loongarch/loongarch.md (any_or): New
1474 define_code_iterator.
1475 (bitwise_operand): New define_code_attr.
1476 (*<optab:any_or><mode:GPR>3): New define_insn.
1477 (*and<mode:GPR>3): New define_insn.
1478 (<optab:any_bitwise><mode:X>3): New define_expand.
1479 (and<mode>3_extended): Remove, replaced by the 3rd alternative
1480 of *and<mode:GPR>3.
1481 (bstrins_<mode>_for_mask): Remove, replaced by the 4th
1482 alternative of *and<mode:GPR>3.
1483 (*<optab:any_bitwise>si3_internal): Remove, already covered by
1484 the *<optab:any_or><mode:GPR>3 and *and<mode:GPR>3 templates.
1486 2025-01-20 Richard Biener <rguenther@suse.de>
1488 PR tree-optimization/118552
1489 * cfgloopmanip.cc (fix_loop_placement): Properly mark
1490 exit source blocks as to be scanned for LC SSA update when
1491 the loops nesting relationship changed.
1492 (fix_loop_placements): Adjust.
1493 (fix_bb_placements): Likewise.
1495 2025-01-20 Thomas Schwinge <tschwinge@baylibre.com>
1497 * config/nvptx/t-nvptx (MULTILIB_OPTIONS): Don't add 'mptx=3.1' if
1498 neither sm_30 nor sm_35 multilib variant is built.
1500 2025-01-20 Jakub Jelinek <jakub@redhat.com>
1502 PR c++/118509
1503 * tree.cc (tree_invariant_p_1): Return true for TARGET_EXPR too.
1505 2025-01-20 Jakub Jelinek <jakub@redhat.com>
1507 PR tree-optimization/118224
1508 * tree-ssa-dce.cc (is_removable_allocation_p): Multiply a1 by a2
1509 instead of adding it.
1511 2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
1513 * config/s390/s390-builtins.def (s390_vec_load_len): Deprecate
1514 some overloads.
1515 (s390_vec_store_len): Deprecate some overloads.
1516 (s390_vec_load_len_r): Add.
1517 (s390_vec_store_len_r): Add.
1518 * config/s390/s390-c.cc (s390_vec_load_len_r): Add.
1519 (s390_vec_store_len_r): Add.
1520 * config/s390/vecintrin.h (vec_load_len_r): Redefine.
1521 (vec_store_len_r): Redefine.
1523 2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
1525 * config/s390/s390-builtins.def: Add 128-bit variants.
1526 * config/s390/s390-builtin-types.def: Update accordingly.
1527 * config/s390/vector.md (<vec_shifts_name><mode>3): Add 128-bit
1528 variants.
1529 * config/s390/vx-builtins.md: Ditto.
1531 2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
1533 * config/s390/s390-builtins.def: Add 128-bit variants and remove
1534 bool variants.
1535 * config/s390/s390-builtin-types.def: Update accordinly.
1536 * config/s390/s390.md: Emulate min/max for GPR.
1537 * config/s390/vector.md: Add min/max patterns and emulate in
1538 case of no VXE3.
1540 2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
1542 * config/s390/s390-builtins.def (s390_vec_abs_s128): Add.
1543 (s390_vlpq): Add.
1544 * config/s390/s390-builtin-types.def: Update accordingly.
1545 * config/s390/vector.md (abs<mode>2): Emulate w/o VXE3.
1546 (*abs<mode>2): Add 128-bit variant.
1547 (*vec_sel0<mode>): Make it a ...
1548 (vec_sel0<mode>): named pattern.
1550 2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
1552 * config/s390/s390-builtins.def: Add 128-bit variants.
1553 * config/s390/s390-builtin-types.def: Update accordingly.
1554 * config/s390/s390.cc (s390_expand_vec_compare_cc): Also
1555 consider TI modes for vectors.
1556 * config/s390/vector.md: Enable *vec_cmp et al. for VXE3.
1557 * config/s390/vx-builtins.md: Ditto.
1559 2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
1561 * config/s390/vector.md (div<mode>3): Add.
1562 (udiv<mode>3): Add.
1563 (mod<mode>3): Add.
1564 (umod<mode>3): Add.
1566 2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
1568 * config/s390/s390-builtins.def (s390_vec_cntlz): Add 128-bit
1569 integer overloads.
1570 (s390_vclzq): Add.
1571 (s390_vec_cnttz): Add 128-bit integer overloads.
1572 (s390_vctzq): Add.
1573 * config/s390/s390-builtin-types.def: Update accordingly.
1574 * config/s390/s390.h (CTZ_DEFINED_VALUE_AT_ZERO): Define.
1575 * config/s390/s390.md (*clzg): New insn.
1576 (clztidi2): Exploit new insn for target arch15.
1577 (ctzdi2): New insn.
1578 * config/s390/vector.md (clz<mode>2): Extend modes including
1579 128-bit integer.
1580 (ctz<mode>2): Likewise.
1582 2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
1584 * config/s390/s390-builtins.def (s390_vec_gen_element_masks_128): Add.
1585 (s390_vgemb): Add.
1586 (s390_vgemh): Add.
1587 (s390_vgemf): Add.
1588 (s390_vgemg): Add.
1589 (s390_vgemq): Add.
1590 * config/s390/s390-builtin-types.def: Update accordingly.
1591 * config/s390/s390.md (UNSPEC_VEC_VGEM): Add.
1592 * config/s390/vecintrin.h (vec_gen_element_masks_8): Define.
1593 (vec_gen_element_masks_16): Define.
1594 (vec_gen_element_masks_32): Define.
1595 (vec_gen_element_masks_64): Define.
1596 (vec_gen_element_masks_128): Define.
1597 * config/s390/vx-builtins.md (vgemv16qi): Add.
1598 (vgem<mode>): Add.
1600 2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
1602 * config/s390/s390-builtins.def (s390_vec_evaluate): Add.
1603 (s390_veval): Add.
1604 * config/s390/s390-builtin-types.def: Update accordingly.
1605 * config/s390/s390.md (UNSPEC_VEC_VEVAL): Add.
1606 * config/s390/vecintrin.h (vec_evaluate): Define.
1607 * config/s390/vector.md
1608 (*veval<mode>_<logic_op1:logic_op_stringify><logic_op2:logic_op_stringify>):
1609 Add.
1610 (veval<mode>): Add.
1612 2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
1614 * config/s390/s390-builtins.def (s390_vec_blend): Add.
1615 (s390_vblendb): Add.
1616 (s390_vblendh): Add.
1617 (s390_vblendf): Add.
1618 (s390_vblendg): Add.
1619 (s390_vblendq): Add.
1620 * config/s390/s390-builtin-types.def: Update accordingly.
1621 * config/s390/s390.md (UNSPEC_VEC_VBLEND): Add.
1622 * config/s390/vecintrin.h (vec_blend): Define.
1623 * config/s390/vx-builtins.md (vblend<mode>): Add.
1625 2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
1627 * config/s390/s390-builtins.def (s390_bdepg): Add.
1628 (s390_bextg): Add.
1629 * config/s390/s390-builtin-types.def: Update accordingly.
1630 * config/s390/s390.md (UNSPEC_BDEPG): Add.
1631 (UNSPEC_BEXTG): Add.
1632 (bdepg): Add.
1633 (bextg): Add.
1635 2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
1637 * config/s390/s390.md (*lxa<LXAMODE>_index): Add.
1638 (*lxa<LXAMODE>_displacement_index): Add.
1639 (*lxa<LXAMODE>_index_base): Add.
1640 (*lxa<LXAMODE>_displacement_index_base): Add.
1641 (*lxab_displacement_index_base): Add.
1642 (*llxa<LXAMODE>_displacement_index): Add.
1643 (*llxa<LXAMODE>_index_base): Add.
1644 (*llxa<LXAMODE>_displacement_index_base): Add.
1645 (*llxab_displacement_index_base): Add.
1647 2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
1649 * config/s390/s390-builtins.def: Add new instruction variants.
1650 * config/s390/s390-builtin-types.def: Update accordingly.
1651 * config/s390/vecintrin.h: Add new defines.
1652 * config/s390/vector.md: Adapt insns for new instruction
1653 variants.
1654 * config/s390/vx-builtins.md: Ditto.
1656 2025-01-20 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1658 * config/s390/s390-builtins.def (B_VXE3): Define.
1659 (B_ARCH15): Define.
1660 * config/s390/s390-c.cc (s390_resolve_overloaded_builtin):
1661 Consistency checks for VXE3.
1662 * config/s390/s390.cc (s390_expand_builtin): Consistency checks
1663 for VXE3.
1665 2025-01-20 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1667 * config/s390/s390-c.cc (rid_int128): New helper function.
1668 (s390_macro_to_expand): Deal with `vector __int128`.
1669 (s390_cpu_cpp_builtins_internal): Bump __VEC__.
1670 * config/s390/s390.cc (s390_handle_vectorbool_attribute): Add
1671 128-bit bool zvector.
1673 2025-01-20 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1675 * common/config/s390/s390-common.cc: Add arch15 processor flags.
1676 * config.gcc: Add arch15 for options --with-{arch,mtune}.
1677 * config/s390/driver-native.cc (s390_host_detect_local_cpu):
1678 Default to arch15.
1679 * config/s390/s390-opts.h (enum processor_type): Add
1680 PROCESSOR_ARCH15.
1681 * config/s390/s390.cc (processor_table,s390_issue_rate,
1682 s390_get_sched_attrmask,s390_get_unit_mask): Add arch15.
1683 * config/s390/s390.h (enum processor_flags): Add processor flags
1684 for VXE3 and ARCH15.
1685 (TARGET_CPU_VXE3): Define.
1686 (TARGET_CPU_VXE3_P): Define.
1687 (TARGET_CPU_ARCH15): Define.
1688 (TARGET_CPU_ARCH15_P): Define.
1689 (TARGET_VXE3): Define.
1690 (TARGET_VXE3_P): Define.
1691 (TARGET_ARCH15): Define.
1692 (TARGET_ARCH15_P): Define.
1693 * config/s390/s390.md: Add VXE3 and ARCH15 to cpu_facility, and
1694 let attribute "enabled" deal with them.
1695 * config/s390/s390.opt: Add arch15.
1697 2025-01-20 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1699 * config/s390/vecintrin.h: Sort definitions.
1701 2025-01-20 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
1703 * config/s390/vector.md: Stay scalar for TOINTVEC/tointvec.
1705 2025-01-20 Kito Cheng <kito.cheng@sifive.com>
1707 * config.gcc (riscv*): Install sifive_vector.h.
1708 * config/riscv/sifive_vector.h: New.
1710 2025-01-20 Hongyu Wang <hongyu.wang@intel.com>
1712 PR target/118510
1713 * config/i386/i386.md (*x86_64_shld_ndd_2): Use register_operand
1714 for operand[0] and adjust the output template to directly
1715 generate ndd form shld pattern.
1716 (*x86_shld_ndd_2): Likewise.
1717 (*x86_64_shrd_ndd_2): Likewise.
1718 (*x86_shrd_ndd_2): Likewise.
1720 2025-01-19 Uros Bizjak <ubizjak@gmail.com>
1722 * config/i386/i386.md (*movdi_internal): Reorder ISA attribute
1723 by ascending alternative index.
1725 2025-01-19 Mark Wielaard <mark@klomp.org>
1727 * config/sparc/sparc.opt.urls: Regenerated.
1729 2025-01-19 Gerald Pfeifer <gerald@pfeifer.com>
1731 * doc/gm2.texi (Type compatibility): Move modula2.org link
1732 to https.
1734 2025-01-19 Gerald Pfeifer <gerald@pfeifer.com>
1736 * doc/extend.texi (OpenMP): Adjust link to specifications.
1738 2025-01-18 Jeff Law <jlaw@ventanamicro.com>
1740 PR target/116308
1741 * config/riscv/riscv.cc (riscv_lshift_subword): Use gen_lowpart
1742 rather than simplify_gen_subreg.
1744 2025-01-18 Michal Jires <mjires@suse.cz>
1746 * cgraph.cc (symbol_table::create_empty):
1747 Move uid to symtab_node.
1748 (test_symbol_table_test): Change expected dump id.
1749 * cgraph.h (struct cgraph_node):
1750 Move uid to symtab_node.
1751 (symbol_table::register_symbol): Likewise.
1752 * dumpfile.cc (test_capture_of_dump_calls):
1753 Change expected dump id.
1754 * ipa-inline.cc (update_caller_keys):
1755 Use summary id instead of uid.
1756 (update_callee_keys): Likewise.
1757 * symtab.cc (symtab_node::get_dump_name):
1758 Use uid instead of order.
1760 2025-01-18 Eric Botcazou <ebotcazou@adacore.com>
1762 PR target/118512
1763 * config/sparc/sparc-c.cc (sparc_target_macros): Deal with VIS 3B.
1764 * config/sparc/sparc.cc (dump_target_flag_bits): Likewise.
1765 (sparc_option_override): Likewise.
1766 (sparc_vis_init_builtins): Likewise.
1767 * config/sparc/sparc.md (fpcmp_vis): Replace TARGET_VIS3 with
1768 TARGET_VIS3B.
1769 (vec_cmp): Likewise.
1770 (fpcmpu_vis): Likewise.
1771 (vec_cmpu): Likewise.
1772 (vcond_mask_): Likewise.
1773 * config/sparc/sparc.opt (VIS3B): New target mask.
1774 * doc/invoke.texi (SPARC options): Document -mvis3b.
1776 2025-01-18 Jin Ma <jinma@linux.alibaba.com>
1778 PR target/118357
1779 * config/riscv/riscv-vsetvl.cc: Function change_vtype_only_p always
1780 returns false for XTheadVector.
1782 2025-01-18 Richard Biener <rguenther@suse.de>
1784 PR tree-optimization/118529
1785 * tree-vect-stmts.cc (vectorizable_condition): Check the
1786 shape of the vector and condition vector type are compatible.
1788 2025-01-18 Georg-Johann Lay <avr@gjlay.de>
1790 * doc/invoke.texi (AVR Options): Fix plenk at -msplit-ldst.
1792 2025-01-18 Akram Ahmad <Akram.Ahmad@arm.com>
1793 Tamar Christina <tamar.christina@arm.com>
1795 * config/aarch64/aarch64-builtins.cc: Expand iterators.
1796 * config/aarch64/aarch64-simd-builtins.def: Use standard names
1797 * config/aarch64/aarch64-simd.md: Use standard names, split insn
1798 definitions on signedness of operator and type of operands.
1799 * config/aarch64/arm_neon.h: Use standard builtin names.
1800 * config/aarch64/iterators.md: Add VSDQ_I_QI_HI iterator to
1801 simplify splitting of insn for unsigned scalar arithmetic.
1803 2025-01-18 Akram Ahmad <Akram.Ahmad@arm.com>
1805 * config/aarch64/aarch64-sve.md: Rename insns
1807 2025-01-18 Tamar Christina <tamar.christina@arm.com>
1809 Revert:
1810 2025-01-17 Tamar Christina <tamar.christina@arm.com>
1812 * config/aarch64/aarch64-builtins.cc: Expand iterators.
1813 * config/aarch64/aarch64-simd-builtins.def: Use standard names
1814 * config/aarch64/aarch64-simd.md: Use standard names, split insn
1815 definitions on signedness of operator and type of operands.
1816 * config/aarch64/arm_neon.h: Use standard builtin names.
1817 * config/aarch64/iterators.md: Add VSDQ_I_QI_HI iterator to
1818 simplify splitting of insn for unsigned scalar arithmetic.
1820 2025-01-18 Tamar Christina <tamar.christina@arm.com>
1822 Revert:
1823 2025-01-17 Tamar Christina <tamar.christina@arm.com>
1825 * config/aarch64/aarch64-sve.md: Rename insns
1827 2025-01-18 Monk Chiang <monk.chiang@sifive.com>
1829 * config/riscv/riscv.cc: Remove unused variable.
1831 2025-01-18 Xi Ruoyao <xry111@xry111.site>
1833 * config/loongarch/loongarch.cc (loongarch_rtx_costs): Fix the
1834 cost for (a + b * imm) and (a + (b << imm)) which can be
1835 implemented with a single alsl instruction.
1837 2025-01-18 Xi Ruoyao <xry111@xry111.site>
1839 * config/loongarch/loongarch.md (alslsi3_extend): Add alsl.wu.
1841 2025-01-17 Vladimir N. Makarov <vmakarov@redhat.com>
1843 PR rtl-optimization/118067
1844 * lra-constraints.cc (invalid_mode_reg_p): New function.
1845 (curr_insn_transform): Use it to check mode returned by target
1846 secondary_memory_needed_mode.
1848 2025-01-17 Jakub Jelinek <jakub@redhat.com>
1850 PR target/118511
1851 * config/s390/s390.cc (print_operand) <case 'p'>: Use
1852 output_operand_lossage instead of gcc_checking_assert.
1853 (print_operand) <case 'q'>: Likewise.
1854 (print_operand) <case 'r'>: Likewise.
1856 2025-01-17 Tamar Christina <tamar.christina@arm.com>
1858 * config/aarch64/aarch64-sve.md: Rename insns
1860 2025-01-17 Tamar Christina <tamar.christina@arm.com>
1862 * config/aarch64/aarch64-builtins.cc: Expand iterators.
1863 * config/aarch64/aarch64-simd-builtins.def: Use standard names
1864 * config/aarch64/aarch64-simd.md: Use standard names, split insn
1865 definitions on signedness of operator and type of operands.
1866 * config/aarch64/arm_neon.h: Use standard builtin names.
1867 * config/aarch64/iterators.md: Add VSDQ_I_QI_HI iterator to
1868 simplify splitting of insn for unsigned scalar arithmetic.
1870 2025-01-17 Carl Love <cel@linux.ibm.com>
1872 * config/rs6000/rs6000-builtins.def (__builtin_vsx_xvcvuxwdp):
1873 Remove built-in definition.
1875 2025-01-17 Carl Love <cel@linux.ibm.com>
1877 * config/rs6000/rs6000-builtins.def (__builtin_vsx_vperm_8hi,
1878 __builtin_vsx_vperm_8hi_uns): Remove built-in definitions.
1880 2025-01-17 Carl Love <cel@linux.ibm.com>
1882 * doc/extend.texi: Fix spelling mistake in description of the
1883 vec_sel built-in. Add documentation of the 128-bit vec_perm
1884 instance.
1886 2025-01-17 Georg-Johann Lay <avr@gjlay.de>
1888 * config/avr/avr-c.cc (DEF_BUILTIN): Add ATTRS argument to macro
1889 definition.
1890 * config/avr/avr.cc: Same.
1891 (avr_init_builtins) <attr_const>: New variable that can be used
1892 as ATTRS argument in DEF_BUILTIN.
1893 * config/avr/builtins.def (DEF_BUILTIN): Add ATTRS parameter
1894 to all definitions.
1896 2025-01-17 Georg-Johann Lay <avr@gjlay.de>
1898 PR target/118329
1899 * config/avr/avr-modes.def: Add INT_N (PSI, 24).
1900 * config/avr/avr.cc (avr_init_builtin_int24)
1901 <__int24>: Remove definition.
1902 <__uint24>: Adjust definition to INT_N interface.
1904 2025-01-17 Jakub Jelinek <jakub@redhat.com>
1906 PR tree-optimization/118522
1907 * match.pd ((FTYPE) N CMP (FTYPE) M): Add convert, as in GENERIC
1908 integral types with the same precision and sign might actually not
1909 be compatible types.
1911 2025-01-17 Richard Biener <rguenther@suse.de>
1913 PR tree-optimization/92539
1914 * tree-ssa-loop-ivcanon.cc (tree_unroll_loops_completely_1):
1915 Also try force-evaluation if ivcanon did not yet run.
1916 (canonicalize_loop_induction_variables):
1917 When niter was computed constant by force evaluation add a
1918 canonical IV if we didn't unroll.
1919 * tree-ssa-loop-niter.cc (loop_niter_by_eval): When we
1920 don't find a proper PHI try if the exit condition scans
1921 over a STRING_CST and simulate that.
1923 2025-01-17 Monk Chiang <monk.chiang@sifive.com>
1925 * config/riscv/riscv.cc
1926 (is_zicfilp_p): New function.
1927 (is_zicfiss_p): New function.
1928 * config/riscv/riscv-zicfilp.cc: Update.
1929 * config/riscv/riscv.h: Update.
1930 * config/riscv/riscv.md: Update.
1931 * config/riscv/riscv-c.cc: Add CFI predefine marco.
1933 2025-01-17 Monk Chiang <monk.chiang@sifive.com>
1935 * config/riscv/riscv.cc
1936 (riscv_file_end): Add .note.gnu.property.
1938 2025-01-17 Monk Chiang <monk.chiang@sifive.com>
1940 * common/config/riscv/riscv-common.cc: Add ZICFILP ISA
1941 string.
1942 * config.gcc: Add riscv-zicfilp.o
1943 * config/riscv/riscv-passes.def (INSERT_PASS_BEFORE):
1944 Insert landing pad instructions.
1945 * config/riscv/riscv-protos.h (make_pass_insert_landing_pad):
1946 Declare.
1947 * config/riscv/riscv-zicfilp.cc: New file.
1948 * config/riscv/riscv.cc
1949 (riscv_trampoline_init): Add landing pad instructions.
1950 (riscv_legitimize_call_address): Likewise.
1951 (riscv_output_mi_thunk): Likewise.
1952 * config/riscv/riscv.h: Update.
1953 * config/riscv/riscv.md: Add landing pad patterns.
1954 * config/riscv/riscv.opt (TARGET_ZICFILP): Define.
1955 * config/riscv/t-riscv: Add build rule for
1956 riscv-zicfilp.o
1958 2025-01-17 Monk Chiang <monk.chiang@sifive.com>
1960 * common/config/riscv/riscv-common.cc: Add ZICFISS ISA string.
1961 * config/riscv/predicates.md: New predicate x1x5_operand.
1962 * config/riscv/riscv.cc
1963 (riscv_expand_prologue): Insert shadow stack instructions.
1964 (riscv_expand_epilogue): Likewise.
1965 (riscv_for_each_saved_reg): Assign t0 or ra register for
1966 sspopchk instruction.
1967 (need_shadow_stack_push_pop_p): New function. Omit shadow
1968 stack operation on leaf function.
1969 * config/riscv/riscv.h
1970 (need_shadow_stack_push_pop_p): Define.
1971 * config/riscv/riscv.md: Add shadow stack patterns.
1972 (save_stack_nonlocal): Add shadow stack instructions for setjump.
1973 (restore_stack_nonlocal): Add shadow stack instructions for longjump.
1974 * config/riscv/riscv.opt (TARGET_ZICFISS): Define.
1976 2025-01-16 Tamar Christina <tamar.christina@arm.com>
1977 Richard Sandiford <richard.sandiford@arm.com>
1979 PR target/113257
1980 * config/aarch64/driver-aarch64.cc (get_cpu_from_id, DEFAULT_CPU): New.
1981 (host_detect_local_cpu): Use it.
1983 2025-01-16 Tamar Christina <tamar.christina@arm.com>
1985 PR target/110901
1986 * config/aarch64/aarch64.h (MCPU_TO_MARCH_SPEC): Don't override if
1987 march is set.
1989 2025-01-16 Vladimir N. Makarov <vmakarov@redhat.com>
1991 PR rtl-optimization/1180167
1992 * lra-constraints.cc (process_alt_operands): Use operand mode not
1993 subreg reg mode. Add and improve debugging prints for updating
1994 losers.
1996 2025-01-16 Sandra Loosemore <sloosemore@baylibre.com>
1998 * omp-general.cc (omp_complete_construct_context): Check
1999 "omp declare target" attribute, not "omp declare target block".
2001 2025-01-16 Peter Bergner <bergner@linux.ibm.com>
2003 * config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Return
2004 const0_rtx when there is an error.
2006 2025-01-16 Peter Bergner <bergner@linux.ibm.com>
2008 * config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Use correct
2009 array size for the loop limit.
2010 * config/rs6000/rs6000-builtins.def: Fix field size for PMASK operand.
2012 2025-01-16 Liao Shihua <shihua@iscas.ac.cn>
2014 * config/riscv/vector.md: New attr set.
2016 2025-01-16 Jiawei <jiawei@iscas.ac.cn>
2018 * config/riscv/genrvv-type-indexer.cc (expand_floattype): New func.
2019 (main): New type.
2020 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_XFQF_OPS): New def.
2021 (vint8mf8_t): Ditto.
2022 (vint8mf4_t): Ditto.
2023 (vint8mf2_t): Ditto.
2024 (vint8m1_t): Ditto.
2025 (vint8m2_t): Ditto.
2026 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_XFQF_OPS): Ditto.
2027 (rvv_arg_type_info::get_xfqf_float_type): Ditto.
2028 * config/riscv/riscv-vector-builtins.def (xfqf_vector): Ditto.
2029 (xfqf_float): Ditto.
2030 * config/riscv/riscv-vector-builtins.h
2031 (struct rvv_arg_type_info): New function prototype.
2032 * config/riscv/sifive-vector.md: Update iterator.
2033 * config/riscv/vector-iterators.md: Ditto.
2035 2025-01-16 Christoph Mรผllner <christoph.muellner@vrull.eu>
2037 PR tree-optimization/118487
2038 * tree-ssa-forwprop.cc (recognise_vec_perm_simplify_seq):
2039 Ensure that shuffle masks are VECTOR_CSTs.
2041 2025-01-16 Christoph Mรผllner <christoph.muellner@vrull.eu>
2043 * tree-ssa-forwprop.cc (recognise_vec_perm_simplify_seq):
2044 Eliminate redundant calls to to_constant().
2046 2025-01-16 Richard Biener <rguenther@suse.de>
2047 Mikael Morin <mikael@gcc.gnu.org>
2049 PR tree-optimization/115494
2050 * tree-ssa-pre.cc (phi_translate_1): Always generate a
2051 representative for translated dependent expressions.
2053 2025-01-16 Jakub Jelinek <jakub@redhat.com>
2055 PR tree-optimization/118430
2056 * tree-ssa-propagate.cc (may_propagate_copy): Return false if dest
2057 is lhs of an [[gnu::musttail]] call.
2058 (substitute_and_fold_dom_walker::before_dom_children): Formatting fix.
2060 2025-01-16 Jakub Jelinek <jakub@redhat.com>
2061 Andrew Pinski <quic_apinski@quicinc.com>
2063 PR tree-optimization/118430
2064 * tree-tailcall.cc: Include gimple-range.h, alloc-pool.h, sreal.h,
2065 symbol-summary.h, ipa-cp.h and ipa-prop.h.
2066 (find_tail_calls): If ass_var is NULL and ret_var is not, check if
2067 IPA-VRP has not found singleton return range for it. In that case,
2068 don't punt if ret_var is the only value in that range. Adjust the
2069 maybe_error_musttail message otherwise to diagnose different value
2070 being returned from the caller and callee rather than using return
2071 slot. Formatting fixes.
2073 2025-01-16 Jakub Jelinek <jakub@redhat.com>
2075 * doc/extend.texi (Using Assembly Language with C): Add Asm constexprs
2076 to @menu.
2077 (Basic Asm): Move @node asm constexprs before Asm Labels, rename to
2078 Asm constexprs, change wording so that it is clearer that the constant
2079 expression actually must not return a string literal, just some specific
2080 container and other wording tweaks. Only talk about top-level for basic
2081 asms in this @node, move restrictions on top-level extended asms to ...
2082 (Extended Asm): ... here.
2084 2025-01-16 Jakub Jelinek <jakub@redhat.com>
2086 PR ipa/118400
2087 * vec.h (vec<T, va_heap, vl_ptr>::release): Call m_vec->truncate (0)
2088 instead of clearing m_vec->m_vecpfx.m_num.
2090 2025-01-16 liuhongt <hongtao.liu@intel.com>
2092 PR target/118489
2093 * config/i386/sse.md (VF1_AVX512BW): Fix typo.
2095 2025-01-16 Richard Biener <rguenther@suse.de>
2097 PR tree-optimization/115895
2098 * tree-vect-stmts.cc (get_group_load_store_type): When we
2099 might overrun because the group size is not a multiple of the
2100 vector size we cannot use loop masking since that does not
2101 implement the required load shortening.
2103 2025-01-16 Keith Packard <keithp@keithp.com>
2105 * config/lm32/lm32.cc: Add several #includes.
2106 (va_list_type): New.
2107 (lm32_build_va_list): New function.
2108 (lm32_builtin_va_start): Likewise.
2109 (lm32_sd_gimplify_va_arg_expr): Likewise.
2110 (lm32_gimplify_va_arg_expr): Likewise.
2112 2025-01-16 Keith Packard <keithp@keithp.com>
2114 * config/lm32/lm32.cc (setup_incoming_varargs): Adjust the
2115 conditionals so that pretend_size is always computed, even
2116 if no_rtl is set.
2118 2025-01-16 Keith Packard <keithp@keithp.com>
2120 * config/lm32/lm32.cc (lm32_setup_incoming_varargs): Skip last
2121 named parameter when preparing to flush registers with unnamed
2122 arguments to th stack.
2124 2025-01-16 Keith Packard <keithp@keithp.com>
2126 * config/lm32/lm32.cc (lm32_function_arg): Pass unnamed
2127 arguments in registers too, just like named arguments.
2129 2025-01-16 Andi Kleen <ak@gcc.gnu.org>
2131 * config/i386/x86-tune-sched-core.cc: Fix incorrect comment.
2133 2025-01-16 Eugene Rozenfeld <erozen@microsoft.com>
2135 PR gcov-profile/116743
2136 * auto-profile.cc (afdo_annotate_cfg): Fix mismatch between the call graph node count
2137 and the entry block count.
2139 2025-01-15 Andrew Pinski <quic_apinski@quicinc.com>
2141 PR tree-optimization/102705
2142 * match.pd (`(1 >> X) != 0`): Remove pattern.
2143 (`1 >> x`): New pattern.
2145 2025-01-15 Sam James <sam@gentoo.org>
2147 * doc/extend.texi: Cleanup trailing whitespace.
2149 2025-01-15 Sam James <sam@gentoo.org>
2151 * doc/extend.texi: Add 'a' for grammar fix.
2153 2025-01-15 Wilco Dijkstra <wilco.dijkstra@arm.com>
2155 * config/aarch64/tuning_models/neoverse512tvb.h (tune_flags): Update.
2157 2025-01-15 Wilco Dijkstra <wilco.dijkstra@arm.com>
2159 * config/aarch64/aarch64-tuning-flags.def (AARCH64_EXTRA_TUNE_BASE):
2160 Add AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
2161 * config/aarch64/tuning_models/ampere1b.h: Remove redundant
2162 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
2163 * config/aarch64/tuning_models/neoversev2.h: Likewise.
2165 2025-01-15 Wilco Dijkstra <wilco.dijkstra@arm.com>
2167 * config/aarch64/aarch64.cc (aarch64_override_options): Add warning.
2168 * doc/invoke.texi: Document -mabi=ilp32 as deprecated.
2170 2025-01-15 Cupertino Miranda <cupertino.miranda@oracle.com>
2172 * config/bpf/core-builtins.cc (compute_field_expr): Change
2173 VAR_DECL outcome in switch case.
2175 2025-01-15 Cupertino Miranda <cupertino.miranda@oracle.com>
2177 * config/bpf/core-builtins.cc
2178 (make_gimple_core_safe_access_index): Fix in condition.
2180 2025-01-15 Cupertino Miranda <cupertino.miranda@oracle.com>
2182 * btfout.cc (get_btf_kind): Remove static from function definition.
2183 * config/bpf/btfext-out.cc (bpf_code_reloc_add): Check if CO-RE type
2184 is not a const or volatile.
2185 * ctfc.h (btf_dtd_kind): Add prototype for function.
2187 2025-01-15 Tamar Christina <tamar.christina@arm.com>
2189 PR middle-end/118472
2190 * fold-const.cc (operand_compare::operand_equal_p): Fix incorrect
2191 replacement.
2193 2025-01-15 Richard Biener <rguenther@suse.de>
2195 * genmatch.cc (define_dump_logs): Make reverse lookup in
2196 dbg_line_numbers easier by adding comments with start index
2197 and cutting number of elements per line to 10.
2199 2025-01-15 Jakub Jelinek <jakub@redhat.com>
2201 PR ipa/116068
2202 * cgraphunit.cc (symbol_table::process_new_functions): Call
2203 bitmap_obstack_initialize (NULL); and bitmap_obstack_release (NULL)
2204 around processing the functions.
2206 2025-01-15 Kito Cheng <kito.cheng@sifive.com>
2208 PR target/118182
2209 * config/riscv/autovec-opt.md (*widen_reduc_plus_scal_<mode>): Adjust
2210 argument for expand_reduction.
2211 (*widen_reduc_plus_scal_<mode>): Ditto.
2212 (*fold_left_widen_plus_<mode>): Ditto.
2213 (*mask_len_fold_left_widen_plus_<mode>): Ditto.
2214 (*cond_widen_reduc_plus_scal_<mode>): Ditto.
2215 (*cond_len_widen_reduc_plus_scal_<mode>): Ditto.
2216 (*cond_widen_reduc_plus_scal_<mode>): Ditto.
2217 * config/riscv/autovec.md (reduc_plus_scal_<mode>): Adjust argument for
2218 expand_reduction.
2219 (reduc_smax_scal_<mode>): Ditto.
2220 (reduc_umax_scal_<mode>): Ditto.
2221 (reduc_smin_scal_<mode>): Ditto.
2222 (reduc_umin_scal_<mode>): Ditto.
2223 (reduc_and_scal_<mode>): Ditto.
2224 (reduc_ior_scal_<mode>): Ditto.
2225 (reduc_xor_scal_<mode>): Ditto.
2226 (reduc_plus_scal_<mode>): Ditto.
2227 (reduc_smax_scal_<mode>): Ditto.
2228 (reduc_smin_scal_<mode>): Ditto.
2229 (reduc_fmax_scal_<mode>): Ditto.
2230 (reduc_fmin_scal_<mode>): Ditto.
2231 (fold_left_plus_<mode>): Ditto.
2232 (mask_len_fold_left_plus_<mode>): Ditto.
2233 * config/riscv/riscv-v.cc (expand_reduction): Add one more
2234 argument for reduction code for vl0-safe.
2235 * config/riscv/riscv-protos.h (expand_reduction): Ditto.
2236 * config/riscv/vector-iterators.md (unspec): Add _VL0_SAFE variant of
2237 reduction.
2238 (ANY_REDUC_VL0_SAFE): New.
2239 (ANY_WREDUC_VL0_SAFE): Ditto.
2240 (ANY_FREDUC_VL0_SAFE): Ditto.
2241 (ANY_FREDUC_SUM_VL0_SAFE): Ditto.
2242 (ANY_FWREDUC_SUM_VL0_SAFE): Ditto.
2243 (reduc_op): Add _VL0_SAFE variant of reduction.
2244 (order) Ditto.
2245 * config/riscv/vector.md (@pred_<reduc_op><mode>): New.
2247 2025-01-15 Richard Biener <rguenther@suse.de>
2249 PR tree-optimization/115777
2250 * tree-vect-slp.cc (vect_bb_slp_scalar_cost): Do not
2251 cost a scalar stmt that needs to be preserved.
2253 2025-01-15 Michal Jires <mjires@suse.cz>
2255 PR lto/118238
2256 * lto-wrapper.cc (run_gcc): Remove link() copying.
2258 2025-01-15 Anton Blanchard <antonb@tenstorrent.com>
2259 Jeff Law <jlaw@ventanamicro.com>
2261 PR target/118170
2262 * config/riscv/generic-ooo.md (generic_ooo_float_div_half): New
2263 reservation.
2265 2025-01-15 Richard Sandiford <richard.sandiford@arm.com>
2266 Jeff Law <jlaw@ventanamicro.com>
2268 PR rtl-optimization/109592
2269 * simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
2270 Simplify nested shifts with subregs.
2272 2025-01-14 anetczuk <anetczuk@o2.pl>
2274 * tree-dump.cc (dequeue_and_dump): Handle OBJ_TYPE_REF.
2276 2025-01-14 Alexandre Oliva <oliva@adacore.com>
2278 * gimple-fold.cc (decode_field_reference): Rebustify to set
2279 out parms only when returning non-NULL.
2280 (fold_truth_andor_for_ifcombine): Bail if
2281 decode_field_reference returns NULL. Add complementary assert
2282 on r_const's not being set when l_const isn't.
2284 2025-01-14 Sandra Loosemore <sloosemore@baylibre.com>
2286 * cgraph.cc (symbol_table::create_edge): Don't set
2287 calls_declare_variant_alt in the caller.
2288 * cgraph.h (struct cgraph_node): Remove declare_variant_alt
2289 and calls_declare_variant_alt flags.
2290 * cgraphclones.cc (cgraph_node::create_clone): Don't copy
2291 calls_declare_variant_alt bit.
2292 * gimplify.cc: Remove previously #ifdef-ed out code.
2293 * ipa-free-lang-data.cc (free_lang_data_in_decl): Adjust code
2294 referencing declare_variant_alt bit.
2295 * ipa.cc (symbol_table::remove_unreachable_nodes): Likewise.
2296 * lto-cgraph.cc (lto_output_node): Remove references to deleted
2297 bits.
2298 (output_refs): Adjust code referencing declare_variant_alt bit.
2299 (input_overwrite_node): Remove references to deleted bits.
2300 (input_refs): Adjust code referencing declare_variant_alt bit.
2301 * lto-streamer-out.cc (lto_output): Likewise.
2302 * lto-streamer.h (omp_lto_output_declare_variant_alt): Delete.
2303 (omp_lto_input_declare_variant_alt): Delete.
2304 * omp-expand.cc (expand_omp_target): Use has_omp_variant_constructs
2305 bit to trigger pass_omp_device_lower instead of
2306 calls_declare_variant_alt.
2307 * omp-general.cc (struct omp_declare_variant_entry): Delete.
2308 (struct omp_declare_variant_base_entry): Delete.
2309 (struct omp_declare_variant_hasher): Delete.
2310 (omp_declare_variant_hasher::hash): Delete.
2311 (omp_declare_variant_hasher::equal): Delete.
2312 (omp_declare_variants): Delete.
2313 (omp_declare_variant_alt_hasher): Delete.
2314 (omp_declare_variant_alt_hasher::hash): Delete.
2315 (omp_declare_variant_alt_hasher::equal): Delete.
2316 (omp_declare_variant_alt): Delete.
2317 (omp_lto_output_declare_variant_alt): Delete.
2318 (omp_lto_input_declare_variant_alt): Delete.
2319 (includes): Delete unnecessary include of gt-omp-general.h.
2320 * omp-offload.cc (execute_omp_device_lower): Remove references
2321 to deleted bit.
2322 (pass_omp_device_lower::gate): Likewise.
2323 * omp-simd-clone.cc (simd_clone_create): Likewise.
2324 * passes.cc (ipa_write_summaries): Likeise.
2325 * symtab.cc (symtab_node::get_partitioning_class): Likewise.
2326 * tree-inline.cc (expand_call_inline): Likewise.
2327 (tree_function_versioning): Likewise.
2329 2025-01-14 Sandra Loosemore <sloosemore@baylibre.com>
2330 Kwok Cheung Yeung <kcy@codesourcery.com>
2331 Sandra Loosemore <sandra@codesourcery.com>
2332 Marcel Vollweiler <marcel@codesourcery.com>
2334 PR middle-end/114596
2335 PR middle-end/112779
2336 PR middle-end/113904
2337 * Makefile.in (GTFILES): Move omp-general.h earlier; required
2338 because of moving score_wide_int declaration to that file.
2339 * cgraph.h (struct cgraph_node): Add has_omp_variant_constructs flag.
2340 * cgraphclones.cc (cgraph_node::create_clone): Propagate
2341 has_omp_variant_constructs flag.
2342 * gimplify.cc (omp_resolved_variant_calls): New.
2343 (expand_late_variant_directive): New.
2344 (find_supercontext): New.
2345 (gimplify_variant_call_expr): New.
2346 (gimplify_call_expr): Adjust parameters to make fallback available.
2347 Update processing for "declare variant" substitution.
2348 (is_gimple_stmt): Add OMP_METADIRECTIVE.
2349 (omp_construct_selector_matches): Ifdef out unused function.
2350 (omp_get_construct_context): New.
2351 (gimplify_omp_dispatch): Replace call to deleted function
2352 omp_resolve_declare_variant with equivalent logic.
2353 (expand_omp_metadirective): New.
2354 (expand_late_variant_directive): New.
2355 (gimplify_omp_metadirective): New.
2356 (gimplify_expr): Adjust arguments to gimplify_call_expr. Add
2357 cases for OMP_METADIRECTIVE, OMP_NEXT_VARIANT, and
2358 OMP_TARGET_DEVICE_MATCHES.
2359 (gimplify_function_tree): Initialize/clean up
2360 omp_resolved_variant_calls.
2361 * gimplify.h (omp_construct_selector_matches): Delete declaration.
2362 (omp_get_construct_context): Declare.
2363 * lto-cgraph.cc (lto_output_node): Write has_omp_variant_constructs.
2364 (input_overwrite_node): Read has_omp_variant_constructs.
2365 * omp-builtins.def (BUILT_IN_OMP_GET_NUM_DEVICES): New.
2366 * omp-expand.cc (expand_omp_taskreg): Propagate
2367 has_omp_variant_constructs.
2368 (expand_omp_target): Likewise.
2369 * omp-general.cc (omp_maybe_offloaded): Add construct_context
2370 parameter; use it instead of querying gimplifier state. Add
2371 comments.
2372 (omp_context_name_list_prop): Do not test lang_GNU_Fortran in
2373 offload compiler, just use the string as-is.
2374 (expr_uses_parm_decl): New.
2375 (omp_check_context_selector): Add metadirective_p parameter.
2376 Remove sorry for target_device selector. Add additional checks
2377 specific to metadirective or declare variant.
2378 (make_omp_metadirective_variant): New.
2379 (omp_construct_traits_match): New.
2380 (omp_context_selector_matches): Temporarily ifdef out the previous
2381 code, and add a new implementation based on the old one with
2382 different parameters, some unnecessary loops removed, and code
2383 re-indented.
2384 (omp_target_device_matches_on_host): New.
2385 (resolve_omp_target_device_matches): New.
2386 (omp_construct_simd_compare): Support matching of "simdlen" and
2387 "aligned" clauses.
2388 (omp_context_selector_set_compare): Make static. Adjust call to
2389 omp_construct_simd_compare.
2390 (score_wide_int): Move declaration to omp-general.h.
2391 (omp_selector_is_dynamic): New.
2392 (omp_device_num_check): New.
2393 (omp_dynamic_cond): New.
2394 (omp_context_compute_score): Ifdef out the old version and
2395 re-implement with different parameters.
2396 (omp_complete_construct_context): New.
2397 (omp_resolve_late_declare_variant): Ifdef out.
2398 (omp_declare_variant_remove_hook): Likewise.
2399 (omp_resolve_declare_variant): Likewise.
2400 (sort_variant): New.
2401 (omp_get_dynamic_candidates): New.
2402 (omp_declare_variant_candidates): New.
2403 (omp_metadirective_candidates): New.
2404 (omp_early_resolve_metadirective): New.
2405 (omp_resolve_variant_construct): New.
2406 * omp-general.h (score_wide_int): Moved here from omp-general.cc.
2407 (struct omp_variant): New.
2408 (make_omp_metadirective_variant): Declare.
2409 (omp_construct_traits_to_codes): Delete declaration.
2410 (omp_check_context_selector): Adjust parameters.
2411 (omp_context_selector_matches): Likewise.
2412 (omp_context_selector_set_compare): Delete declaration.
2413 (omp_resolve_declare_variant): Likewise.
2414 (omp_declare_variant_candidates): Declare.
2415 (omp_metadirective_candidates): Declare.
2416 (omp_get_dynamic_candidates): Declare.
2417 (omp_early_resolve_metadirective): Declare.
2418 (omp_resolve_variant_construct): Declare.
2419 (omp_dynamic_cond): Declare.
2420 * omp-offload.cc (resolve_omp_variant_cookies): New.
2421 (execute_omp_device_lower): Call the above function to resolve
2422 variant directives. Remove call to omp_resolve_declare_variant.
2423 (pass_omp_device_lower::gate): Check has_omp_variant_construct bit.
2424 * omp-simd-clone.cc (simd_clone_create): Propagate
2425 has_omp_variant_constructs bit.
2426 * tree-inline.cc (expand_call_inline): Likewise.
2427 (tree_function_versioning): Likewise.
2429 2025-01-14 Sandra Loosemore <sloosemore@baylibre.com>
2430 Kwok Cheung Yeung <kcy@codesourcery.com>
2431 Sandra Loosemore <sandra@codesourcery.com>
2433 * doc/generic.texi (OpenMP): Document OMP_METADIRECTIVE,
2434 OMP_NEXT_VARIANT, and OMP_TARGET_DEVICE_MATCHES.
2435 * fold-const.cc (operand_compare::hash_operand): Ignore
2436 the new nodes.
2437 * gimple-expr.cc (is_gimple_val): Allow OMP_NEXT_VARIANT
2438 and OMP_TARGET_DEVICE_MATCHES.
2439 * gimple.cc (get_gimple_rhs_num_ops): OMP_NEXT_VARIANT and
2440 OMP_TARGET_DEVICE_MATCHES are both GIMPLE_SINGLE_RHS.
2441 * tree-cfg.cc (tree_node_can_be_shared): Allow sharing of
2442 OMP_NEXT_VARIANT.
2443 * tree-inline.cc (remap_gimple_op_r): Ignore subtrees of
2444 OMP_NEXT_VARIANT.
2445 * tree-pretty-print.cc (dump_generic_node): Handle OMP_METADIRECTIVE,
2446 OMP_NEXT_VARIANT, and OMP_TARGET_DEVICE_MATCHES.
2447 * tree-ssa-operands.cc (operands_scanner::get_expr_operands):
2448 Ignore operands of OMP_NEXT_VARIANT and OMP_TARGET_DEVICE_MATCHES.
2449 * tree.def (OMP_METADIRECTIVE): New.
2450 (OMP_NEXT_VARIANT): New.
2451 (OMP_TARGET_DEVICE_MATCHES): New.
2452 * tree.h (OMP_METADIRECTIVE_VARIANTS): New.
2453 (OMP_METADIRECTIVE_VARIANT_SELECTOR): New.
2454 (OMP_METADIRECTIVE_VARIANT_DIRECTIVE): New.
2455 (OMP_METADIRECTIVE_VARIANT_BODY): New.
2456 (OMP_NEXT_VARIANT_INDEX): New.
2457 (OMP_NEXT_VARIANT_STATE): New.
2458 (OMP_TARGET_DEVICE_MATCHES_SELECTOR): New.
2459 (OMP_TARGET_DEVICE_MATCHES_PROPERTIES): New.
2461 2025-01-14 Alexandre Oliva <oliva@adacore.com>
2463 PR tree-optimization/118456
2464 * gimple-fold.cc (decode_field_reference): Punt if shifting
2465 after changing signedness.
2466 (fold_truth_andor_for_ifcombine): Check extension bits in
2467 constants before clipping.
2469 2025-01-14 Robin Dapp <rdapp@ventanamicro.com>
2471 PR target/118154
2472 * config/riscv/riscv-vsetvl.cc (MAX_LMUL): New define.
2473 (pre_vsetvl::earliest_fuse_vsetvl_info): Use.
2474 (pre_vsetvl::pre_global_vsetvl_info): New predicate with equal
2475 ratio.
2476 * config/riscv/riscv-vsetvl.def: Use.
2478 2025-01-14 Robin Dapp <rdapp@ventanamicro.com>
2480 PR middle-end/118140
2481 * gimple-match-exports.cc (maybe_resimplify_conditional_op): Add
2482 COND_EXPR when we simplified to a scalar gimple value but still
2483 have an else value.
2485 2025-01-14 Richard Biener <rguenther@suse.de>
2487 PR tree-optimization/118405
2488 * tree-vect-stmts.cc (vectorizable_load): When we fall back
2489 to scalar loads make sure we properly convert to vector(1) T
2490 when there was only a single vector element.
2492 2025-01-14 Robin Dapp <rdapp.gcc@gmail.com>
2494 * config/riscv/riscv-v.cc (expand_const_vector): Shift in Xmode.
2496 2025-01-14 Jiufu Guo <guojiufu@linux.ibm.com>
2498 PR target/116030
2499 * config/rs6000/vsx.md (vsx_stxvd2x4_le_const_<mode>): Add clobber
2500 and guard with !altivec_indexed_or_indirect_operand.
2502 2025-01-14 Robin Dapp <rdapp.gcc@gmail.com>
2504 PR target/117682
2505 * config/riscv/riscv-v.cc (expand_const_vector): Fall back to
2506 merging if either step is negative.
2508 2025-01-13 Xi Ruoyao <xry111@xry111.site>
2510 PR target/115921
2511 * config/riscv/riscv.md (<optab>_shift_reverse): Remove
2512 check for TARGET_ZBA.
2514 2025-01-13 Richard Sandiford <richard.sandiford@arm.com>
2516 PR target/118418
2517 * simplify-rtx.cc (simplify_context::simplify_relational_operation_1):
2518 Take STORE_FLAG_VALUE into account when handling signed comparisons
2519 of comparison results.
2521 2025-01-13 Xi Ruoyao <xry111@xry111.site>
2523 PR target/115921
2524 * config/riscv/riscv.md (<optab>_shift_reverse): Only check
2525 popcount_hwi if !TARGET_ZBS.
2527 2025-01-13 Jin Ma <jinma@linux.alibaba.com>
2529 * config/riscv/riscv-vsetvl.cc (demand_system::use_max_sew): Also
2530 set the ratio for PREV.
2532 2025-01-13 Vineet Gupta <vineetg@rivosinc.com>
2534 * config/riscv/riscv.cc (riscv_register_move_cost): Remove buggy
2535 check.
2537 2025-01-13 Jin Ma <jinma@linux.alibaba.com>
2539 * config/riscv/riscv.cc (riscv_build_integer_1): Change
2540 1UL/1ULL to HOST_WIDE_INT_1U.
2542 2025-01-13 Jeff Law <jlaw@ventanamicro.com>
2544 PR rtl-optimization/107455
2545 * postreload.cc (reload_cse_regs_1): Take advantage of conditional
2546 equivalences.
2548 2025-01-13 Alexandre Oliva <oliva@adacore.com>
2550 PR tree-optimization/118409
2551 * gimple-fold.cc (fold_truth_andor_for_ifcombine): Apply the
2552 signbit mask to the right-hand XOR operand too.
2554 2025-01-13 Jakub Jelinek <jakub@redhat.com>
2556 PR target/115910
2557 * expr.cc (expand_expr_divmod): Prefix the TDF_DETAILS note with
2558 ";; " and add a space before (needed tie breaker). Formatting fixes.
2560 2025-01-13 Richard Biener <rguenther@suse.de>
2561 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2563 PR tree-optimization/117119
2564 * tree-data-ref.cc (initialize_matrix_A): Check whether
2565 an INTEGER_CST fits in HWI, otherwise return chrec_dont_know.
2567 2025-01-13 Michal Jires <mjires@suse.cz>
2569 PR lto/118181
2570 * lto-ltrans-cache.cc (ltrans_file_cache::create_item):
2571 Pass checksum by reference.
2572 * lto-ltrans-cache.h: Likewise.
2574 2025-01-13 Michal Jires <mjires@suse.cz>
2576 * lockfile.cc (LOCKFILE_USE_FCNTL): New.
2577 (lockfile::lock_write): Use LOCKFILE_USE_FCNTL.
2578 (lockfile::try_lock_write): Use LOCKFILE_USE_FCNTL.
2579 (lockfile::lock_read): Use LOCKFILE_USE_FCNTL.
2580 (lockfile::unlock): Use LOCKFILE_USE_FCNTL.
2581 (lockfile::lockfile_supported): Use LOCKFILE_USE_FCNTL.
2583 2025-01-13 liuhongt <hongtao.liu@intel.com>
2585 * config/i386/i386-expand.cc (ix86_expand_vecop_qihi2):
2586 Refactor to avoid redundant TARGET_AVX512BW in many places.
2588 2025-01-13 Jakub Jelinek <jakub@redhat.com>
2590 PR tree-optimization/117997
2591 PR middle-end/118415
2592 * expr.cc (assemble_crc_table): Make static, remove id argument,
2593 use output_constant_def. Emit note if -fdump-rtl-expand-details
2594 about which table has been emitted.
2595 (generate_crc_table): Make static, adjust assemble_crc_table
2596 caller, call it always.
2597 (calculate_table_based_CRC): Make static.
2598 * internal-fn.cc (expand_crc_optab_fn): Emit note if
2599 -fdump-rtl-expand-details about using optab for crc. Formatting fix.
2601 2025-01-12 Maciej W. Rozycki <macro@orcam.me.uk>
2603 * config/alpha/alpha.cc (alpha_expand_block_move): Use a HImode
2604 subreg of a DImode register to hold data from an aligned HImode
2605 load.
2607 2025-01-12 Maciej W. Rozycki <macro@orcam.me.uk>
2609 * config/alpha/alpha.cc (alpha_expand_block_move): Merge loaded
2610 data from pairs of SImode registers into single DImode registers
2611 if to be used with unaligned stores.
2613 2025-01-12 Maciej W. Rozycki <macro@orcam.me.uk>
2615 * config/alpha/alpha.cc (alpha_option_override): Ignore CPU
2616 flags corresponding to features the enabling or disabling of
2617 which has been requested with an individual feature option.
2619 2025-01-12 Maciej W. Rozycki <macro@orcam.me.uk>
2621 PR middle-end/64242
2622 * config/alpha/alpha.md (`builtin_longjmp'): Restore frame
2623 pointer last. Add frame clobber and schedule blockage.
2625 2025-01-12 Maciej W. Rozycki <macro@orcam.me.uk>
2627 * config/alpha/alpha.md (builtin_longjmp): Add memory clobbers.
2629 2025-01-12 Richard Biener <rguenther@suse.de>
2631 * tree-vect-slp.cc (vect_analyze_slp): Release saved_stmts
2632 vector.
2633 (vect_build_slp_tree_2): Release new_oprnds_info when not
2634 used.
2635 (vect_analyze_slp): Release root_stmts when gcond SLP
2636 build fails.
2638 2025-01-12 Andrew Pinski <quic_apinski@quicinc.com>
2640 PR middle-end/118411
2641 * final.cc (get_attr_length_1): Handle asm for CALL_INSN
2642 and JUMP_INSNs.
2644 2025-01-11 mengqinggang <mengqinggang@loongson.cn>
2646 * config/loongarch/lasx.md: Use new loongarch_output_move.
2647 * config/loongarch/loongarch-protos.h (loongarch_output_move):
2648 Change parameters from (rtx, rtx) to (rtx *).
2649 * config/loongarch/loongarch.cc (loongarch_output_move):
2650 Generate final immediate for lu12i.w and lu52i.d.
2651 * config/loongarch/loongarch.md:
2652 Generate final immediate for lu32i.d and lu52i.d.
2653 * config/loongarch/lsx.md: Use new loongarch_output_move.
2655 2025-01-11 Andrew MacLeod <amacleod@redhat.com>
2657 PR tree-optimization/88575
2658 * vr-values.cc (simplify_using_ranges::fold_cond_with_ops): Query
2659 relation between op0 and op1 and utilize it.
2660 (simplify_using_ranges::simplify): Do not eliminate float checks.
2662 2025-01-10 Alex Coplan <alex.coplan@arm.com>
2664 PR tree-optimization/118211
2665 PR tree-optimization/116126
2666 * tree-vect-loop.cc (vect_compute_single_scalar_iteration_cost):
2667 Don't skip over gconds.
2669 2025-01-10 Alex Coplan <alex.coplan@arm.com>
2671 PR tree-optimization/118211
2672 PR tree-optimization/116126
2673 * tree-vect-loop-manip.cc (vect_do_peeling): Adjust skip_vector
2674 condition to only omit the edge if we're versioning for
2675 alignment.
2677 2025-01-10 Tamar Christina <Tamar.Christina@arm.com>
2678 Alex Coplan <alex.coplan@arm.com>
2680 PR tree-optimization/118211
2681 PR tree-optimization/116126
2682 * tree-vect-loop-manip.cc (vect_do_peeling): Update immediate
2683 dominators of nodes that were dominated by the prolog skip block
2684 after inserting vector skip edge. Initialize prolog variable to
2685 NULL to avoid bogus -Wmaybe-uninitialized during bootstrap.
2687 2025-01-10 Alex Coplan <alex.coplan@arm.com>
2689 PR tree-optimization/118211
2690 PR tree-optimization/116126
2691 * tree-vect-loop-manip.cc (vect_do_peeling): Avoid emitting an
2692 epilogue guard for inverted early-exit loops.
2694 2025-01-10 Alex Coplan <alex.coplan@arm.com>
2695 Tamar Christina <tamar.christina@arm.com>
2697 PR tree-optimization/118211
2698 PR tree-optimization/116126
2699 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
2700 Set need_peeling_for_alignment flag on read DRs instead of
2701 failing vectorization. Punt on gathers.
2702 (dr_misalignment): Handle non-constant target alignments.
2703 (vect_compute_data_ref_alignment): If need_peeling_for_alignment
2704 flag is set on the DR, then override the target alignment chosen
2705 by the preferred_vector_alignment hook to choose a safe
2706 alignment.
2707 (vect_supportable_dr_alignment): Override
2708 support_vector_misalignment hook if need_peeling_for_alignment
2709 is set on the DR: in this case we must return
2710 dr_unaligned_unsupported in order to force peeling.
2711 * tree-vect-loop-manip.cc (vect_do_peeling): Allow prolog
2712 peeling by a compile-time non-constant amount.
2713 * tree-vectorizer.h (dr_vec_info): Add new flag
2714 need_peeling_for_alignment.
2716 2025-01-10 Tamar Christina <tamar.christina@arm.com>
2718 * config/aarch64/aarch64-cores.def (AARCH64_CORE): Fix cortex-x4 parts
2719 num.
2721 2025-01-10 Richard Biener <rguenther@suse.de>
2723 * df-core.cc (rest_of_handle_df_finish): Release dflow for
2724 problems without free function (like LR).
2725 * gimple-crc-optimization.cc (crc_optimization::loop_may_calculate_crc):
2726 Release loop_bbs on all exits.
2727 * tree-vectorizer.h (supportable_indirect_convert_operation): Change.
2728 * tree-vect-generic.cc (expand_vector_conversion): Adjust.
2729 * tree-vect-stmts.cc (vectorizable_conversion): Use auto_vec for
2730 converts.
2731 (supportable_indirect_convert_operation): Get a reference to
2732 the output vector of converts.
2734 2025-01-10 Christophe Lyon <christophe.lyon@linaro.org>
2736 PR target/118332
2737 * config/arm/arm-mve-builtins.cc (wrap_type_in_struct): Delete.
2738 (register_type_decl): Delete.
2739 (register_builtin_tuple_types): Use
2740 lang_hooks.types.simulate_record_decl.
2742 2025-01-10 Richard Biener <rguenther@suse.de>
2744 * gcse.cc (pass_hardreg_pre::gate): Wrap possibly unused
2745 fun argument.
2747 2025-01-10 Richard Biener <rguenther@suse.de>
2749 PR rtl-optimization/117467
2750 PR rtl-optimization/117934
2751 * ext-dce.cc (ext_dce_execute): Do nothing if a memory
2752 allocation estimate exceeds what is allowed by
2753 --param max-gcse-memory.
2755 2025-01-10 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
2757 * config/s390/s390-protos.h (s390_emit_compare): Add mode
2758 parameter for the resulting RTX.
2759 * config/s390/s390.cc (s390_emit_compare): Dito.
2760 (s390_emit_compare_and_swap): Change.
2761 (s390_expand_vec_strlen): Change.
2762 (s390_expand_cs_hqi): Change.
2763 (s390_expand_split_stack_prologue): Change.
2764 * config/s390/s390.md (*add<mode>3_carry1_cc): Renamed to ...
2765 (add<mode>3_carry1_cc): this and in order to use the
2766 corresponding gen function, encode CC mode into pattern.
2767 (*sub<mode>3_borrow_cc): Renamed to ...
2768 (sub<mode>3_borrow_cc): this and in order to use the
2769 corresponding gen function, encode CC mode into pattern.
2770 (*add<mode>3_alc_carry1_cc): Renamed to ...
2771 (add<mode>3_alc_carry1_cc): this and in order to use the
2772 corresponding gen function, encode CC mode into pattern.
2773 (sub<mode>3_slb_borrow1_cc): New.
2774 (uaddc<mode>5): New.
2775 (usubc<mode>5): New.
2777 2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
2779 * doc/passes.texi: Document hardreg PRE pass.
2781 2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
2783 * config/aarch64/aarch64.h (HARDREG_PRE_REGNOS): New macro.
2784 * gcse.cc (doing_hardreg_pre_p): New global variable.
2785 (do_load_motion): New boolean check.
2786 (current_hardreg_regno): New global variable.
2787 (compute_local_properties): Unset transp for hardreg clobbers.
2788 (prune_hardreg_uses): New function.
2789 (want_to_gcse_p): Use different checks for hardreg PRE.
2790 (oprs_unchanged_p): Disable load motion for hardreg PRE pass.
2791 (hash_scan_set): For hardreg PRE, skip non-hardreg sets and
2792 check for hardreg clobbers.
2793 (record_last_mem_set_info): Skip for hardreg PRE.
2794 (compute_pre_data): Prune hardreg uses from transp bitmap.
2795 (pre_expr_reaches_here_p_work): Add sentence to comment.
2796 (insert_insn_start_basic_block): New functions.
2797 (pre_edge_insert): Don't add hardreg sets to predecessor block.
2798 (pre_delete): Use hardreg for the reaching reg.
2799 (reset_hardreg_debug_uses): New function.
2800 (pre_gcse): For hardreg PRE, reset debug uses and don't insert
2801 copies.
2802 (one_pre_gcse_pass): Disable load motion for hardreg PRE.
2803 (execute_hardreg_pre): New.
2804 (class pass_hardreg_pre): New.
2805 (pass_hardreg_pre::gate): New.
2806 (make_pass_hardreg_pre): New.
2807 * passes.def (pass_hardreg_pre): New pass.
2808 * tree-pass.h (make_pass_hardreg_pre): New.
2810 2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
2812 * multiple_target.cc
2813 (redirect_to_specific_clone): Assert that "target" attribute is
2814 used for FMV before checking it.
2815 (ipa_target_clone): Skip redirect_to_specific_clone on some
2816 targets.
2818 2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
2820 * doc/invoke.texi: Add new AArch64 flags.
2822 2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
2824 * config/aarch64/aarch64-arches.def (V8_7A): Add XS.
2825 * config/aarch64/aarch64-option-extensions.def (XS): New flag.
2827 2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
2829 * config/aarch64/aarch64-arches.def (V8_7A): Add WFXT.
2830 * config/aarch64/aarch64-option-extensions.def (WFXT): New flag.
2832 2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
2834 * config/aarch64/aarch64-arches.def (V8_4A): Add RCPC2.
2835 * config/aarch64/aarch64-option-extensions.def
2836 (RCPC2): New flag.
2837 (RCPC3): Add RCPC2 dependency.
2838 * config/aarch64/aarch64.h (TARGET_RCPC2): Use new flag.
2840 2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
2842 * config/aarch64/aarch64-arches.def (V8_5A): Add FLAGM2.
2843 * config/aarch64/aarch64-option-extensions.def (FLAGM2): New flag.
2845 2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
2847 * config/aarch64/aarch64-arches.def (V8_5A): Add FRINTTS
2848 * config/aarch64/aarch64-option-extensions.def (FRINTTS): New flag.
2849 * config/aarch64/aarch64.h (TARGET_FRINT): Use new flag.
2850 * config/aarch64/arm_acle.h: Use new flag for frintts intrinsics.
2851 * config/aarch64/arm_neon.h: Ditto.
2853 2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
2855 * config/aarch64/aarch64-arches.def (V8_3A): Add JSCVT.
2856 * config/aarch64/aarch64-option-extensions.def (JSCVT): New flag.
2857 * config/aarch64/aarch64.h (TARGET_JSCVT): Use new flag.
2858 * config/aarch64/arm_acle.h: Use new flag for jscvt intrinsics.
2860 2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
2862 * config/aarch64/aarch64-arches.def (V8_3A): Add FCMA.
2863 * config/aarch64/aarch64-option-extensions.def (FCMA): New flag.
2864 (SVE): Add FCMA dependency.
2865 * config/aarch64/aarch64.h (TARGET_COMPLEX): Use new flag.
2866 * config/aarch64/arm_neon.h: Use new flag for fcma intrinsics.
2868 2025-01-10 Andrew Carlotti <andrew.carlotti@arm.com>
2870 * config/aarch64/aarch64.cc
2871 (aarch64_expand_epilogue): Use TARGET_PAUTH.
2872 * config/aarch64/aarch64.md: Update comment.
2874 2025-01-10 Richard Sandiford <richard.sandiford@arm.com>
2876 PR rtl-optimization/117186
2877 * rtl.h (simplify_context::simplify_logical_relational_operation): Add
2878 an invert0_p parameter.
2879 * simplify-rtx.cc (unsigned_comparison_to_mask): New function.
2880 (mask_to_unsigned_comparison): Likewise.
2881 (comparison_code_valid_for_mode): Delete.
2882 (simplify_context::simplify_logical_relational_operation): Add
2883 an invert0_p parameter. Handle AND and XOR. Handle unsigned
2884 comparisons. Handle always-false results. Ignore the low bit
2885 of the mask if the operands are always ordered and remove the
2886 then-redundant check of comparison_code_valid_for_mode. Check
2887 for side-effects in the operands before simplifying them away.
2888 (simplify_context::simplify_binary_operation_1): Remove
2889 simplification of (compare (gt ...) (lt ...)) and instead...
2890 (simplify_context::simplify_relational_operation_1): ...handle
2891 comparisons of comparisons here.
2892 (test_comparisons): New function.
2893 (test_scalar_ops): Call it.
2895 2025-01-10 Alexandre Oliva <oliva@adacore.com>
2897 * gimple-fold.cc (decode_field_reference): Drop misuses of
2898 uniform_integer_cst_p.
2899 (fold_truth_andor_for_ifcombine): Likewise.
2901 2025-01-10 Alexandre Oliva <oliva@adacore.com>
2903 PR tree-optimization/118344
2904 * gimple-fold.cc (fold_truth_andor_for_ifcombine): Fix typo in
2905 rr_and_mask's type adjustment test.
2907 2025-01-10 Alexandre Oliva <oliva@adacore.com>
2909 * gimple-fold.cc (decode_field_reference): Add xor_pand_mask.
2910 Propagate pand_mask to the right-hand xor operand. Don't
2911 require the right-hand xor operand to be a constant.
2912 (fold_truth_andor_for_ifcombine): Pass right-hand mask when
2913 appropriate.
2915 2025-01-10 Alexandre Oliva <oliva@adacore.com>
2917 PR tree-optimization/118206
2918 * gimple-fold.cc (decode_field_reference): Account for upper
2919 bits dropped by narrowing conversions whether before or after
2920 a right shift.
2921 (fold_truth_andor_for_ifcombine): Fold masks, compares, and
2922 combined results.
2924 2025-01-10 Alexandre Oliva <oliva@adacore.com>
2926 * gimple-fold.cc (fold_truth_andor_for_ifcombine): Limit
2927 boundary choice by word size as well. Try aligned double-word
2928 loads as a last resort.
2930 2025-01-10 Martin Jambor <mjambor@suse.cz>
2932 PR ipa/118138
2933 * ipa-cp.cc (ipacp_value_safe_for_type): Return the appropriate
2934 type instead of a bool, accept NULL_TREE VALUEs.
2935 (propagate_vals_across_arith_jfunc): Use the new returned value of
2936 ipacp_value_safe_for_type.
2937 (propagate_vals_across_ancestor): Likewise.
2938 (propagate_scalar_across_jump_function): Likewise.
2940 2025-01-10 chenxiaolong <chenxiaolong@loongson.cn>
2941 Deng Jianbo <dengjianbo@loongson.cn>.
2943 * config/loongarch/loongarch.cc
2944 (loongarch_builtin_vectorization_cost): Modify the
2945 construction cost of the vec_construct vector.
2947 2025-01-09 Tamar Christina <tamar.christina@arm.com>
2949 PR target/118188
2950 * config/aarch64/aarch64.cc (aarch64_vector_costs::count_ops): Adjust
2951 throughput of emulated gather and scatters.
2953 2025-01-09 Vladimir N. Makarov <vmakarov@redhat.com>
2955 PR target/118017
2956 * lra-constraints.cc (inherit_reload_reg): Check reg class on uniformity.
2958 2025-01-09 Stefan Schulze Frielinghaus <stefansf@gcc.gnu.org>
2960 PR target/118362
2961 * config/s390/s390.cc (s390_constant_via_vgbm_p): Allow at most
2962 16-byte vectors.
2964 2025-01-09 Christophe Lyon <christophe.lyon@linaro.org>
2966 PR target/118131
2967 * config/arm/arm.h (VALID_MVE_STRUCT_MODE): Accept TI, OI and XI
2968 modes again.
2970 2025-01-09 Thomas Schwinge <tschwinge@baylibre.com>
2972 PR target/65181
2973 * config/nvptx/nvptx.cc (nvptx_get_drap_rtx): Handle
2974 '!TARGET_SOFT_STACK'.
2975 * config/nvptx/nvptx.md (define_c_enum "unspec"): Add
2976 'UNSPEC_STACKSAVE', 'UNSPEC_STACKRESTORE'.
2977 (define_expand "allocate_stack", define_expand "save_stack_block")
2978 (define_expand "save_stack_block"): Handle '!TARGET_SOFT_STACK',
2979 PTX 'alloca'.
2980 (define_insn "@nvptx_alloca_<mode>")
2981 (define_insn "@nvptx_stacksave_<mode>")
2982 (define_insn "@nvptx_stackrestore_<mode>"): New.
2983 * doc/invoke.texi (Nvidia PTX Options): Update '-msoft-stack',
2984 '-mno-soft-stack'.
2985 * doc/sourcebuild.texi (nvptx-specific attributes): Document
2986 'nvptx_runtime_alloca_ptx'.
2987 (Add Options): Document 'nvptx_alloca_ptx'.
2989 2025-01-09 Richard Biener <rguenther@suse.de>
2991 * cfgloopmanip.cc (duplicate_loop_body_to_header_edge): When
2992 copying to the header edge first redirect the entry to the
2993 new loop and then the exit to the old to avoid PHI node
2994 re-allocation.
2996 2025-01-09 H.J. Lu <hjl.tools@gmail.com>
2998 PR rtl-optimization/118266
2999 * ree.cc (add_removable_extension): Skip extension on fixed
3000 register.
3002 2025-01-09 Jakub Jelinek <jakub@redhat.com>
3003 Andrew Pinski <quic_apinski@quicinc.com>
3005 PR tree-optimization/117927
3006 * tree-pass.h (PROP_last_full_fold): Define.
3007 * passes.def: Add last= parameters to pass_forwprop.
3008 * tree-ssa-forwprop.cc (pass_forwprop): Add last_p non-static
3009 data member and initialize it in the ctor.
3010 (pass_forwprop::set_pass_param): New method.
3011 (pass_forwprop::execute): Set PROP_last_full_fold in curr_properties
3012 at the start if last_p.
3013 * match.pd (a rrotate (32-b) -> a lrotate b): Only optimize either
3014 if @2 is known not to be equal to prec or if during/after last
3015 forwprop the subtraction has single use and prec is power of two; in
3016 that case transform it into orotate by masked count.
3018 2025-01-09 Haochen Jiang <haochen.jiang@intel.com>
3020 * common/config/i386/cpuinfo.h (get_intel_cpu): Remove 0x00.
3022 2025-01-09 xuli <xuli1@eswincomputing.com>
3024 * config/riscv/riscv-vector-builtins.cc (function_builder::add_unique_function):
3025 Only register overloaded intrinsic for g++.
3026 Only insert non_overloaded_function_table for gcc.
3027 (function_builder::add_overloaded_function): Only register overloaded intrinsic for gcc.
3028 (handle_pragma_vector): Only initialize non_overloaded_function_table for gcc.
3030 2025-01-09 Tobias Burnus <tburnus@baylibre.com>
3032 * builtin-types.def (BT_FN_PTRMODE_PTR_INT_PTR): Add.
3033 * gimplify.cc (gimplify_call_expr): Add error for multiple
3034 list items to the OpenMP interop clause if no device clause;
3035 continue instead of restarting after append_args handling.
3036 (gimplify_omp_dispatch): Extract device number from the
3037 single interop-clause list item.
3038 * omp-builtins.def (BUILT_IN_OMP_GET_INTEROP_INT): Add.
3040 2025-01-08 Thomas Schwinge <tschwinge@baylibre.com>
3042 PR target/65181
3043 * config/nvptx/nvptx.cc (default_ptx_version_option): For
3044 '-march=sm_52' and higher, default at least to '-mptx=7.3'.
3045 * doc/invoke.texi (Nvidia PTX Options): Update '-mptx=[...]'.
3047 2025-01-08 Thomas Schwinge <tschwinge@baylibre.com>
3049 * config/nvptx/nvptx-opts.h (enum ptx_version): Add
3050 'PTX_VERSION_7_3'.
3051 * config/nvptx/nvptx.cc (ptx_version_to_string)
3052 (ptx_version_to_number): Adjust.
3053 * config/nvptx/nvptx.h (TARGET_PTX_7_3): New.
3054 * config/nvptx/nvptx.opt (Enum(ptx_version)): Add 'EnumValue'
3055 '7.3' for 'PTX_VERSION_7_3'.
3056 * doc/invoke.texi (Nvidia PTX Options): Document '-mptx=7.3'.
3058 2025-01-08 Thomas Schwinge <tschwinge@baylibre.com>
3060 * doc/sourcebuild.texi (Effective-Target Keywords): Document
3061 'nvptx_softstack'.
3063 2025-01-08 Thomas Schwinge <tschwinge@baylibre.com>
3065 PR target/65181
3066 * config/nvptx/nvptx.h (STACK_SAVEAREA_MODE): '#define'.
3067 * config/nvptx/nvptx.md [!TARGET_SOFT_STACK]
3068 (save_stack_function): 'define_expand'.
3069 (restore_stack_function): Handle '!TARGET_SOFT_STACK'.
3071 2025-01-08 Thomas Schwinge <tschwinge@baylibre.com>
3073 PR target/65181
3074 * config/nvptx/nvptx.md [!TARGET_SOFT_STACK] (save_stack_block):
3075 'define_expand'.
3077 2025-01-08 Thiago Jung Bauermann <thiago.bauermann@linaro.org>
3079 * configure.ac: Fix check for HAVE_GAS_SHF_MERGE on Arm targets.
3080 * configure: Regenerate.
3082 2025-01-08 Richard Sandiford <richard.sandiford@arm.com>
3084 PR target/107102
3085 * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall): Only
3086 reject calls with different PCSes if the callee clobbers register
3087 state that the caller must preserve.
3089 2025-01-08 Tobias Burnus <tburnus@baylibre.com>
3091 * gimplify.cc (gimplify_call_expr): Disable variant function's
3092 append_args in 'omp dispatch' when invoking the variant directly
3093 and not through the base function.
3095 2025-01-08 Thomas Schwinge <tschwinge@baylibre.com>
3097 * doc/invoke.texi (Nvidia PTX Options): Update '-march-map=sm_50'.
3099 2025-01-08 Richard Biener <rguenther@suse.de>
3101 PR tree-optimization/117979
3102 * tree-ssa-dce.cc (make_forwarders_with_degenerate_phis):
3103 Properly update the irreducible region state.
3105 2025-01-08 Jakub Jelinek <jakub@redhat.com>
3107 * dwarf2out.cc (break_out_comdat_types): Copy over
3108 DW_AT_language_{name,version} if present.
3109 (output_skeleton_debug_sections): Remove also
3110 DW_AT_language_{name,version}.
3111 (gen_compile_unit_die): For C17, C23, C2Y, C++17, C++20, C++23
3112 and C++26 emit for -gdwarf-5 -gno-strict-dwarf also
3113 DW_AT_language_{name,version} attributes.
3115 2025-01-08 Richard Biener <rguenther@suse.de>
3117 PR middle-end/118325
3118 * tree-nested.cc (convert_nl_goto_reference): Assign proper
3119 context to generated artificial label.
3121 2025-01-08 Richard Biener <rguenther@suse.de>
3123 PR tree-optimization/118269
3124 * tree-vect-loop.cc (vect_create_epilog_for_reduction):
3125 Use the correct stmt for the REDUC_GROUP_FIRST_ELEMENT lookup.
3127 2025-01-08 Christophe Lyon <christophe.lyon@linaro.org>
3129 PR target/118332
3130 * config/arm/arm-mve-builtins.cc (wrap_type_in_struct): Use 'val'
3131 instead of '__val'.
3133 2025-01-08 Haochen Jiang <haochen.jiang@intel.com>
3135 * config/i386/amxavx512intrin.h
3136 (_tile_cvtrowps2pbf16h_internal): Rename to...
3137 (_tile_cvtrowps2bf16h_internal): ...this.
3138 (_tile_cvtrowps2pbf16hi_internal): Rename to...
3139 (_tile_cvtrowps2bf16hi_internal): ...this.
3140 (_tile_cvtrowps2pbf16l_internal): Rename to...
3141 (_tile_cvtrowps2bf16l_internal): ...this.
3142 (_tile_cvtrowps2pbf16li_internal): Rename to...
3143 (_tile_cvtrowps2bf16li_internal): ...this.
3144 (_tile_cvtrowps2pbf16h): Rename to...
3145 (_tile_cvtrowps2bf16h): ...this.
3146 (_tile_cvtrowps2pbf16hi): Rename to...
3147 (_tile_cvtrowps2bf16hi): ...this.
3148 (_tile_cvtrowps2pbf16l): Rename to...
3149 (_tile_cvtrowps2bf16l): ...this.
3150 (_tile_cvtrowps2pbf16li): Rename to...
3151 (_tile_cvtrowps2bf16li): ...this.
3153 2025-01-08 Hongyu Wang <hongyu.wang@intel.com>
3155 * config/i386/i386.cc (ix86_noce_max_ifcvt_seq_cost): Adjust
3156 cost with ix86_tune_cost->br_mispredict_scale.
3157 * config/i386/i386.h (processor_costs): Add br_mispredict_scale.
3158 * config/i386/x86-tune-costs.h: Add new br_mispredict_scale to
3159 all processor_costs, in which icelake_cost/alderlake_cost
3160 with value COSTS_N_INSNS (2) + 3 and other processor with value
3161 COSTS_N_INSNS (2).
3163 2025-01-07 Pan Li <pan2.li@intel.com>
3165 * match.pd: Update comments for sat_* pattern.
3167 2025-01-07 Pan Li <pan2.li@intel.com>
3169 * match.pd: Extract saturated value match for signed SAT_*.
3171 2025-01-07 Pan Li <pan2.li@intel.com>
3173 * match.pd: Refactor sorts of signed SAT_TRUNC match patterns
3175 2025-01-07 Pan Li <pan2.li@intel.com>
3177 * match.pd: Refactor sorts of signed SAT_SUB match patterns.
3179 2025-01-07 Vineet Gupta <vineetg@rivosinc.com>
3180 Pan Li <pan2.li@intel.com>
3182 PR target/117722
3183 * config/riscv/autovec.md: Add uabd expander.
3185 2025-01-07 Tsung Chun Lin <tclin914@gmail.com>
3187 * expr.cc (widest_fixed_size_mode_for_size): Prefer scalar modes
3188 over vector modes in more cases.
3190 2025-01-07 Andreas Schwab <schwab@suse.de>
3192 PR target/118137
3193 * config/riscv/sync.md ("lrsc_atomic_exchange<mode>"): Apply mask
3194 to shifted value.
3196 2025-01-07 Jeff Law <jlaw@ventanamicro.com>
3198 * config/ft32/ft32.md (casesi expander): Force operands[2] into
3199 a register if it's not a suitable rimm operand.
3201 2025-01-07 Wilco Dijkstra <wilco.dijkstra@arm.com>
3203 * common/config/aarch64/aarch64-common.cc: Switch off fschedule_insns.
3205 2025-01-07 Wilco Dijkstra <wilco.dijkstra@arm.com>
3207 * config/aarch64/aarch64.md (movhf_aarch64): Use aarch64_valid_fp_move.
3208 (movsf_aarch64): Likewise.
3209 (movdf_aarch64): Likewise.
3210 * config/aarch64/aarch64.cc (aarch64_valid_fp_move): New function.
3211 * config/aarch64/aarch64-protos.h (aarch64_valid_fp_move): Likewise.
3213 2025-01-07 Paul-Antoine Arras <parras@baylibre.com>
3215 * gimplify.cc (gimplify_call_expr): Create variable
3216 variant_substituted_p to control whether adjust_args applies.
3218 2025-01-07 Tamar Christina <tamar.christina@arm.com>
3220 PR tree-optimization/114932
3221 * tree-ssa-loop-ivopts.cc (alloc_iv): Perform affine unsigned fold.
3223 2025-01-07 Andrew Pinski <quic_apinski@quicinc.com>
3225 PR tree-optimization/105769
3226 * cfgexpand.cc (vars_ssa_cache::operator()): For constructors
3227 walk over the elements.
3229 2025-01-07 Andrew Pinski <quic_apinski@quicinc.com>
3231 PR middle-end/117426
3232 PR middle-end/111422
3233 * cfgexpand.cc (struct vars_ssa_cache): New class.
3234 (vars_ssa_cache::vars_ssa_cache): New constructor.
3235 (vars_ssa_cache::~vars_ssa_cache): New deconstructor.
3236 (vars_ssa_cache::create): New method.
3237 (vars_ssa_cache::exists): New method.
3238 (vars_ssa_cache::add_one): New method.
3239 (vars_ssa_cache::update): New method.
3240 (vars_ssa_cache::dump): New method.
3241 (add_scope_conflicts_2): Factor mostly out to
3242 vars_ssa_cache::operator(). New cache argument.
3243 Walk the bitmap cache for the stack variables addresses.
3244 (vars_ssa_cache::operator()): New method factored out from
3245 add_scope_conflicts_2. Rewrite to be a full walk of all operands
3246 and use a worklist.
3247 (add_scope_conflicts_1): Add cache new argument for the addr cache.
3248 Just call add_scope_conflicts_2 for the phi result instead of calling
3249 for the uses and don't call walk_stmt_load_store_addr_ops for phis.
3250 Update call to add_scope_conflicts_2 to add cache argument.
3251 (add_scope_conflicts): Add cache argument and update calls to
3252 add_scope_conflicts_1.
3254 2025-01-07 Andrew Pinski <quic_apinski@quicinc.com>
3256 * cfgexpand.cc (INVALID_STACK_INDEX): New defined.
3257 (decl_stack_index): New function.
3258 (visit_op): Use decl_stack_index.
3259 (visit_conflict): Likewise.
3260 (add_scope_conflicts_1): Likewise.
3262 2025-01-07 Richard Biener <rguenther@suse.de>
3264 PR rtl-optimization/118298
3265 * loop-unroll.cc (decide_unroll_constant_iterations): Honor
3266 loop->unroll even if the loop is too big for heuristics.
3268 2025-01-07 Deng Jianbo <dengjianbo@loongson.cn>
3270 * config/loongarch/loongarch.cc (loongarch_output_move):
3271 Optimize instructions for initializing fp regsiter to zero.
3273 2025-01-07 Gaius Mulley <gaiusmod2@gmail.com>
3275 PR modula2/118010
3276 * doc/gm2.texi (Compiler options): New option
3277 -fm2-file-offset-bits=.
3279 2025-01-07 Jennifer Schmitz <jschmitz@nvidia.com>
3281 * tree-vect-stmts.cc (vectorizable_store): Extend the use of
3282 n_adjacent_stores to also cover vec_to_scalar operations.
3283 * config/aarch64/aarch64-tuning-flags.def: Remove
3284 use_new_vector_costs as tuning option.
3285 * config/aarch64/aarch64.cc (aarch64_use_new_vector_costs_p):
3286 Remove.
3287 (aarch64_vector_costs::add_stmt_cost): Remove use of
3288 aarch64_use_new_vector_costs_p.
3289 (aarch64_vector_costs::finish_cost): Remove use of
3290 aarch64_use_new_vector_costs_p.
3291 * config/aarch64/tuning_models/cortexx925.h: Remove
3292 AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS.
3293 * config/aarch64/tuning_models/fujitsu_monaka.h: Likewise.
3294 * config/aarch64/tuning_models/generic_armv8_a.h: Likewise.
3295 * config/aarch64/tuning_models/generic_armv9_a.h: Likewise.
3296 * config/aarch64/tuning_models/neoverse512tvb.h: Likewise.
3297 * config/aarch64/tuning_models/neoversen2.h: Likewise.
3298 * config/aarch64/tuning_models/neoversen3.h: Likewise.
3299 * config/aarch64/tuning_models/neoversev1.h: Likewise.
3300 * config/aarch64/tuning_models/neoversev2.h: Likewise.
3301 * config/aarch64/tuning_models/neoversev3.h: Likewise.
3302 * config/aarch64/tuning_models/neoversev3ae.h: Likewise.
3304 2025-01-06 Alexandre Oliva <oliva@adacore.com>
3306 PR middle-end/118006
3307 * cfgexpand.cc (expand_gimple_basic_block): Do not emit
3308 pending stack adjustments after a barrier.
3310 2025-01-06 Akram Ahmad <Akram.Ahmad@arm.com>
3312 * config/aarch64/aarch64-simd.md: (*aarch64_trunc_concat)
3313 new insn definition.
3315 2025-01-06 Fangrui Song <maskray@gcc.gnu.org>
3317 PR gcov-profile/96092
3318 * coverage.cc (coverage_init): Remap getpwd().
3320 2025-01-06 Jennifer Schmitz <jschmitz@nvidia.com>
3322 * config/aarch64/aarch64-sve-builtins-base.cc
3323 (svmul_impl::fold): Wrap code for folding to svneg in lambda
3324 function and pass to gimple_folder::convert_and_fold to enable
3325 the transform for unsigned types.
3326 * config/aarch64/aarch64-sve-builtins.cc
3327 (gimple_folder::convert_and_fold): New function that converts
3328 operands to target type before calling callback function, adding the
3329 necessary conversion statements.
3330 (gimple_folder::redirect_call): Set fntype of redirected call.
3331 (get_vector_type): Move from here to aarch64-sve-builtins.h.
3332 * config/aarch64/aarch64-sve-builtins.h
3333 (gimple_folder::convert_and_fold): Declare function.
3334 (get_vector_type): Move here as inline function.
3336 2025-01-06 Martin Jambor <mjambor@suse.cz>
3338 * ipa-cp.cc (ipcp_print_widest_int): New function.
3339 (ipcp_store_vr_results): Use it.
3340 (ipcp_bits_lattice::print): Likewise. Fix formatting.
3342 2025-01-06 Mark Wielaard <mark@klomp.org>
3344 PR tree-optimization/118032
3345 * tree-switch-conversion.cc (jump_table_cluster::find_jump_tables):
3346 Remove param_switch_lower_slow_alg_max_cases check.
3348 2025-01-06 Tamar Christina <tamar.christina@arm.com>
3350 PR target/96342
3351 PR target/118272
3352 * config/aarch64/aarch64-sve.md (vec_init<mode><Vquad>,
3353 vec_initvnx16qivnx2qi): New.
3354 * config/aarch64/aarch64.cc (aarch64_sve_expand_vector_init_subvector):
3355 Rewrite to support any arbitrary combinations.
3356 * config/aarch64/iterators.md (SVE_NO2E): Update to use SVE_NO4E
3357 (SVE_NO2E, Vquad): New.
3359 2025-01-06 Jakub Jelinek <jakub@redhat.com>
3361 PR tree-optimization/118224
3362 * tree-ssa-dce.cc (is_removable_allocation_p): Don't return true
3363 for allocations with constant size argument larger than PTRDIFF_MAX
3364 or for calloc with one of the arguments constant larger than
3365 PTRDIFF_MAX or their product known constant above PTRDIFF_MAX.
3366 Fix comment typos, furhter -> further and then -> than.
3367 * lto-section-in.cc (lto_free_function_in_decl_state_for_node):
3368 Fix comment typo, furhter -> further.
3370 2025-01-04 Hans-Peter Nilsson <hp@axis.com>
3372 * config/mmix/mmix.cc (mmix_asm_output_labelref): Replace '.'
3373 with '::'.
3374 * config/mmix/mmix.h (ASM_PN_FORMAT): Define to actual default.
3376 2025-01-03 Richard Sandiford <richard.sandiford@arm.com>
3378 PR rtl-optimization/117938
3379 * rtlanal.cc (rtx_properties::try_to_add_dest): Treat writes
3380 to the stack pointer as also writing to memory.
3382 2025-01-03 Jakub Jelinek <jakub@redhat.com>
3384 PR c++/118275
3385 * varasm.cc (array_size_for_constructor): Use build_int_cst
3386 with TREE_TYPE (index) as first argument, instead of bitsize_int.
3388 2025-01-03 Jakub Jelinek <jakub@redhat.com>
3390 * tree-ssa-forwprop.cc (check_ctz_array): Use tree_fits_shwi_p instead
3391 of just TREE_CODE tests for INTEGER_CST.
3393 2025-01-03 Jose E. Marchesi <jose.marchesi@oracle.com>
3395 * config.gcc: install a wrapping stdint.h in bpf targets.
3397 2025-01-02 Paul-Antoine Arras <parras@baylibre.com>
3399 * gimplify.cc (gimplify_call_expr): Fix handling of need_device_ptr for
3400 type(c_ptr). Fix handling of nested function calls in a dispatch region.
3401 (find_ifn_gomp_dispatch): Return the IFN without stripping it.
3402 (gimplify_omp_dispatch): Keep IFN_GOMP_DISPATCH until
3403 gimplify_call_expr.
3405 2025-01-02 Tobias Burnus <tburnus@baylibre.com>
3407 * doc/install.texi (amdgcn-x-amdhsa): Refer to Newlib 4.5.0 for
3408 the I/O locking fixes.
3410 2025-01-02 Richard Biener <rguenther@suse.de>
3412 PR tree-optimization/118171
3413 * tree-ssa-pre.cc (create_component_ref_by_pieces_1): Do not
3414 fold any component ref parts.
3416 2025-01-02 Richard Sandiford <richard.sandiford@arm.com>
3418 PR target/118184
3419 * config/aarch64/aarch64-early-ra.cc (allocno_assignment_is_rmw):
3420 New function.
3421 (early_ra::record_insn_defs): Mark the live range information as
3422 untrustworthy if an assignment would change part of an allocno
3423 but preserve the rest.
3425 2025-01-02 Jakub Jelinek <jakub@redhat.com>
3427 * tree-ssa-forwprop.cc (check_ctz_array): Handle also RAW_DATA_CST
3428 in the CONSTRUCTOR_ELTS.
3430 2025-01-02 Jakub Jelinek <jakub@redhat.com>
3432 * doc/libgdiagnostics/conf.py: Use u'' instead of '' in
3433 project and copyright initialization.
3435 2025-01-02 Jakub Jelinek <jakub@redhat.com>
3437 * gcc.cc (process_command): Update copyright notice dates.
3438 * gcov-dump.cc (print_version): Ditto.
3439 * gcov.cc (print_version): Ditto.
3440 * gcov-tool.cc (print_version): Ditto.
3441 * gengtype.cc (create_file): Ditto.
3442 * doc/cpp.texi: Bump @copying's copyright year.
3443 * doc/cppinternals.texi: Ditto.
3444 * doc/gcc.texi: Ditto.
3445 * doc/gccint.texi: Ditto.
3446 * doc/gcov.texi: Ditto.
3447 * doc/install.texi: Ditto.
3448 * doc/invoke.texi: Ditto.
3450 2025-01-02 Guo Jie <guojie@loongson.cn>
3452 * config/loongarch/loongarch.cc
3453 (loongarch_expand_conditional_move): Add some optimization
3454 implementations based on noce_try_cmove_arith.
3456 2025-01-02 Guo Jie <guojie@loongson.cn>
3458 * config/loongarch/lasx.md (lasx_xvabsd_s_<lasxfmt>): Remove.
3459 (<su>abd<mode>3): New insn pattern.
3460 (lasx_xvabsd_u_<lasxfmt_u>): Remove.
3461 * config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vabsd_b):
3462 Rename.
3463 (CODE_FOR_lsx_vabsd_h): Ditto.
3464 (CODE_FOR_lsx_vabsd_w): Ditto.
3465 (CODE_FOR_lsx_vabsd_d): Ditto.
3466 (CODE_FOR_lsx_vabsd_bu): Ditto.
3467 (CODE_FOR_lsx_vabsd_hu): Ditto.
3468 (CODE_FOR_lsx_vabsd_wu): Ditto.
3469 (CODE_FOR_lsx_vabsd_du): Ditto.
3470 (CODE_FOR_lasx_xvabsd_b): Ditto.
3471 (CODE_FOR_lasx_xvabsd_h): Ditto.
3472 (CODE_FOR_lasx_xvabsd_w): Ditto.
3473 (CODE_FOR_lasx_xvabsd_d): Ditto.
3474 (CODE_FOR_lasx_xvabsd_bu): Ditto.
3475 (CODE_FOR_lasx_xvabsd_hu): Ditto.
3476 (CODE_FOR_lasx_xvabsd_wu): Ditto.
3477 (CODE_FOR_lasx_xvabsd_du): Ditto.
3478 * config/loongarch/loongarch.md (u): Add smax/umax.
3479 * config/loongarch/lsx.md (SU_MAX): New iterator.
3480 (su_min): New attr.
3481 (lsx_vabsd_s_<lsxfmt>): Remove.
3482 (<su>abd<mode>3): New insn pattern.
3483 (lsx_vabsd_u_<lsxfmt_u>): Remove.
3485 2025-01-02 Guo Jie <guojie@loongson.cn>
3487 * config/loongarch/lasx.md (vec_unpacks_lo_<mode>): Redefine.
3488 (vec_unpacku_lo_<mode>): Ditto.
3489 (lasx_vext2xv_h<u>_b<u>): Replaced by vec_unpack<su>_lo_v32qi.
3490 (vec_unpack<su>_lo_v32qi): New insn.
3491 (lasx_vext2xv_w<u>_h<u>): Replaced by vec_unpack<su>_lo_v16hi.
3492 (vec_unpack<su>_lo_v16qi_internal): New insn, for 128 bits.
3493 (vec_unpack<su>_lo_v16hi): New insn.
3494 (lasx_vext2xv_d<u>_w<u>): Replaced by vec_unpack<su>_lo_v8si.
3495 (vec_unpack<su>_lo_v8hi_internal): New insn, for 128 bits.
3496 (vec_unpack<su>_lo_v8si): New insn.
3497 (vec_unpack<su>_lo_v4si_internal): New insn, for 128 bits.
3498 (vec_packs_float_v4di): New expander.
3499 (vec_pack_sfix_trunc_v4df): Ditto.
3500 (vec_unpacks_float_hi_v8si): Ditto.
3501 (vec_unpacks_float_lo_v8si): Ditto.
3502 (vec_unpack_sfix_trunc_hi_v8sf): Ditto.
3503 (vec_unpack_sfix_trunc_lo_v8sf): Ditto.
3504 * config/loongarch/loongarch-builtins.cc
3505 (CODE_FOR_lsx_vftintrz_w_d): Rename.
3506 (CODE_FOR_lsx_vftintrzh_l_s): Ditto.
3507 (CODE_FOR_lsx_vftintrzl_l_s): Ditto.
3508 (CODE_FOR_lsx_vffint_s_l): Ditto.
3509 (CODE_FOR_lsx_vffinth_d_w): Ditto.
3510 (CODE_FOR_lsx_vffintl_d_w): Ditto.
3511 (CODE_FOR_lsx_vexth_h_b): Ditto.
3512 (CODE_FOR_lsx_vexth_w_h): Ditto.
3513 (CODE_FOR_lsx_vexth_d_w): Ditto.
3514 (CODE_FOR_lsx_vexth_hu_bu): Ditto.
3515 (CODE_FOR_lsx_vexth_wu_hu): Ditto.
3516 (CODE_FOR_lsx_vexth_du_wu): Ditto.
3517 (CODE_FOR_lsx_vfcvth_d_s): Ditto.
3518 (CODE_FOR_lsx_vfcvtl_d_s): Ditto.
3519 (CODE_FOR_lasx_vext2xv_h_b): Ditto.
3520 (CODE_FOR_lasx_vext2xv_w_h): Ditto.
3521 (CODE_FOR_lasx_vext2xv_d_w): Ditto.
3522 (CODE_FOR_lasx_vext2xv_hu_bu): Ditto.
3523 (CODE_FOR_lasx_vext2xv_wu_hu): Ditto.
3524 (CODE_FOR_lasx_vext2xv_du_wu): Ditto.
3525 (loongarch_expand_builtin_insn): Swap source operands in
3526 CODE_FOR_lsx_vftintrz_w_d and CODE_FOR_lsx_vffint_s_l.
3527 * config/loongarch/loongarch-protos.h
3528 (loongarch_expand_vec_unpack): Remove useless parameter high_p.
3529 * config/loongarch/loongarch.cc (loongarch_expand_vec_unpack):
3530 Rewrite.
3531 * config/loongarch/lsx.md (vec_unpacks_hi_v4sf): Redefine.
3532 (vec_unpacks_lo_v4sf): Ditto.
3533 (vec_unpacks_hi_<mode>): Ditto.
3534 (vec_unpacku_hi_<mode>): Ditto.
3535 (lsx_vfcvth_d_s): Replaced by vec_unpacks_hi_v4sf.
3536 (lsx_vfcvtl_d_s): Replaced by vec_unpacks_lo_v4sf.
3537 (lsx_vffint_s_l): Replaced by vec_packs_float_v2di.
3538 (vec_packs_float_v2di): New insn.
3539 (lsx_vftintrz_w_d): Replaced by vec_pack_sfix_trunc_v2df.
3540 (vec_pack_sfix_trunc_v2df): New insn.
3541 (lsx_vffinth_d_w): Replaced by vec_unpacks_float_hi_v4si.
3542 (vec_unpacks_float_hi_v4si): New insn.
3543 (lsx_vffintl_d_w): Replaced by vec_unpacks_float_lo_v4si.
3544 (vec_unpacks_float_lo_v4si): New insn.
3545 (lsx_vftintrzh_l_s): Replaced by vec_unpack_sfix_trunc_hi_v4sf.
3546 (vec_unpack_sfix_trunc_hi_v4sf): New insn.
3547 (lsx_vftintrzl_l_s): Replaced by vec_unpack_sfix_trunc_lo_v4sf.
3548 (vec_unpack_sfix_trunc_lo_v4sf): New insn.
3549 (lsx_vexth_h<u>_b<u>): Replaced by vec_unpack<su>_hi_v16qi.
3550 (vec_unpack<su>_hi_v16qi): New insn.
3551 (lsx_vexth_w<u>_h<u>): Replaced by vec_unpack<su>_hi_v8hi.
3552 (vec_unpack<su>_hi_v8hi): New insn.
3553 (lsx_vexth_d<u>_w<u>): Replaced by vec_unpack<su>_hi_v4si.
3554 (vec_unpack<su>_hi_v4si): New insn.
3556 2025-01-02 Guo Jie <guojie@loongson.cn>
3558 * config/loongarch/loongarch.md
3559 (bytepick_d_<bytepick_imm>_rev): New combiner.
3560 (bstrpick_alsl_paired): Reorder input operands.
3562 2025-01-02 Guo Jie <guojie@loongson.cn>
3564 * config/loongarch/lasx.md: Remove useless vec_select.
3565 * config/loongarch/predicates.md: Correct error predicate.
3567 2025-01-02 Guo Jie <guojie@loongson.cn>
3569 * config/loongarch/lasx.md: Fix selector index.
3571 2025-01-02 Guo Jie <guojie@loongson.cn>
3573 * config/loongarch/lasx.md: Remove useless code.
3574 * config/loongarch/lsx.md: Ditto.
3576 2025-01-01 Sam James <sam@gentoo.org>
3578 * doc/cpp.texi (Common Predefined Macros): Fix syntax.
3580 2025-01-01 Richard Biener <rguenther@suse.de>
3582 PR middle-end/118174
3583 * tree-outof-ssa.cc (ssa_is_replaceable_p): Exclude tailcalls.
3585 2025-01-01 Sandra Loosemore <sloosemore@baylibre.com>
3587 * doc/invoke.texi (Option Summary): Put "M32C Options" and
3588 "Cygwin and MinGW Options" in alphabetical order. Add
3589 cross-references.
3590 (Cygwin and MinGW Options): Likewise move the section to its
3591 correct alphabetical location.
3592 * config/lynx.opt.urls: Regenerated.
3593 * config/mingw/cygming.opt.urls: Regenerated.
3594 \f
3595 Copyright (C) 2025 Free Software Foundation, Inc.
3597 Copying and distribution of this file, with or without modification,
3598 are permitted in any medium without royalty provided the copyright
3599 notice and this notice are preserved.