gcc/combine.cc

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987-2025 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify it under
   7 the terms of the GNU General Public License as published by the Free
   8 Software Foundation; either version 3, or (at your option) any later
   9 version.
  10
  11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14 for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 /* This module is essentially the "combiner" phase of the U. of Arizona
  21    Portable Optimizer, but redone to work on our list-structured
  22    representation for RTL instead of their string representation.
  23
  24    The LOG_LINKS of each insn identify the most recent assignment
  25    to each REG used in the insn.  It is a list of previous insns,
  26    each of which contains a SET for a REG that is used in this insn
  27    and not used or set in between.  LOG_LINKs never cross basic blocks.
  28    They were set up by the preceding pass (lifetime analysis).
  29
  30    We try to combine each pair of insns joined by a logical link.
  31    We also try to combine triplets of insns A, B and C when C has
  32    a link back to B and B has a link back to A.  Likewise for a
  33    small number of quadruplets of insns A, B, C and D for which
  34    there's high likelihood of success.
  35
  36    We check (with modified_between_p) to avoid combining in such a way
  37    as to move a computation to a place where its value would be different.
  38
  39    Combination is done by mathematically substituting the previous
  40    insn(s) values for the regs they set into the expressions in
  41    the later insns that refer to these regs.  If the result is a valid insn
  42    for our target machine, according to the machine description,
  43    we install it, delete the earlier insns, and update the data flow
  44    information (LOG_LINKS and REG_NOTES) for what we did.
  45
  46    There are a few exceptions where the dataflow information isn't
  47    completely updated (however this is only a local issue since it is
  48    regenerated before the next pass that uses it):
  49
  50    - reg_live_length is not updated
  51    - reg_n_refs is not adjusted in the rare case when a register is
  52      no longer required in a computation
  53    - there are extremely rare cases (see distribute_notes) when a
  54      REG_DEAD note is lost
  55    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  56      removed because there is no way to know which register it was
  57      linking
  58
  59    To simplify substitution, we combine only when the earlier insn(s)
  60    consist of only a single assignment.  To simplify updating afterward,
  61    we never combine when a subroutine call appears in the middle.  */
  62
  63 #include "config.h"
  64 #include "system.h"
  65 #include "coretypes.h"
  66 #include "backend.h"
  67 #include "target.h"
  68 #include "rtl.h"
  69 #include "tree.h"
  70 #include "cfghooks.h"
  71 #include "predict.h"
  72 #include "df.h"
  73 #include "memmodel.h"
  74 #include "tm_p.h"
  75 #include "optabs.h"
  76 #include "regs.h"
  77 #include "emit-rtl.h"
  78 #include "recog.h"
  79 #include "cgraph.h"
  80 #include "stor-layout.h"
  81 #include "cfgrtl.h"
  82 #include "cfgcleanup.h"
  83 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  84 #include "explow.h"
  85 #include "insn-attr.h"
  86 #include "rtlhooks-def.h"
  87 #include "expr.h"
  88 #include "tree-pass.h"
  89 #include "valtrack.h"
  90 #include "rtl-iter.h"
  91 #include "print-rtl.h"
  92 #include "function-abi.h"
  93 #include "rtlanal.h"
  94
  95 /* Number of attempts to combine instructions in this function.  */
  96
  97 static int combine_attempts;
  98
  99 /* Number of attempts that got as far as substitution in this function.  */
 100
 101 static int combine_merges;
 102
 103 /* Number of instructions combined with added SETs in this function.  */
 104
 105 static int combine_extras;
 106
 107 /* Number of instructions combined in this function.  */
 108
 109 static int combine_successes;
 110
 111 /* combine_instructions may try to replace the right hand side of the
 112    second instruction with the value of an associated REG_EQUAL note
 113    before throwing it at try_combine.  That is problematic when there
 114    is a REG_DEAD note for a register used in the old right hand side
 115    and can cause distribute_notes to do wrong things.  This is the
 116    second instruction if it has been so modified, null otherwise.  */
 117
 118 static rtx_insn *i2mod;
 119
 120 /* When I2MOD is nonnull, this is a copy of the old right hand side.  */
 121
 122 static rtx i2mod_old_rhs;
 123
 124 /* When I2MOD is nonnull, this is a copy of the new right hand side.  */
 125
 126 static rtx i2mod_new_rhs;
 127 \f
 128 struct reg_stat_type {
 129   /* Record last point of death of (hard or pseudo) register n.  */
 130   rtx_insn                      *last_death;
 131
 132   /* Record last point of modification of (hard or pseudo) register n.  */
 133   rtx_insn                      *last_set;
 134
 135   /* The next group of fields allows the recording of the last value assigned
 136      to (hard or pseudo) register n.  We use this information to see if an
 137      operation being processed is redundant given a prior operation performed
 138      on the register.  For example, an `and' with a constant is redundant if
 139      all the zero bits are already known to be turned off.
 140
 141      We use an approach similar to that used by cse, but change it in the
 142      following ways:
 143
 144      (1) We do not want to reinitialize at each label.
 145      (2) It is useful, but not critical, to know the actual value assigned
 146          to a register.  Often just its form is helpful.
 147
 148      Therefore, we maintain the following fields:
 149
 150      last_set_value             the last value assigned
 151      last_set_label             records the value of label_tick when the
 152                                 register was assigned
 153      last_set_table_tick        records the value of label_tick when a
 154                                 value using the register is assigned
 155      last_set_invalid           set to true when it is not valid
 156                                 to use the value of this register in some
 157                                 register's value
 158
 159      To understand the usage of these tables, it is important to understand
 160      the distinction between the value in last_set_value being valid and
 161      the register being validly contained in some other expression in the
 162      table.
 163
 164      (The next two parameters are out of date).
 165
 166      reg_stat[i].last_set_value is valid if it is nonzero, and either
 167      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 168
 169      Register I may validly appear in any expression returned for the value
 170      of another register if reg_n_sets[i] is 1.  It may also appear in the
 171      value for register J if reg_stat[j].last_set_invalid is zero, or
 172      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 173
 174      If an expression is found in the table containing a register which may
 175      not validly appear in an expression, the register is replaced by
 176      something that won't match, (clobber (const_int 0)).  */
 177
 178   /* Record last value assigned to (hard or pseudo) register n.  */
 179
 180   rtx                           last_set_value;
 181
 182   /* Record the value of label_tick when an expression involving register n
 183      is placed in last_set_value.  */
 184
 185   int                           last_set_table_tick;
 186
 187   /* Record the value of label_tick when the value for register n is placed in
 188      last_set_value.  */
 189
 190   int                           last_set_label;
 191
 192   /* These fields are maintained in parallel with last_set_value and are
 193      used to store the mode in which the register was last set, the bits
 194      that were known to be zero when it was last set, and the number of
 195      sign bits copies it was known to have when it was last set.  */
 196
 197   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 198   char                          last_set_sign_bit_copies;
 199   ENUM_BITFIELD(machine_mode)   last_set_mode : MACHINE_MODE_BITSIZE;
 200
 201   /* Set to true if references to register n in expressions should not be
 202      used.  last_set_invalid is set nonzero when this register is being
 203      assigned to and last_set_table_tick == label_tick.  */
 204
 205   bool                          last_set_invalid;
 206
 207   /* Some registers that are set more than once and used in more than one
 208      basic block are nevertheless always set in similar ways.  For example,
 209      a QImode register may be loaded from memory in two places on a machine
 210      where byte loads zero extend.
 211
 212      We record in the following fields if a register has some leading bits
 213      that are always equal to the sign bit, and what we know about the
 214      nonzero bits of a register, specifically which bits are known to be
 215      zero.
 216
 217      If an entry is zero, it means that we don't know anything special.  */
 218
 219   unsigned char                 sign_bit_copies;
 220
 221   unsigned HOST_WIDE_INT        nonzero_bits;
 222
 223   /* Record the value of the label_tick when the last truncation
 224      happened.  The field truncated_to_mode is only valid if
 225      truncation_label == label_tick.  */
 226
 227   int                           truncation_label;
 228
 229   /* Record the last truncation seen for this register.  If truncation
 230      is not a nop to this mode we might be able to save an explicit
 231      truncation if we know that value already contains a truncated
 232      value.  */
 233
 234   ENUM_BITFIELD(machine_mode)   truncated_to_mode : MACHINE_MODE_BITSIZE;
 235 };
 236
 237
 238 static vec<reg_stat_type> reg_stat;
 239
 240 /* One plus the highest pseudo for which we track REG_N_SETS.
 241    regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
 242    but during combine_split_insns new pseudos can be created.  As we don't have
 243    updated DF information in that case, it is hard to initialize the array
 244    after growing.  The combiner only cares about REG_N_SETS (regno) == 1,
 245    so instead of growing the arrays, just assume all newly created pseudos
 246    during combine might be set multiple times.  */
 247
 248 static unsigned int reg_n_sets_max;
 249
 250 /* Record the luid of the last insn that invalidated memory
 251    (anything that writes memory, and subroutine calls, but not pushes).  */
 252
 253 static int mem_last_set;
 254
 255 /* Record the luid of the last CALL_INSN
 256    so we can tell whether a potential combination crosses any calls.  */
 257
 258 static int last_call_luid;
 259
 260 /* When `subst' is called, this is the insn that is being modified
 261    (by combining in a previous insn).  The PATTERN of this insn
 262    is still the old pattern partially modified and it should not be
 263    looked at, but this may be used to examine the successors of the insn
 264    to judge whether a simplification is valid.  */
 265
 266 static rtx_insn *subst_insn;
 267
 268 /* This is the lowest LUID that `subst' is currently dealing with.
 269    get_last_value will not return a value if the register was set at or
 270    after this LUID.  If not for this mechanism, we could get confused if
 271    I2 or I1 in try_combine were an insn that used the old value of a register
 272    to obtain a new value.  In that case, we might erroneously get the
 273    new value of the register when we wanted the old one.  */
 274
 275 static int subst_low_luid;
 276
 277 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 278    must consider all these registers to be always live.  */
 279
 280 static HARD_REG_SET newpat_used_regs;
 281
 282 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 283    insn is the earlier than I2 or I3, combine should rescan starting at
 284    that location.  */
 285
 286 static rtx_insn *added_links_insn;
 287
 288 /* And similarly, for notes.  */
 289
 290 static rtx_insn *added_notes_insn;
 291
 292 /* Basic block in which we are performing combines.  */
 293 static basic_block this_basic_block;
 294 static bool optimize_this_for_speed_p;
 295
 296 \f
 297 /* Length of the currently allocated uid_insn_cost array.  */
 298
 299 static int max_uid_known;
 300
 301 /* The following array records the insn_cost for every insn
 302    in the instruction stream.  */
 303
 304 static int *uid_insn_cost;
 305
 306 /* The following array records the LOG_LINKS for every insn in the
 307    instruction stream as struct insn_link pointers.  */
 308
 309 struct insn_link {
 310   rtx_insn *insn;
 311   unsigned int regno;
 312   struct insn_link *next;
 313 };
 314
 315 static struct insn_link **uid_log_links;
 316
 317 static inline int
 318 insn_uid_check (const_rtx insn)
 319 {
 320   int uid = INSN_UID (insn);
 321   gcc_checking_assert (uid <= max_uid_known);
 322   return uid;
 323 }
 324
 325 #define INSN_COST(INSN)         (uid_insn_cost[insn_uid_check (INSN)])
 326 #define LOG_LINKS(INSN)         (uid_log_links[insn_uid_check (INSN)])
 327
 328 #define FOR_EACH_LOG_LINK(L, INSN)                              \
 329   for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
 330
 331 /* Links for LOG_LINKS are allocated from this obstack.  */
 332
 333 static struct obstack insn_link_obstack;
 334
 335 /* Allocate a link.  */
 336
 337 static inline struct insn_link *
 338 alloc_insn_link (rtx_insn *insn, unsigned int regno, struct insn_link *next)
 339 {
 340   struct insn_link *l
 341     = (struct insn_link *) obstack_alloc (&insn_link_obstack,
 342                                           sizeof (struct insn_link));
 343   l->insn = insn;
 344   l->regno = regno;
 345   l->next = next;
 346   return l;
 347 }
 348
 349 /* Incremented for each basic block.  */
 350
 351 static int label_tick;
 352
 353 /* Reset to label_tick for each extended basic block in scanning order.  */
 354
 355 static int label_tick_ebb_start;
 356
 357 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 358    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 359
 360 static scalar_int_mode nonzero_bits_mode;
 361
 362 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 363    be safely used.  It is zero while computing them and after combine has
 364    completed.  This former test prevents propagating values based on
 365    previously set values, which can be incorrect if a variable is modified
 366    in a loop.  */
 367
 368 static int nonzero_sign_valid;
 369
 370 \f
 371 /* Record one modification to rtl structure
 372    to be undone by storing old_contents into *where.  */
 373
 374 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
 375
 376 struct undo
 377 {
 378   struct undo *next;
 379   enum undo_kind kind;
 380   union { rtx r; int i; machine_mode m; struct insn_link *l; } old_contents;
 381   union { rtx *r; int *i; int regno; struct insn_link **l; } where;
 382 };
 383
 384 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 385    num_undo says how many are currently recorded.
 386
 387    other_insn is nonzero if we have modified some other insn in the process
 388    of working on subst_insn.  It must be verified too.  */
 389
 390 struct undobuf
 391 {
 392   struct undo *undos;
 393   struct undo *frees;
 394   rtx_insn *other_insn;
 395 };
 396
 397 static struct undobuf undobuf;
 398
 399 /* Number of times the pseudo being substituted for
 400    was found and replaced.  */
 401
 402 static int n_occurrences;
 403
 404 static rtx reg_nonzero_bits_for_combine (const_rtx, scalar_int_mode,
 405                                          scalar_int_mode,
 406                                          unsigned HOST_WIDE_INT *);
 407 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, scalar_int_mode,
 408                                                 scalar_int_mode,
 409                                                 unsigned int *);
 410 static void do_SUBST (rtx *, rtx);
 411 static void do_SUBST_INT (int *, int);
 412 static void init_reg_last (void);
 413 static void setup_incoming_promotions (rtx_insn *);
 414 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
 415 static bool cant_combine_insn_p (rtx_insn *);
 416 static bool can_combine_p (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
 417                            rtx_insn *, rtx_insn *, rtx *, rtx *);
 418 static bool combinable_i3pat (rtx_insn *, rtx *, rtx, rtx, rtx,
 419                               bool, bool, rtx *);
 420 static bool contains_muldiv (rtx);
 421 static rtx_insn *try_combine (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
 422                               bool *, rtx_insn *);
 423 static void undo_all (void);
 424 static void undo_commit (void);
 425 static rtx *find_split_point (rtx *, rtx_insn *, bool);
 426 static rtx subst (rtx, rtx, rtx, bool, bool, bool);
 427 static rtx combine_simplify_rtx (rtx, machine_mode, bool, bool);
 428 static rtx simplify_if_then_else (rtx);
 429 static rtx simplify_set (rtx);
 430 static rtx simplify_logical (rtx);
 431 static rtx expand_compound_operation (rtx);
 432 static const_rtx expand_field_assignment (const_rtx);
 433 static rtx make_extraction (machine_mode, rtx, HOST_WIDE_INT, rtx,
 434                             unsigned HOST_WIDE_INT, bool, bool, bool);
 435 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 436                               unsigned HOST_WIDE_INT *);
 437 static rtx canon_reg_for_combine (rtx, rtx);
 438 static rtx force_int_to_mode (rtx, scalar_int_mode, scalar_int_mode,
 439                               scalar_int_mode, unsigned HOST_WIDE_INT, bool);
 440 static rtx force_to_mode (rtx, machine_mode,
 441                           unsigned HOST_WIDE_INT, bool);
 442 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 443 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 444 static bool rtx_equal_for_field_assignment_p (rtx, rtx, bool = false);
 445 static rtx make_field_assignment (rtx);
 446 static rtx apply_distributive_law (rtx);
 447 static rtx distribute_and_simplify_rtx (rtx, int);
 448 static rtx simplify_and_const_int_1 (scalar_int_mode, rtx,
 449                                      unsigned HOST_WIDE_INT);
 450 static rtx simplify_and_const_int (rtx, scalar_int_mode, rtx,
 451                                    unsigned HOST_WIDE_INT);
 452 static bool merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 453                              HOST_WIDE_INT, machine_mode, bool *);
 454 static rtx simplify_shift_const_1 (enum rtx_code, machine_mode, rtx, int);
 455 static rtx simplify_shift_const (rtx, enum rtx_code, machine_mode, rtx,
 456                                  int);
 457 static int recog_for_combine (rtx *, rtx_insn *, rtx *);
 458 static rtx gen_lowpart_for_combine (machine_mode, rtx);
 459 static enum rtx_code simplify_compare_const (enum rtx_code, machine_mode,
 460                                              rtx *, rtx *);
 461 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 462 static void update_table_tick (rtx);
 463 static void record_value_for_reg (rtx, rtx_insn *, rtx);
 464 static void check_promoted_subreg (rtx_insn *, rtx);
 465 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
 466 static void record_dead_and_set_regs (rtx_insn *);
 467 static bool get_last_value_validate (rtx *, rtx_insn *, int, bool);
 468 static rtx get_last_value (const_rtx);
 469 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
 470 static bool reg_dead_at_p (rtx, rtx_insn *);
 471 static void move_deaths (rtx, rtx, int, rtx_insn *, rtx *);
 472 static bool reg_bitfield_target_p (rtx, rtx);
 473 static void distribute_notes (rtx, rtx_insn *, rtx_insn *, rtx_insn *,
 474                               rtx, rtx, rtx);
 475 static void distribute_links (struct insn_link *);
 476 static void mark_used_regs_combine (rtx);
 477 static void record_promoted_value (rtx_insn *, rtx);
 478 static bool unmentioned_reg_p (rtx, rtx);
 479 static void record_truncated_values (rtx *, void *);
 480 static bool reg_truncated_to_mode (machine_mode, const_rtx);
 481 static rtx gen_lowpart_or_truncate (machine_mode, rtx);
 482 \f
 483
 484 /* It is not safe to use ordinary gen_lowpart in combine.
 485    See comments in gen_lowpart_for_combine.  */
 486 #undef RTL_HOOKS_GEN_LOWPART
 487 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 488
 489 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 490 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 491 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 492
 493 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 494 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 495
 496 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 497 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 498
 499 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
 500 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE    reg_truncated_to_mode
 501
 502 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 503
 504 \f
 505 /* Convenience wrapper for the canonicalize_comparison target hook.
 506    Target hooks cannot use enum rtx_code.  */
 507 static inline void
 508 target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1,
 509                                 bool op0_preserve_value)
 510 {
 511   int code_int = (int)*code;
 512   targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
 513   *code = (enum rtx_code)code_int;
 514 }
 515
 516 /* Try to split PATTERN found in INSN.  This returns NULL_RTX if
 517    PATTERN cannot be split.  Otherwise, it returns an insn sequence.
 518    This is a wrapper around split_insns which ensures that the
 519    reg_stat vector is made larger if the splitter creates a new
 520    register.  */
 521
 522 static rtx_insn *
 523 combine_split_insns (rtx pattern, rtx_insn *insn)
 524 {
 525   rtx_insn *ret;
 526   unsigned int nregs;
 527
 528   ret = split_insns (pattern, insn);
 529   nregs = max_reg_num ();
 530   if (nregs > reg_stat.length ())
 531     reg_stat.safe_grow_cleared (nregs, true);
 532   return ret;
 533 }
 534
 535 /* This is used by find_single_use to locate an rtx in LOC that
 536    contains exactly one use of DEST, which is typically a REG.
 537    It returns a pointer to the innermost rtx expression
 538    containing DEST.  Appearances of DEST that are being used to
 539    totally replace it are not counted.  */
 540
 541 static rtx *
 542 find_single_use_1 (rtx dest, rtx *loc)
 543 {
 544   rtx x = *loc;
 545   enum rtx_code code = GET_CODE (x);
 546   rtx *result = NULL;
 547   rtx *this_result;
 548   int i;
 549   const char *fmt;
 550
 551   switch (code)
 552     {
 553     case CONST:
 554     case LABEL_REF:
 555     case SYMBOL_REF:
 556     CASE_CONST_ANY:
 557     case CLOBBER:
 558       return 0;
 559
 560     case SET:
 561       /* If the destination is anything other than PC, a REG or a SUBREG
 562          of a REG that occupies all of the REG, the insn uses DEST if
 563          it is mentioned in the destination or the source.  Otherwise, we
 564          need just check the source.  */
 565       if (GET_CODE (SET_DEST (x)) != PC
 566           && !REG_P (SET_DEST (x))
 567           && ! (GET_CODE (SET_DEST (x)) == SUBREG
 568                 && REG_P (SUBREG_REG (SET_DEST (x)))
 569                 && !read_modify_subreg_p (SET_DEST (x))))
 570         break;
 571
 572       return find_single_use_1 (dest, &SET_SRC (x));
 573
 574     case MEM:
 575     case SUBREG:
 576       return find_single_use_1 (dest, &XEXP (x, 0));
 577
 578     default:
 579       break;
 580     }
 581
 582   /* If it wasn't one of the common cases above, check each expression and
 583      vector of this code.  Look for a unique usage of DEST.  */
 584
 585   fmt = GET_RTX_FORMAT (code);
 586   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
 587     {
 588       if (fmt[i] == 'e')
 589         {
 590           if (dest == XEXP (x, i)
 591               || (REG_P (dest) && REG_P (XEXP (x, i))
 592                   && REGNO (dest) == REGNO (XEXP (x, i))))
 593             this_result = loc;
 594           else
 595             this_result = find_single_use_1 (dest, &XEXP (x, i));
 596
 597           if (result == NULL)
 598             result = this_result;
 599           else if (this_result)
 600             /* Duplicate usage.  */
 601             return NULL;
 602         }
 603       else if (fmt[i] == 'E')
 604         {
 605           int j;
 606
 607           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
 608             {
 609               if (XVECEXP (x, i, j) == dest
 610                   || (REG_P (dest)
 611                       && REG_P (XVECEXP (x, i, j))
 612                       && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
 613                 this_result = loc;
 614               else
 615                 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
 616
 617               if (result == NULL)
 618                 result = this_result;
 619               else if (this_result)
 620                 return NULL;
 621             }
 622         }
 623     }
 624
 625   return result;
 626 }
 627
 628
 629 /* See if DEST, produced in INSN, is used only a single time in the
 630    sequel.  If so, return a pointer to the innermost rtx expression in which
 631    it is used.
 632
 633    If PLOC is nonzero, *PLOC is set to the insn containing the single use.
 634
 635    Otherwise, we find the single use by finding an insn that has a
 636    LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST.  If DEST is
 637    only referenced once in that insn, we know that it must be the first
 638    and last insn referencing DEST.  */
 639
 640 static rtx *
 641 find_single_use (rtx dest, rtx_insn *insn, rtx_insn **ploc)
 642 {
 643   basic_block bb;
 644   rtx_insn *next;
 645   rtx *result;
 646   struct insn_link *link;
 647
 648   if (!REG_P (dest))
 649     return 0;
 650
 651   bb = BLOCK_FOR_INSN (insn);
 652   for (next = NEXT_INSN (insn);
 653        next && BLOCK_FOR_INSN (next) == bb;
 654        next = NEXT_INSN (next))
 655     if (NONDEBUG_INSN_P (next) && dead_or_set_p (next, dest))
 656       {
 657         FOR_EACH_LOG_LINK (link, next)
 658           if (link->insn == insn && link->regno == REGNO (dest))
 659             break;
 660
 661         if (link)
 662           {
 663             result = find_single_use_1 (dest, &PATTERN (next));
 664             if (ploc)
 665               *ploc = next;
 666             return result;
 667           }
 668       }
 669
 670   return 0;
 671 }
 672 \f
 673 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 674    insn.  The substitution can be undone by undo_all.  If INTO is already
 675    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 676    also call SUBST, we have to compute it before we put anything into
 677    the undo table.  */
 678
 679 static void
 680 do_SUBST (rtx *into, rtx newval)
 681 {
 682   struct undo *buf;
 683   rtx oldval = *into;
 684
 685   if (oldval == newval)
 686     return;
 687
 688   /* We'd like to catch as many invalid transformations here as
 689      possible.  Unfortunately, there are way too many mode changes
 690      that are perfectly valid, so we'd waste too much effort for
 691      little gain doing the checks here.  Focus on catching invalid
 692      transformations involving integer constants.  */
 693   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 694       && CONST_INT_P (newval))
 695     {
 696       /* Sanity check that we're replacing oldval with a CONST_INT
 697          that is a valid sign-extension for the original mode.  */
 698       gcc_assert (INTVAL (newval)
 699                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 700
 701       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 702          CONST_INT is not valid, because after the replacement, the
 703          original mode would be gone.  Unfortunately, we can't tell
 704          when do_SUBST is called to replace the operand thereof, so we
 705          perform this test on oldval instead, checking whether an
 706          invalid replacement took place before we got here.  */
 707       gcc_assert (!(GET_CODE (oldval) == SUBREG
 708                     && CONST_INT_P (SUBREG_REG (oldval))));
 709       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 710                     && CONST_INT_P (XEXP (oldval, 0))));
 711     }
 712
 713   if (undobuf.frees)
 714     buf = undobuf.frees, undobuf.frees = buf->next;
 715   else
 716     buf = XNEW (struct undo);
 717
 718   buf->kind = UNDO_RTX;
 719   buf->where.r = into;
 720   buf->old_contents.r = oldval;
 721   *into = newval;
 722
 723   buf->next = undobuf.undos, undobuf.undos = buf;
 724 }
 725
 726 #define SUBST(INTO, NEWVAL)     do_SUBST (&(INTO), (NEWVAL))
 727
 728 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 729    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 730    not safe.  */
 731
 732 static void
 733 do_SUBST_INT (int *into, int newval)
 734 {
 735   struct undo *buf;
 736   int oldval = *into;
 737
 738   if (oldval == newval)
 739     return;
 740
 741   if (undobuf.frees)
 742     buf = undobuf.frees, undobuf.frees = buf->next;
 743   else
 744     buf = XNEW (struct undo);
 745
 746   buf->kind = UNDO_INT;
 747   buf->where.i = into;
 748   buf->old_contents.i = oldval;
 749   *into = newval;
 750
 751   buf->next = undobuf.undos, undobuf.undos = buf;
 752 }
 753
 754 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT (&(INTO), (NEWVAL))
 755
 756 /* Similar to SUBST, but just substitute the mode.  This is used when
 757    changing the mode of a pseudo-register, so that any other
 758    references to the entry in the regno_reg_rtx array will change as
 759    well.  */
 760
 761 static void
 762 subst_mode (int regno, machine_mode newval)
 763 {
 764   struct undo *buf;
 765   rtx reg = regno_reg_rtx[regno];
 766   machine_mode oldval = GET_MODE (reg);
 767
 768   if (oldval == newval)
 769     return;
 770
 771   if (undobuf.frees)
 772     buf = undobuf.frees, undobuf.frees = buf->next;
 773   else
 774     buf = XNEW (struct undo);
 775
 776   buf->kind = UNDO_MODE;
 777   buf->where.regno = regno;
 778   buf->old_contents.m = oldval;
 779   adjust_reg_mode (reg, newval);
 780
 781   buf->next = undobuf.undos, undobuf.undos = buf;
 782 }
 783
 784 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression.  */
 785
 786 static void
 787 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
 788 {
 789   struct undo *buf;
 790   struct insn_link * oldval = *into;
 791
 792   if (oldval == newval)
 793     return;
 794
 795   if (undobuf.frees)
 796     buf = undobuf.frees, undobuf.frees = buf->next;
 797   else
 798     buf = XNEW (struct undo);
 799
 800   buf->kind = UNDO_LINKS;
 801   buf->where.l = into;
 802   buf->old_contents.l = oldval;
 803   *into = newval;
 804
 805   buf->next = undobuf.undos, undobuf.undos = buf;
 806 }
 807
 808 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
 809 \f
 810 /* Subroutine of try_combine.  Determine whether the replacement patterns
 811    NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
 812    than the original sequence I0, I1, I2, I3 and undobuf.other_insn.  Note
 813    that I0, I1 and/or NEWI2PAT may be NULL_RTX.  Similarly, NEWOTHERPAT and
 814    undobuf.other_insn may also both be NULL_RTX.  Return false if the cost
 815    of all the instructions can be estimated and the replacements are more
 816    expensive than the original sequence.  */
 817
 818 static bool
 819 combine_validate_cost (rtx_insn *i0, rtx_insn *i1, rtx_insn *i2, rtx_insn *i3,
 820                        rtx newpat, rtx newi2pat, rtx newotherpat)
 821 {
 822   int i0_cost, i1_cost, i2_cost, i3_cost;
 823   int new_i2_cost, new_i3_cost;
 824   int old_cost, new_cost;
 825
 826   /* Lookup the original insn_costs.  */
 827   i2_cost = INSN_COST (i2);
 828   i3_cost = INSN_COST (i3);
 829
 830   if (i1)
 831     {
 832       i1_cost = INSN_COST (i1);
 833       if (i0)
 834         {
 835           i0_cost = INSN_COST (i0);
 836           old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 837                       ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
 838         }
 839       else
 840         {
 841           old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 842                       ? i1_cost + i2_cost + i3_cost : 0);
 843           i0_cost = 0;
 844         }
 845     }
 846   else
 847     {
 848       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 849       i1_cost = i0_cost = 0;
 850     }
 851
 852   /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
 853      correct that.  */
 854   if (old_cost && i1 && INSN_UID (i1) == INSN_UID (i2))
 855     old_cost -= i1_cost;
 856
 857
 858   /* Calculate the replacement insn_costs.  */
 859   rtx tmp = PATTERN (i3);
 860   PATTERN (i3) = newpat;
 861   int tmpi = INSN_CODE (i3);
 862   INSN_CODE (i3) = -1;
 863   new_i3_cost = insn_cost (i3, optimize_this_for_speed_p);
 864   PATTERN (i3) = tmp;
 865   INSN_CODE (i3) = tmpi;
 866   if (newi2pat)
 867     {
 868       tmp = PATTERN (i2);
 869       PATTERN (i2) = newi2pat;
 870       tmpi = INSN_CODE (i2);
 871       INSN_CODE (i2) = -1;
 872       new_i2_cost = insn_cost (i2, optimize_this_for_speed_p);
 873       PATTERN (i2) = tmp;
 874       INSN_CODE (i2) = tmpi;
 875       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 876                  ? new_i2_cost + new_i3_cost : 0;
 877     }
 878   else
 879     {
 880       new_cost = new_i3_cost;
 881       new_i2_cost = 0;
 882     }
 883
 884   if (undobuf.other_insn)
 885     {
 886       int old_other_cost, new_other_cost;
 887
 888       old_other_cost = INSN_COST (undobuf.other_insn);
 889       tmp = PATTERN (undobuf.other_insn);
 890       PATTERN (undobuf.other_insn) = newotherpat;
 891       tmpi = INSN_CODE (undobuf.other_insn);
 892       INSN_CODE (undobuf.other_insn) = -1;
 893       new_other_cost = insn_cost (undobuf.other_insn,
 894                                   optimize_this_for_speed_p);
 895       PATTERN (undobuf.other_insn) = tmp;
 896       INSN_CODE (undobuf.other_insn) = tmpi;
 897       if (old_other_cost > 0 && new_other_cost > 0)
 898         {
 899           old_cost += old_other_cost;
 900           new_cost += new_other_cost;
 901         }
 902       else
 903         old_cost = 0;
 904     }
 905
 906   /* Disallow this combination if both new_cost and old_cost are greater than
 907      zero, and new_cost is greater than old cost.  */
 908   bool reject = old_cost > 0 && new_cost > old_cost;
 909
 910   if (dump_file)
 911     {
 912       fprintf (dump_file, "%s combination of insns ",
 913                reject ? "rejecting" : "allowing");
 914       if (i0)
 915         fprintf (dump_file, "%d, ", INSN_UID (i0));
 916       if (i1 && INSN_UID (i1) != INSN_UID (i2))
 917         fprintf (dump_file, "%d, ", INSN_UID (i1));
 918       fprintf (dump_file, "%d and %d\n", INSN_UID (i2), INSN_UID (i3));
 919
 920       fprintf (dump_file, "original costs ");
 921       if (i0)
 922         fprintf (dump_file, "%d + ", i0_cost);
 923       if (i1 && INSN_UID (i1) != INSN_UID (i2))
 924         fprintf (dump_file, "%d + ", i1_cost);
 925       fprintf (dump_file, "%d + %d = %d\n", i2_cost, i3_cost, old_cost);
 926
 927       if (newi2pat)
 928         fprintf (dump_file, "replacement costs %d + %d = %d\n",
 929                  new_i2_cost, new_i3_cost, new_cost);
 930       else
 931         fprintf (dump_file, "replacement cost %d\n", new_cost);
 932     }
 933
 934   if (reject)
 935     return false;
 936
 937   /* Update the uid_insn_cost array with the replacement costs.  */
 938   INSN_COST (i2) = new_i2_cost;
 939   INSN_COST (i3) = new_i3_cost;
 940   if (i1)
 941     {
 942       INSN_COST (i1) = 0;
 943       if (i0)
 944         INSN_COST (i0) = 0;
 945     }
 946
 947   return true;
 948 }
 949
 950
 951 /* Delete any insns that copy a register to itself.
 952    Return true if the CFG was changed.  */
 953
 954 static bool
 955 delete_noop_moves (void)
 956 {
 957   rtx_insn *insn, *next;
 958   basic_block bb;
 959
 960   bool edges_deleted = false;
 961
 962   FOR_EACH_BB_FN (bb, cfun)
 963     {
 964       for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
 965         {
 966           next = NEXT_INSN (insn);
 967           if (INSN_P (insn) && noop_move_p (insn))
 968             {
 969               if (dump_file)
 970                 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
 971
 972               edges_deleted |= delete_insn_and_edges (insn);
 973             }
 974         }
 975     }
 976
 977   return edges_deleted;
 978 }
 979
 980 \f
 981 /* Return false if we do not want to (or cannot) combine DEF.  */
 982 static bool
 983 can_combine_def_p (df_ref def)
 984 {
 985   /* Do not consider if it is pre/post modification in MEM.  */
 986   if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
 987     return false;
 988
 989   unsigned int regno = DF_REF_REGNO (def);
 990
 991   /* Do not combine frame pointer adjustments.  */
 992   if ((regno == FRAME_POINTER_REGNUM
 993        && (!reload_completed || frame_pointer_needed))
 994       || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
 995           && regno == HARD_FRAME_POINTER_REGNUM
 996           && (!reload_completed || frame_pointer_needed))
 997       || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
 998           && regno == ARG_POINTER_REGNUM && fixed_regs[regno]))
 999     return false;
1000
1001   return true;
1002 }
1003
1004 /* Return false if we do not want to (or cannot) combine USE.  */
1005 static bool
1006 can_combine_use_p (df_ref use)
1007 {
1008   /* Do not consider the usage of the stack pointer by function call.  */
1009   if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1010     return false;
1011
1012   return true;
1013 }
1014
1015 /* Fill in log links field for all insns.  */
1016
1017 static void
1018 create_log_links (void)
1019 {
1020   basic_block bb;
1021   rtx_insn **next_use;
1022   rtx_insn *insn;
1023   df_ref def, use;
1024
1025   next_use = XCNEWVEC (rtx_insn *, max_reg_num ());
1026
1027   /* Pass through each block from the end, recording the uses of each
1028      register and establishing log links when def is encountered.
1029      Note that we do not clear next_use array in order to save time,
1030      so we have to test whether the use is in the same basic block as def.
1031
1032      There are a few cases below when we do not consider the definition or
1033      usage -- these are taken from original flow.c did. Don't ask me why it is
1034      done this way; I don't know and if it works, I don't want to know.  */
1035
1036   FOR_EACH_BB_FN (bb, cfun)
1037     {
1038       FOR_BB_INSNS_REVERSE (bb, insn)
1039         {
1040           if (!NONDEBUG_INSN_P (insn))
1041             continue;
1042
1043           /* Log links are created only once.  */
1044           gcc_assert (!LOG_LINKS (insn));
1045
1046           FOR_EACH_INSN_DEF (def, insn)
1047             {
1048               unsigned int regno = DF_REF_REGNO (def);
1049               rtx_insn *use_insn;
1050
1051               if (!next_use[regno])
1052                 continue;
1053
1054               if (!can_combine_def_p (def))
1055                 continue;
1056
1057               use_insn = next_use[regno];
1058               next_use[regno] = NULL;
1059
1060               if (BLOCK_FOR_INSN (use_insn) != bb)
1061                 continue;
1062
1063               /* flow.c claimed:
1064
1065                  We don't build a LOG_LINK for hard registers contained
1066                  in ASM_OPERANDs.  If these registers get replaced,
1067                  we might wind up changing the semantics of the insn,
1068                  even if reload can make what appear to be valid
1069                  assignments later.  */
1070               if (regno < FIRST_PSEUDO_REGISTER
1071                   && asm_noperands (PATTERN (use_insn)) >= 0)
1072                 continue;
1073
1074               /* Don't add duplicate links between instructions.  */
1075               struct insn_link *links;
1076               FOR_EACH_LOG_LINK (links, use_insn)
1077                 if (insn == links->insn && regno == links->regno)
1078                   break;
1079
1080               if (!links)
1081                 LOG_LINKS (use_insn)
1082                   = alloc_insn_link (insn, regno, LOG_LINKS (use_insn));
1083             }
1084
1085           FOR_EACH_INSN_USE (use, insn)
1086             if (can_combine_use_p (use))
1087               next_use[DF_REF_REGNO (use)] = insn;
1088         }
1089     }
1090
1091   free (next_use);
1092 }
1093
1094 /* Walk the LOG_LINKS of insn B to see if we find a reference to A.  Return
1095    true if we found a LOG_LINK that proves that A feeds B.  This only works
1096    if there are no instructions between A and B which could have a link
1097    depending on A, since in that case we would not record a link for B.  */
1098
1099 static bool
1100 insn_a_feeds_b (rtx_insn *a, rtx_insn *b)
1101 {
1102   struct insn_link *links;
1103   FOR_EACH_LOG_LINK (links, b)
1104     if (links->insn == a)
1105       return true;
1106   return false;
1107 }
1108 \f
1109 /* Main entry point for combiner.  F is the first insn of the function.
1110    NREGS is the first unused pseudo-reg number.
1111
1112    Return nonzero if the CFG was changed (e.g. if the combiner has
1113    turned an indirect jump instruction into a direct jump).  */
1114 static bool
1115 combine_instructions (rtx_insn *f, unsigned int nregs)
1116 {
1117   rtx_insn *insn, *next;
1118   struct insn_link *links, *nextlinks;
1119   rtx_insn *first;
1120   basic_block last_bb;
1121
1122   bool new_direct_jump_p = false;
1123
1124   for (first = f; first && !NONDEBUG_INSN_P (first); )
1125     first = NEXT_INSN (first);
1126   if (!first)
1127     return false;
1128
1129   combine_attempts = 0;
1130   combine_merges = 0;
1131   combine_extras = 0;
1132   combine_successes = 0;
1133
1134   rtl_hooks = combine_rtl_hooks;
1135
1136   reg_stat.safe_grow_cleared (nregs, true);
1137
1138   init_recog_no_volatile ();
1139
1140   /* Allocate array for insn info.  */
1141   max_uid_known = get_max_uid ();
1142   uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1143   uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1144   gcc_obstack_init (&insn_link_obstack);
1145
1146   nonzero_bits_mode = int_mode_for_size (HOST_BITS_PER_WIDE_INT, 0).require ();
1147
1148   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
1149      problems when, for example, we have j <<= 1 in a loop.  */
1150
1151   nonzero_sign_valid = 0;
1152   label_tick = label_tick_ebb_start = 1;
1153
1154   /* Scan all SETs and see if we can deduce anything about what
1155      bits are known to be zero for some registers and how many copies
1156      of the sign bit are known to exist for those registers.
1157
1158      Also set any known values so that we can use it while searching
1159      for what bits are known to be set.  */
1160
1161   setup_incoming_promotions (first);
1162   /* Allow the entry block and the first block to fall into the same EBB.
1163      Conceptually the incoming promotions are assigned to the entry block.  */
1164   last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1165
1166   create_log_links ();
1167   FOR_EACH_BB_FN (this_basic_block, cfun)
1168     {
1169       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1170       last_call_luid = 0;
1171       mem_last_set = -1;
1172
1173       label_tick++;
1174       if (!single_pred_p (this_basic_block)
1175           || single_pred (this_basic_block) != last_bb)
1176         label_tick_ebb_start = label_tick;
1177       last_bb = this_basic_block;
1178
1179       FOR_BB_INSNS (this_basic_block, insn)
1180         if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1181           {
1182             rtx links;
1183
1184             subst_low_luid = DF_INSN_LUID (insn);
1185             subst_insn = insn;
1186
1187             note_stores (insn, set_nonzero_bits_and_sign_copies, insn);
1188             record_dead_and_set_regs (insn);
1189
1190             if (AUTO_INC_DEC)
1191               for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1192                 if (REG_NOTE_KIND (links) == REG_INC)
1193                   set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1194                                                     insn);
1195
1196             /* Record the current insn_cost of this instruction.  */
1197             INSN_COST (insn) = insn_cost (insn, optimize_this_for_speed_p);
1198             if (dump_file)
1199               {
1200                 fprintf (dump_file, "insn_cost %d for ", INSN_COST (insn));
1201                 dump_insn_slim (dump_file, insn);
1202               }
1203           }
1204     }
1205
1206   nonzero_sign_valid = 1;
1207
1208   /* Now scan all the insns in forward order.  */
1209   label_tick = label_tick_ebb_start = 1;
1210   init_reg_last ();
1211   setup_incoming_promotions (first);
1212   last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1213   int max_combine = param_max_combine_insns;
1214
1215   FOR_EACH_BB_FN (this_basic_block, cfun)
1216     {
1217       rtx_insn *last_combined_insn = NULL;
1218
1219       /* Ignore instruction combination in basic blocks that are going to
1220          be removed as unreachable anyway.  See PR82386.  */
1221       if (EDGE_COUNT (this_basic_block->preds) == 0)
1222         continue;
1223
1224       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1225       last_call_luid = 0;
1226       mem_last_set = -1;
1227
1228       label_tick++;
1229       if (!single_pred_p (this_basic_block)
1230           || single_pred (this_basic_block) != last_bb)
1231         label_tick_ebb_start = label_tick;
1232       last_bb = this_basic_block;
1233
1234       rtl_profile_for_bb (this_basic_block);
1235       for (insn = BB_HEAD (this_basic_block);
1236            insn != NEXT_INSN (BB_END (this_basic_block));
1237            insn = next ? next : NEXT_INSN (insn))
1238         {
1239           next = 0;
1240           if (!NONDEBUG_INSN_P (insn))
1241             continue;
1242
1243           while (last_combined_insn
1244                  && (!NONDEBUG_INSN_P (last_combined_insn)
1245                      || last_combined_insn->deleted ()))
1246             last_combined_insn = PREV_INSN (last_combined_insn);
1247           if (last_combined_insn == NULL_RTX
1248               || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1249               || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1250             last_combined_insn = insn;
1251
1252           /* See if we know about function return values before this
1253              insn based upon SUBREG flags.  */
1254           check_promoted_subreg (insn, PATTERN (insn));
1255
1256           /* See if we can find hardregs and subreg of pseudos in
1257              narrower modes.  This could help turning TRUNCATEs
1258              into SUBREGs.  */
1259           note_uses (&PATTERN (insn), record_truncated_values, NULL);
1260
1261           /* Try this insn with each insn it links back to.  */
1262
1263           FOR_EACH_LOG_LINK (links, insn)
1264             if ((next = try_combine (insn, links->insn, NULL,
1265                                      NULL, &new_direct_jump_p,
1266                                      last_combined_insn)) != 0)
1267               {
1268                 statistics_counter_event (cfun, "two-insn combine", 1);
1269                 goto retry;
1270               }
1271
1272           /* Try each sequence of three linked insns ending with this one.  */
1273
1274           if (max_combine >= 3)
1275             FOR_EACH_LOG_LINK (links, insn)
1276               {
1277                 rtx_insn *link = links->insn;
1278
1279                 /* If the linked insn has been replaced by a note, then there
1280                    is no point in pursuing this chain any further.  */
1281                 if (NOTE_P (link))
1282                   continue;
1283
1284                 FOR_EACH_LOG_LINK (nextlinks, link)
1285                   if ((next = try_combine (insn, link, nextlinks->insn,
1286                                            NULL, &new_direct_jump_p,
1287                                            last_combined_insn)) != 0)
1288                     {
1289                       statistics_counter_event (cfun, "three-insn combine", 1);
1290                       goto retry;
1291                     }
1292               }
1293
1294           /* Try combining an insn with two different insns whose results it
1295              uses.  */
1296           if (max_combine >= 3)
1297             FOR_EACH_LOG_LINK (links, insn)
1298               for (nextlinks = links->next; nextlinks;
1299                    nextlinks = nextlinks->next)
1300                 if ((next = try_combine (insn, links->insn,
1301                                          nextlinks->insn, NULL,
1302                                          &new_direct_jump_p,
1303                                          last_combined_insn)) != 0)
1304
1305                   {
1306                     statistics_counter_event (cfun, "three-insn combine", 1);
1307                     goto retry;
1308                   }
1309
1310           /* Try four-instruction combinations.  */
1311           if (max_combine >= 4)
1312             FOR_EACH_LOG_LINK (links, insn)
1313               {
1314                 struct insn_link *next1;
1315                 rtx_insn *link = links->insn;
1316
1317                 /* If the linked insn has been replaced by a note, then there
1318                    is no point in pursuing this chain any further.  */
1319                 if (NOTE_P (link))
1320                   continue;
1321
1322                 FOR_EACH_LOG_LINK (next1, link)
1323                   {
1324                     rtx_insn *link1 = next1->insn;
1325                     if (NOTE_P (link1))
1326                       continue;
1327                     /* I0 -> I1 -> I2 -> I3.  */
1328                     FOR_EACH_LOG_LINK (nextlinks, link1)
1329                       if ((next = try_combine (insn, link, link1,
1330                                                nextlinks->insn,
1331                                                &new_direct_jump_p,
1332                                                last_combined_insn)) != 0)
1333                         {
1334                           statistics_counter_event (cfun, "four-insn combine", 1);
1335                           goto retry;
1336                         }
1337                     /* I0, I1 -> I2, I2 -> I3.  */
1338                     for (nextlinks = next1->next; nextlinks;
1339                          nextlinks = nextlinks->next)
1340                       if ((next = try_combine (insn, link, link1,
1341                                                nextlinks->insn,
1342                                                &new_direct_jump_p,
1343                                                last_combined_insn)) != 0)
1344                         {
1345                           statistics_counter_event (cfun, "four-insn combine", 1);
1346                           goto retry;
1347                         }
1348                   }
1349
1350                 for (next1 = links->next; next1; next1 = next1->next)
1351                   {
1352                     rtx_insn *link1 = next1->insn;
1353                     if (NOTE_P (link1))
1354                       continue;
1355                     /* I0 -> I2; I1, I2 -> I3.  */
1356                     FOR_EACH_LOG_LINK (nextlinks, link)
1357                       if ((next = try_combine (insn, link, link1,
1358                                                nextlinks->insn,
1359                                                &new_direct_jump_p,
1360                                                last_combined_insn)) != 0)
1361                         {
1362                           statistics_counter_event (cfun, "four-insn combine", 1);
1363                           goto retry;
1364                         }
1365                     /* I0 -> I1; I1, I2 -> I3.  */
1366                     FOR_EACH_LOG_LINK (nextlinks, link1)
1367                       if ((next = try_combine (insn, link, link1,
1368                                                nextlinks->insn,
1369                                                &new_direct_jump_p,
1370                                                last_combined_insn)) != 0)
1371                         {
1372                           statistics_counter_event (cfun, "four-insn combine", 1);
1373                           goto retry;
1374                         }
1375                   }
1376               }
1377
1378           /* Try this insn with each REG_EQUAL note it links back to.  */
1379           FOR_EACH_LOG_LINK (links, insn)
1380             {
1381               rtx set, note;
1382               rtx_insn *temp = links->insn;
1383               if ((set = single_set (temp)) != 0
1384                   && (note = find_reg_equal_equiv_note (temp)) != 0
1385                   && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1386                   && ! side_effects_p (SET_SRC (set))
1387                   /* Avoid using a register that may already been marked
1388                      dead by an earlier instruction.  */
1389                   && ! unmentioned_reg_p (note, SET_SRC (set))
1390                   && (GET_MODE (note) == VOIDmode
1391                       ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1392                       : (GET_MODE (SET_DEST (set)) == GET_MODE (note)
1393                          && (GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
1394                              || (GET_MODE (XEXP (SET_DEST (set), 0))
1395                                  == GET_MODE (note))))))
1396                 {
1397                   /* Temporarily replace the set's source with the
1398                      contents of the REG_EQUAL note.  The insn will
1399                      be deleted or recognized by try_combine.  */
1400                   rtx orig_src = SET_SRC (set);
1401                   rtx orig_dest = SET_DEST (set);
1402                   if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT)
1403                     SET_DEST (set) = XEXP (SET_DEST (set), 0);
1404                   SET_SRC (set) = note;
1405                   i2mod = temp;
1406                   i2mod_old_rhs = copy_rtx (orig_src);
1407                   i2mod_new_rhs = copy_rtx (note);
1408                   next = try_combine (insn, i2mod, NULL, NULL,
1409                                       &new_direct_jump_p,
1410                                       last_combined_insn);
1411                   i2mod = NULL;
1412                   if (next)
1413                     {
1414                       statistics_counter_event (cfun, "insn-with-note combine", 1);
1415                       goto retry;
1416                     }
1417                   INSN_CODE (temp) = -1;
1418                   SET_SRC (set) = orig_src;
1419                   SET_DEST (set) = orig_dest;
1420                 }
1421             }
1422
1423           if (!NOTE_P (insn))
1424             record_dead_and_set_regs (insn);
1425
1426 retry:
1427           ;
1428         }
1429     }
1430
1431   default_rtl_profile ();
1432   clear_bb_flags ();
1433
1434   if (purge_all_dead_edges ())
1435     new_direct_jump_p = true;
1436   if (delete_noop_moves ())
1437     new_direct_jump_p = true;
1438
1439   /* Clean up.  */
1440   obstack_free (&insn_link_obstack, NULL);
1441   free (uid_log_links);
1442   free (uid_insn_cost);
1443   reg_stat.release ();
1444
1445   {
1446     struct undo *undo, *next;
1447     for (undo = undobuf.frees; undo; undo = next)
1448       {
1449         next = undo->next;
1450         free (undo);
1451       }
1452     undobuf.frees = 0;
1453   }
1454
1455   statistics_counter_event (cfun, "attempts", combine_attempts);
1456   statistics_counter_event (cfun, "merges", combine_merges);
1457   statistics_counter_event (cfun, "extras", combine_extras);
1458   statistics_counter_event (cfun, "successes", combine_successes);
1459
1460   nonzero_sign_valid = 0;
1461   rtl_hooks = general_rtl_hooks;
1462
1463   /* Make recognizer allow volatile MEMs again.  */
1464   init_recog ();
1465
1466   return new_direct_jump_p;
1467 }
1468
1469 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
1470
1471 static void
1472 init_reg_last (void)
1473 {
1474   unsigned int i;
1475   reg_stat_type *p;
1476
1477   FOR_EACH_VEC_ELT (reg_stat, i, p)
1478     memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1479 }
1480 \f
1481 /* Set up any promoted values for incoming argument registers.  */
1482
1483 static void
1484 setup_incoming_promotions (rtx_insn *first)
1485 {
1486   tree arg;
1487   bool strictly_local = false;
1488
1489   for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1490        arg = DECL_CHAIN (arg))
1491     {
1492       rtx x, reg = DECL_INCOMING_RTL (arg);
1493       int uns1, uns3;
1494       machine_mode mode1, mode2, mode3, mode4;
1495
1496       /* Only continue if the incoming argument is in a register.  */
1497       if (!REG_P (reg))
1498         continue;
1499
1500       /* Determine, if possible, whether all call sites of the current
1501          function lie within the current compilation unit.  (This does
1502          take into account the exporting of a function via taking its
1503          address, and so forth.)  */
1504       strictly_local
1505         = cgraph_node::local_info_node (current_function_decl)->local;
1506
1507       /* The mode and signedness of the argument before any promotions happen
1508          (equal to the mode of the pseudo holding it at that stage).  */
1509       mode1 = TYPE_MODE (TREE_TYPE (arg));
1510       uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1511
1512       /* The mode and signedness of the argument after any source language and
1513          TARGET_PROMOTE_PROTOTYPES-driven promotions.  */
1514       mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1515       uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1516
1517       /* The mode and signedness of the argument as it is actually passed,
1518          see assign_parm_setup_reg in function.cc.  */
1519       mode3 = promote_function_mode (TREE_TYPE (arg), mode1, &uns3,
1520                                      TREE_TYPE (cfun->decl), 0);
1521
1522       /* The mode of the register in which the argument is being passed.  */
1523       mode4 = GET_MODE (reg);
1524
1525       /* Eliminate sign extensions in the callee when:
1526          (a) A mode promotion has occurred;  */
1527       if (mode1 == mode3)
1528         continue;
1529       /* (b) The mode of the register is the same as the mode of
1530              the argument as it is passed; */
1531       if (mode3 != mode4)
1532         continue;
1533       /* (c) There's no language level extension;  */
1534       if (mode1 == mode2)
1535         ;
1536       /* (c.1) All callers are from the current compilation unit.  If that's
1537          the case we don't have to rely on an ABI, we only have to know
1538          what we're generating right now, and we know that we will do the
1539          mode1 to mode2 promotion with the given sign.  */
1540       else if (!strictly_local)
1541         continue;
1542       /* (c.2) The combination of the two promotions is useful.  This is
1543          true when the signs match, or if the first promotion is unsigned.
1544          In the later case, (sign_extend (zero_extend x)) is the same as
1545          (zero_extend (zero_extend x)), so make sure to force UNS3 true.  */
1546       else if (uns1)
1547         uns3 = true;
1548       else if (uns3)
1549         continue;
1550
1551       /* Record that the value was promoted from mode1 to mode3,
1552          so that any sign extension at the head of the current
1553          function may be eliminated.  */
1554       x = gen_rtx_CLOBBER (mode1, const0_rtx);
1555       x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1556       record_value_for_reg (reg, first, x);
1557     }
1558 }
1559
1560 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1561    that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1562    because some machines (maybe most) will actually do the sign-extension and
1563    this is the conservative approach.
1564
1565    ??? For 2.5, try to tighten up the MD files in this regard instead of this
1566    kludge.  */
1567
1568 static rtx
1569 sign_extend_short_imm (rtx src, machine_mode mode, unsigned int prec)
1570 {
1571   scalar_int_mode int_mode;
1572   if (CONST_INT_P (src)
1573       && is_a <scalar_int_mode> (mode, &int_mode)
1574       && GET_MODE_PRECISION (int_mode) < prec
1575       && INTVAL (src) > 0
1576       && val_signbit_known_set_p (int_mode, INTVAL (src)))
1577     src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (int_mode));
1578
1579   return src;
1580 }
1581
1582 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1583    and SET.  */
1584
1585 static void
1586 update_rsp_from_reg_equal (reg_stat_type *rsp, rtx_insn *insn, const_rtx set,
1587                            rtx x)
1588 {
1589   rtx reg_equal_note = insn ? find_reg_equal_equiv_note (insn) : NULL_RTX;
1590   unsigned HOST_WIDE_INT bits = 0;
1591   rtx reg_equal = NULL, src = SET_SRC (set);
1592   unsigned int num = 0;
1593
1594   if (reg_equal_note)
1595     reg_equal = XEXP (reg_equal_note, 0);
1596
1597   if (SHORT_IMMEDIATES_SIGN_EXTEND)
1598     {
1599       src = sign_extend_short_imm (src, GET_MODE (x), BITS_PER_WORD);
1600       if (reg_equal)
1601         reg_equal = sign_extend_short_imm (reg_equal, GET_MODE (x), BITS_PER_WORD);
1602     }
1603
1604   /* Don't call nonzero_bits if it cannot change anything.  */
1605   if (rsp->nonzero_bits != HOST_WIDE_INT_M1U)
1606     {
1607       machine_mode mode = GET_MODE (x);
1608       if (GET_MODE_CLASS (mode) == MODE_INT
1609           && HWI_COMPUTABLE_MODE_P (mode))
1610         mode = nonzero_bits_mode;
1611       bits = nonzero_bits (src, mode);
1612       if (reg_equal && bits)
1613         bits &= nonzero_bits (reg_equal, mode);
1614       rsp->nonzero_bits |= bits;
1615     }
1616
1617   /* Don't call num_sign_bit_copies if it cannot change anything.  */
1618   if (rsp->sign_bit_copies != 1)
1619     {
1620       num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1621       if (reg_equal && maybe_ne (num, GET_MODE_PRECISION (GET_MODE (x))))
1622         {
1623           unsigned int numeq = num_sign_bit_copies (reg_equal, GET_MODE (x));
1624           if (num == 0 || numeq > num)
1625             num = numeq;
1626         }
1627       if (rsp->sign_bit_copies == 0 || num < rsp->sign_bit_copies)
1628         rsp->sign_bit_copies = num;
1629     }
1630 }
1631
1632 /* Called via note_stores.  If X is a pseudo that is narrower than
1633    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1634
1635    If we are setting only a portion of X and we can't figure out what
1636    portion, assume all bits will be used since we don't know what will
1637    be happening.
1638
1639    Similarly, set how many bits of X are known to be copies of the sign bit
1640    at all locations in the function.  This is the smallest number implied
1641    by any set of X.  */
1642
1643 static void
1644 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1645 {
1646   rtx_insn *insn = (rtx_insn *) data;
1647   scalar_int_mode mode;
1648
1649   if (REG_P (x)
1650       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1651       /* If this register is undefined at the start of the file, we can't
1652          say what its contents were.  */
1653       && ! REGNO_REG_SET_P
1654            (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), REGNO (x))
1655       && is_a <scalar_int_mode> (GET_MODE (x), &mode)
1656       && HWI_COMPUTABLE_MODE_P (mode))
1657     {
1658       reg_stat_type *rsp = &reg_stat[REGNO (x)];
1659
1660       if (set == 0 || GET_CODE (set) == CLOBBER)
1661         {
1662           rsp->nonzero_bits = GET_MODE_MASK (mode);
1663           rsp->sign_bit_copies = 1;
1664           return;
1665         }
1666
1667       /* If this register is being initialized using itself, and the
1668          register is uninitialized in this basic block, and there are
1669          no LOG_LINKS which set the register, then part of the
1670          register is uninitialized.  In that case we can't assume
1671          anything about the number of nonzero bits.
1672
1673          ??? We could do better if we checked this in
1674          reg_{nonzero_bits,num_sign_bit_copies}_for_combine.  Then we
1675          could avoid making assumptions about the insn which initially
1676          sets the register, while still using the information in other
1677          insns.  We would have to be careful to check every insn
1678          involved in the combination.  */
1679
1680       if (insn
1681           && reg_referenced_p (x, PATTERN (insn))
1682           && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1683                                REGNO (x)))
1684         {
1685           struct insn_link *link;
1686
1687           FOR_EACH_LOG_LINK (link, insn)
1688             if (dead_or_set_p (link->insn, x))
1689               break;
1690           if (!link)
1691             {
1692               rsp->nonzero_bits = GET_MODE_MASK (mode);
1693               rsp->sign_bit_copies = 1;
1694               return;
1695             }
1696         }
1697
1698       /* If this is a complex assignment, see if we can convert it into a
1699          simple assignment.  */
1700       set = expand_field_assignment (set);
1701
1702       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1703          set what we know about X.  */
1704
1705       if (SET_DEST (set) == x
1706           || (paradoxical_subreg_p (SET_DEST (set))
1707               && SUBREG_REG (SET_DEST (set)) == x))
1708         update_rsp_from_reg_equal (rsp, insn, set, x);
1709       else
1710         {
1711           rsp->nonzero_bits = GET_MODE_MASK (mode);
1712           rsp->sign_bit_copies = 1;
1713         }
1714     }
1715 }
1716 \f
1717 /* See if INSN can be combined into I3.  PRED, PRED2, SUCC and SUCC2 are
1718    optionally insns that were previously combined into I3 or that will be
1719    combined into the merger of INSN and I3.  The order is PRED, PRED2,
1720    INSN, SUCC, SUCC2, I3.
1721
1722    Return false if the combination is not allowed for any reason.
1723
1724    If the combination is allowed, *PDEST will be set to the single
1725    destination of INSN and *PSRC to the single source, and this function
1726    will return true.  */
1727
1728 static bool
1729 can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED,
1730                rtx_insn *pred2 ATTRIBUTE_UNUSED, rtx_insn *succ, rtx_insn *succ2,
1731                rtx *pdest, rtx *psrc)
1732 {
1733   int i;
1734   const_rtx set = 0;
1735   rtx src, dest;
1736   rtx_insn *p;
1737   rtx link;
1738   bool all_adjacent = true;
1739   bool (*is_volatile_p) (const_rtx);
1740
1741   if (succ)
1742     {
1743       if (succ2)
1744         {
1745           if (next_active_insn (succ2) != i3)
1746             all_adjacent = false;
1747           if (next_active_insn (succ) != succ2)
1748             all_adjacent = false;
1749         }
1750       else if (next_active_insn (succ) != i3)
1751         all_adjacent = false;
1752       if (next_active_insn (insn) != succ)
1753         all_adjacent = false;
1754     }
1755   else if (next_active_insn (insn) != i3)
1756     all_adjacent = false;
1757
1758   /* Can combine only if previous insn is a SET of a REG or a SUBREG,
1759      or a PARALLEL consisting of such a SET and CLOBBERs.
1760
1761      If INSN has CLOBBER parallel parts, ignore them for our processing.
1762      By definition, these happen during the execution of the insn.  When it
1763      is merged with another insn, all bets are off.  If they are, in fact,
1764      needed and aren't also supplied in I3, they may be added by
1765      recog_for_combine.  Otherwise, it won't match.
1766
1767      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1768      note.
1769
1770      Get the source and destination of INSN.  If more than one, can't
1771      combine.  */
1772
1773   if (GET_CODE (PATTERN (insn)) == SET)
1774     set = PATTERN (insn);
1775   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1776            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1777     {
1778       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1779         {
1780           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1781
1782           switch (GET_CODE (elt))
1783             {
1784             /* This is important to combine floating point insns
1785                for the SH4 port.  */
1786             case USE:
1787               /* Combining an isolated USE doesn't make sense.
1788                  We depend here on combinable_i3pat to reject them.  */
1789               /* The code below this loop only verifies that the inputs of
1790                  the SET in INSN do not change.  We call reg_set_between_p
1791                  to verify that the REG in the USE does not change between
1792                  I3 and INSN.
1793                  If the USE in INSN was for a pseudo register, the matching
1794                  insn pattern will likely match any register; combining this
1795                  with any other USE would only be safe if we knew that the
1796                  used registers have identical values, or if there was
1797                  something to tell them apart, e.g. different modes.  For
1798                  now, we forgo such complicated tests and simply disallow
1799                  combining of USES of pseudo registers with any other USE.  */
1800               if (REG_P (XEXP (elt, 0))
1801                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1802                 {
1803                   rtx i3pat = PATTERN (i3);
1804                   int i = XVECLEN (i3pat, 0) - 1;
1805                   unsigned int regno = REGNO (XEXP (elt, 0));
1806
1807                   do
1808                     {
1809                       rtx i3elt = XVECEXP (i3pat, 0, i);
1810
1811                       if (GET_CODE (i3elt) == USE
1812                           && REG_P (XEXP (i3elt, 0))
1813                           && (REGNO (XEXP (i3elt, 0)) == regno
1814                               ? reg_set_between_p (XEXP (elt, 0),
1815                                                    PREV_INSN (insn), i3)
1816                               : regno >= FIRST_PSEUDO_REGISTER))
1817                         return false;
1818                     }
1819                   while (--i >= 0);
1820                 }
1821               break;
1822
1823               /* We can ignore CLOBBERs.  */
1824             case CLOBBER:
1825               break;
1826
1827             case SET:
1828               /* Ignore SETs whose result isn't used but not those that
1829                  have side-effects.  */
1830               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1831                   && insn_nothrow_p (insn)
1832                   && !side_effects_p (elt))
1833                 break;
1834
1835               /* If we have already found a SET, this is a second one and
1836                  so we cannot combine with this insn.  */
1837               if (set)
1838                 return false;
1839
1840               set = elt;
1841               break;
1842
1843             default:
1844               /* Anything else means we can't combine.  */
1845               return false;
1846             }
1847         }
1848
1849       if (set == 0
1850           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1851              so don't do anything with it.  */
1852           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1853         return false;
1854     }
1855   else
1856     return false;
1857
1858   if (set == 0)
1859     return false;
1860
1861   /* The simplification in expand_field_assignment may call back to
1862      get_last_value, so set safe guard here.  */
1863   subst_low_luid = DF_INSN_LUID (insn);
1864
1865   set = expand_field_assignment (set);
1866   src = SET_SRC (set), dest = SET_DEST (set);
1867
1868   /* Do not eliminate user-specified register if it is in an
1869      asm input because we may break the register asm usage defined
1870      in GCC manual if allow to do so.
1871      Be aware that this may cover more cases than we expect but this
1872      should be harmless.  */
1873   if (REG_P (dest) && REG_USERVAR_P (dest) && HARD_REGISTER_P (dest)
1874       && extract_asm_operands (PATTERN (i3)))
1875     return false;
1876
1877   /* Don't eliminate a store in the stack pointer.  */
1878   if (dest == stack_pointer_rtx
1879       /* Don't combine with an insn that sets a register to itself if it has
1880          a REG_EQUAL note.  This may be part of a LIBCALL sequence.  */
1881       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1882       /* Can't merge an ASM_OPERANDS.  */
1883       || GET_CODE (src) == ASM_OPERANDS
1884       /* Can't merge a function call.  */
1885       || GET_CODE (src) == CALL
1886       /* Don't eliminate a function call argument.  */
1887       || (CALL_P (i3)
1888           && (find_reg_fusage (i3, USE, dest)
1889               || (REG_P (dest)
1890                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1891                   && global_regs[REGNO (dest)])))
1892       /* Don't substitute into an incremented register.  */
1893       || FIND_REG_INC_NOTE (i3, dest)
1894       || (succ && FIND_REG_INC_NOTE (succ, dest))
1895       || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1896       /* Don't substitute into a non-local goto, this confuses CFG.  */
1897       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1898       /* Make sure that DEST is not used after INSN but before SUCC, or
1899          after SUCC and before SUCC2, or after SUCC2 but before I3.  */
1900       || (!all_adjacent
1901           && ((succ2
1902                && (reg_used_between_p (dest, succ2, i3)
1903                    || reg_used_between_p (dest, succ, succ2)))
1904               || (!succ2 && succ && reg_used_between_p (dest, succ, i3))
1905               || (!succ2 && !succ && reg_used_between_p (dest, insn, i3))
1906               || (succ
1907                   /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1908                      that case SUCC is not in the insn stream, so use SUCC2
1909                      instead for this test.  */
1910                   && reg_used_between_p (dest, insn,
1911                                          succ2
1912                                          && INSN_UID (succ) == INSN_UID (succ2)
1913                                          ? succ2 : succ))))
1914       /* Make sure that the value that is to be substituted for the register
1915          does not use any registers whose values alter in between.  However,
1916          If the insns are adjacent, a use can't cross a set even though we
1917          think it might (this can happen for a sequence of insns each setting
1918          the same destination; last_set of that register might point to
1919          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1920          equivalent to the memory so the substitution is valid even if there
1921          are intervening stores.  Also, don't move a volatile asm or
1922          UNSPEC_VOLATILE across any other insns.  */
1923       || (! all_adjacent
1924           && (((!MEM_P (src)
1925                 || ! find_reg_note (insn, REG_EQUIV, src))
1926                && modified_between_p (src, insn, i3))
1927               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1928               || GET_CODE (src) == UNSPEC_VOLATILE))
1929       /* Don't combine across a CALL_INSN, because that would possibly
1930          change whether the life span of some REGs crosses calls or not,
1931          and it is a pain to update that information.
1932          Exception: if source is a constant, moving it later can't hurt.
1933          Accept that as a special case.  */
1934       || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1935     return false;
1936
1937   /* DEST must be a REG.  */
1938   if (REG_P (dest))
1939     {
1940       /* If register alignment is being enforced for multi-word items in all
1941          cases except for parameters, it is possible to have a register copy
1942          insn referencing a hard register that is not allowed to contain the
1943          mode being copied and which would not be valid as an operand of most
1944          insns.  Eliminate this problem by not combining with such an insn.
1945
1946          Also, on some machines we don't want to extend the life of a hard
1947          register.  */
1948
1949       if (REG_P (src)
1950           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1951                && !targetm.hard_regno_mode_ok (REGNO (dest), GET_MODE (dest)))
1952               /* Don't extend the life of a hard register unless it is
1953                  user variable (if we have few registers) or it can't
1954                  fit into the desired register (meaning something special
1955                  is going on).
1956                  Also avoid substituting a return register into I3, because
1957                  reload can't handle a conflict with constraints of other
1958                  inputs.  */
1959               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1960                   && !targetm.hard_regno_mode_ok (REGNO (src),
1961                                                   GET_MODE (src)))))
1962         return false;
1963     }
1964   else
1965     return false;
1966
1967
1968   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1969     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1970       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1971         {
1972           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1973
1974           /* If the clobber represents an earlyclobber operand, we must not
1975              substitute an expression containing the clobbered register.
1976              As we do not analyze the constraint strings here, we have to
1977              make the conservative assumption.  However, if the register is
1978              a fixed hard reg, the clobber cannot represent any operand;
1979              we leave it up to the machine description to either accept or
1980              reject use-and-clobber patterns.  */
1981           if (!REG_P (reg)
1982               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1983               || !fixed_regs[REGNO (reg)])
1984             if (reg_overlap_mentioned_p (reg, src))
1985               return false;
1986         }
1987
1988   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1989      or not), reject, unless nothing volatile comes between it and I3 */
1990
1991   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1992     {
1993       /* Make sure neither succ nor succ2 contains a volatile reference.  */
1994       if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1995         return false;
1996       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1997         return false;
1998       /* We'll check insns between INSN and I3 below.  */
1999     }
2000
2001   /* If INSN is an asm, and DEST is a hard register, reject, since it has
2002      to be an explicit register variable, and was chosen for a reason.  */
2003
2004   if (GET_CODE (src) == ASM_OPERANDS
2005       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
2006     return false;
2007
2008   /* If INSN contains volatile references (specifically volatile MEMs),
2009      we cannot combine across any other volatile references.
2010      Even if INSN doesn't contain volatile references, any intervening
2011      volatile insn might affect machine state.  */
2012
2013   is_volatile_p = volatile_refs_p (PATTERN (insn))
2014     ? volatile_refs_p
2015     : volatile_insn_p;
2016
2017   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
2018     if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
2019       return false;
2020
2021   /* If INSN contains an autoincrement or autodecrement, make sure that
2022      register is not used between there and I3, and not already used in
2023      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
2024      Also insist that I3 not be a jump if using LRA; if it were one
2025      and the incremented register were spilled, we would lose.
2026      Reload handles this correctly.  */
2027
2028   if (AUTO_INC_DEC)
2029     for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2030       if (REG_NOTE_KIND (link) == REG_INC
2031           && ((JUMP_P (i3) && targetm.lra_p ())
2032               || reg_used_between_p (XEXP (link, 0), insn, i3)
2033               || (pred != NULL_RTX
2034                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
2035               || (pred2 != NULL_RTX
2036                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
2037               || (succ != NULL_RTX
2038                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
2039               || (succ2 != NULL_RTX
2040                   && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
2041               || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
2042         return false;
2043
2044   /* If we get here, we have passed all the tests and the combination is
2045      to be allowed.  */
2046
2047   *pdest = dest;
2048   *psrc = src;
2049
2050   return true;
2051 }
2052 \f
2053 /* LOC is the location within I3 that contains its pattern or the component
2054    of a PARALLEL of the pattern.  We validate that it is valid for combining.
2055
2056    One problem is if I3 modifies its output, as opposed to replacing it
2057    entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2058    doing so would produce an insn that is not equivalent to the original insns.
2059
2060    Consider:
2061
2062          (set (reg:DI 101) (reg:DI 100))
2063          (set (subreg:SI (reg:DI 101) 0) <foo>)
2064
2065    This is NOT equivalent to:
2066
2067          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2068                     (set (reg:DI 101) (reg:DI 100))])
2069
2070    Not only does this modify 100 (in which case it might still be valid
2071    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2072
2073    We can also run into a problem if I2 sets a register that I1
2074    uses and I1 gets directly substituted into I3 (not via I2).  In that
2075    case, we would be getting the wrong value of I2DEST into I3, so we
2076    must reject the combination.  This case occurs when I2 and I1 both
2077    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2078    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2079    of a SET must prevent combination from occurring.  The same situation
2080    can occur for I0, in which case I0_NOT_IN_SRC is set.
2081
2082    Before doing the above check, we first try to expand a field assignment
2083    into a set of logical operations.
2084
2085    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2086    we place a register that is both set and used within I3.  If more than one
2087    such register is detected, we fail.
2088
2089    Return true if the combination is valid, false otherwise.  */
2090
2091 static bool
2092 combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2093                   bool i1_not_in_src, bool i0_not_in_src, rtx *pi3dest_killed)
2094 {
2095   rtx x = *loc;
2096
2097   if (GET_CODE (x) == SET)
2098     {
2099       rtx set = x ;
2100       rtx dest = SET_DEST (set);
2101       rtx src = SET_SRC (set);
2102       rtx inner_dest = dest;
2103       rtx subdest;
2104
2105       while (GET_CODE (inner_dest) == STRICT_LOW_PART
2106              || GET_CODE (inner_dest) == SUBREG
2107              || GET_CODE (inner_dest) == ZERO_EXTRACT)
2108         inner_dest = XEXP (inner_dest, 0);
2109
2110       /* Check for the case where I3 modifies its output, as discussed
2111          above.  We don't want to prevent pseudos from being combined
2112          into the address of a MEM, so only prevent the combination if
2113          i1 or i2 set the same MEM.  */
2114       if ((inner_dest != dest &&
2115            (!MEM_P (inner_dest)
2116             || rtx_equal_p (i2dest, inner_dest)
2117             || (i1dest && rtx_equal_p (i1dest, inner_dest))
2118             || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2119            && (reg_overlap_mentioned_p (i2dest, inner_dest)
2120                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2121                || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2122
2123           /* This is the same test done in can_combine_p except we can't test
2124              all_adjacent; we don't have to, since this instruction will stay
2125              in place, thus we are not considering increasing the lifetime of
2126              INNER_DEST.
2127
2128              Also, if this insn sets a function argument, combining it with
2129              something that might need a spill could clobber a previous
2130              function argument; the all_adjacent test in can_combine_p also
2131              checks this; here, we do a more specific test for this case.  */
2132
2133           || (REG_P (inner_dest)
2134               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2135               && !targetm.hard_regno_mode_ok (REGNO (inner_dest),
2136                                               GET_MODE (inner_dest)))
2137           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2138           || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2139         return false;
2140
2141       /* If DEST is used in I3, it is being killed in this insn, so
2142          record that for later.  We have to consider paradoxical
2143          subregs here, since they kill the whole register, but we
2144          ignore partial subregs, STRICT_LOW_PART, etc.
2145          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2146          STACK_POINTER_REGNUM, since these are always considered to be
2147          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
2148       subdest = dest;
2149       if (GET_CODE (subdest) == SUBREG && !partial_subreg_p (subdest))
2150         subdest = SUBREG_REG (subdest);
2151       if (pi3dest_killed
2152           && REG_P (subdest)
2153           && reg_referenced_p (subdest, PATTERN (i3))
2154           && REGNO (subdest) != FRAME_POINTER_REGNUM
2155           && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2156               || REGNO (subdest) != HARD_FRAME_POINTER_REGNUM)
2157           && (FRAME_POINTER_REGNUM == ARG_POINTER_REGNUM
2158               || (REGNO (subdest) != ARG_POINTER_REGNUM
2159                   || ! fixed_regs [REGNO (subdest)]))
2160           && REGNO (subdest) != STACK_POINTER_REGNUM)
2161         {
2162           if (*pi3dest_killed)
2163             return false;
2164
2165           *pi3dest_killed = subdest;
2166         }
2167     }
2168
2169   else if (GET_CODE (x) == PARALLEL)
2170     {
2171       int i;
2172
2173       for (i = 0; i < XVECLEN (x, 0); i++)
2174         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2175                                 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2176           return false;
2177     }
2178
2179   return true;
2180 }
2181 \f
2182 /* Return true if X is an arithmetic expression that contains a multiplication
2183    and division.  We don't count multiplications by powers of two here.  */
2184
2185 static bool
2186 contains_muldiv (rtx x)
2187 {
2188   switch (GET_CODE (x))
2189     {
2190     case MOD:  case DIV:  case UMOD:  case UDIV:
2191       return true;
2192
2193     case MULT:
2194       return ! (CONST_INT_P (XEXP (x, 1))
2195                 && pow2p_hwi (UINTVAL (XEXP (x, 1))));
2196     default:
2197       if (BINARY_P (x))
2198         return contains_muldiv (XEXP (x, 0))
2199             || contains_muldiv (XEXP (x, 1));
2200
2201       if (UNARY_P (x))
2202         return contains_muldiv (XEXP (x, 0));
2203
2204       return false;
2205     }
2206 }
2207 \f
2208 /* Determine whether INSN can be used in a combination.  Return true if
2209    not.  This is used in try_combine to detect early some cases where we
2210    can't perform combinations.  */
2211
2212 static bool
2213 cant_combine_insn_p (rtx_insn *insn)
2214 {
2215   rtx set;
2216   rtx src, dest;
2217
2218   /* If this isn't really an insn, we can't do anything.
2219      This can occur when flow deletes an insn that it has merged into an
2220      auto-increment address.  */
2221   if (!NONDEBUG_INSN_P (insn))
2222     return true;
2223
2224   /* Never combine loads and stores involving hard regs that are likely
2225      to be spilled.  The register allocator can usually handle such
2226      reg-reg moves by tying.  If we allow the combiner to make
2227      substitutions of likely-spilled regs, reload might die.
2228      As an exception, we allow combinations involving fixed regs; these are
2229      not available to the register allocator so there's no risk involved.  */
2230
2231   set = single_set (insn);
2232   if (! set)
2233     return false;
2234   src = SET_SRC (set);
2235   dest = SET_DEST (set);
2236   if (GET_CODE (src) == SUBREG)
2237     src = SUBREG_REG (src);
2238   if (GET_CODE (dest) == SUBREG)
2239     dest = SUBREG_REG (dest);
2240   if (REG_P (src) && REG_P (dest)
2241       && ((HARD_REGISTER_P (src)
2242            && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2243 #ifdef LEAF_REGISTERS
2244            && ! LEAF_REGISTERS [REGNO (src)])
2245 #else
2246            )
2247 #endif
2248           || (HARD_REGISTER_P (dest)
2249               && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2250               && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2251     return true;
2252
2253   return false;
2254 }
2255
2256 struct likely_spilled_retval_info
2257 {
2258   unsigned regno, nregs;
2259   unsigned mask;
2260 };
2261
2262 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
2263    hard registers that are known to be written to / clobbered in full.  */
2264 static void
2265 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2266 {
2267   struct likely_spilled_retval_info *const info =
2268     (struct likely_spilled_retval_info *) data;
2269   unsigned regno, nregs;
2270   unsigned new_mask;
2271
2272   if (!REG_P (XEXP (set, 0)))
2273     return;
2274   regno = REGNO (x);
2275   if (regno >= info->regno + info->nregs)
2276     return;
2277   nregs = REG_NREGS (x);
2278   if (regno + nregs <= info->regno)
2279     return;
2280   new_mask = (2U << (nregs - 1)) - 1;
2281   if (regno < info->regno)
2282     new_mask >>= info->regno - regno;
2283   else
2284     new_mask <<= regno - info->regno;
2285   info->mask &= ~new_mask;
2286 }
2287
2288 /* Return true iff part of the return value is live during INSN, and
2289    it is likely spilled.  This can happen when more than one insn is needed
2290    to copy the return value, e.g. when we consider to combine into the
2291    second copy insn for a complex value.  */
2292
2293 static bool
2294 likely_spilled_retval_p (rtx_insn *insn)
2295 {
2296   rtx_insn *use = BB_END (this_basic_block);
2297   rtx reg;
2298   rtx_insn *p;
2299   unsigned regno, nregs;
2300   /* We assume here that no machine mode needs more than
2301      32 hard registers when the value overlaps with a register
2302      for which TARGET_FUNCTION_VALUE_REGNO_P is true.  */
2303   unsigned mask;
2304   struct likely_spilled_retval_info info;
2305
2306   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2307     return false;
2308   reg = XEXP (PATTERN (use), 0);
2309   if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2310     return false;
2311   regno = REGNO (reg);
2312   nregs = REG_NREGS (reg);
2313   if (nregs == 1)
2314     return false;
2315   mask = (2U << (nregs - 1)) - 1;
2316
2317   /* Disregard parts of the return value that are set later.  */
2318   info.regno = regno;
2319   info.nregs = nregs;
2320   info.mask = mask;
2321   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2322     if (INSN_P (p))
2323       note_stores (p, likely_spilled_retval_1, &info);
2324   mask = info.mask;
2325
2326   /* Check if any of the (probably) live return value registers is
2327      likely spilled.  */
2328   nregs --;
2329   do
2330     {
2331       if ((mask & 1 << nregs)
2332           && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2333         return true;
2334     } while (nregs--);
2335   return false;
2336 }
2337
2338 /* Adjust INSN after we made a change to its destination.
2339
2340    Changing the destination can invalidate notes that say something about
2341    the results of the insn and a LOG_LINK pointing to the insn.  */
2342
2343 static void
2344 adjust_for_new_dest (rtx_insn *insn)
2345 {
2346   /* For notes, be conservative and simply remove them.  */
2347   remove_reg_equal_equiv_notes (insn, true);
2348
2349   /* The new insn will have a destination that was previously the destination
2350      of an insn just above it.  Call distribute_links to make a LOG_LINK from
2351      the next use of that destination.  */
2352
2353   rtx set = single_set (insn);
2354   gcc_assert (set);
2355
2356   rtx reg = SET_DEST (set);
2357
2358   while (GET_CODE (reg) == ZERO_EXTRACT
2359          || GET_CODE (reg) == STRICT_LOW_PART
2360          || GET_CODE (reg) == SUBREG)
2361     reg = XEXP (reg, 0);
2362   gcc_assert (REG_P (reg));
2363
2364   distribute_links (alloc_insn_link (insn, REGNO (reg), NULL));
2365
2366   df_insn_rescan (insn);
2367 }
2368
2369 /* Return TRUE if combine can reuse reg X in mode MODE.
2370    ADDED_SETS is trueif the original set is still required.  */
2371 static bool
2372 can_change_dest_mode (rtx x, bool added_sets, machine_mode mode)
2373 {
2374   unsigned int regno;
2375
2376   if (!REG_P (x))
2377     return false;
2378
2379   /* Don't change between modes with different underlying register sizes,
2380      since this could lead to invalid subregs.  */
2381   if (maybe_ne (REGMODE_NATURAL_SIZE (mode),
2382                 REGMODE_NATURAL_SIZE (GET_MODE (x))))
2383     return false;
2384
2385   regno = REGNO (x);
2386   /* Allow hard registers if the new mode is legal, and occupies no more
2387      registers than the old mode.  */
2388   if (regno < FIRST_PSEUDO_REGISTER)
2389     return (targetm.hard_regno_mode_ok (regno, mode)
2390             && REG_NREGS (x) >= hard_regno_nregs (regno, mode));
2391
2392   /* Or a pseudo that is only used once.  */
2393   return (regno < reg_n_sets_max
2394           && REG_N_SETS (regno) == 1
2395           && !added_sets
2396           && !REG_USERVAR_P (x));
2397 }
2398
2399
2400 /* Check whether X, the destination of a set, refers to part of
2401    the register specified by REG.  */
2402
2403 static bool
2404 reg_subword_p (rtx x, rtx reg)
2405 {
2406   /* Check that reg is an integer mode register.  */
2407   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2408     return false;
2409
2410   if (GET_CODE (x) == STRICT_LOW_PART
2411       || GET_CODE (x) == ZERO_EXTRACT)
2412     x = XEXP (x, 0);
2413
2414   return GET_CODE (x) == SUBREG
2415          && !paradoxical_subreg_p (x)
2416          && SUBREG_REG (x) == reg
2417          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2418 }
2419
2420 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2421    by an arbitrary number of CLOBBERs.  */
2422 static bool
2423 is_parallel_of_n_reg_sets (rtx pat, int n)
2424 {
2425   if (GET_CODE (pat) != PARALLEL)
2426     return false;
2427
2428   int len = XVECLEN (pat, 0);
2429   if (len < n)
2430     return false;
2431
2432   int i;
2433   for (i = 0; i < n; i++)
2434     if (GET_CODE (XVECEXP (pat, 0, i)) != SET
2435         || !REG_P (SET_DEST (XVECEXP (pat, 0, i))))
2436       return false;
2437   for ( ; i < len; i++)
2438     switch (GET_CODE (XVECEXP (pat, 0, i)))
2439       {
2440       case CLOBBER:
2441         if (XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
2442           return false;
2443         break;
2444       default:
2445         return false;
2446       }
2447   return true;
2448 }
2449
2450 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2451    CLOBBERs), can be split into individual SETs in that order, without
2452    changing semantics.  */
2453 static bool
2454 can_split_parallel_of_n_reg_sets (rtx_insn *insn, int n)
2455 {
2456   if (!insn_nothrow_p (insn))
2457     return false;
2458
2459   rtx pat = PATTERN (insn);
2460
2461   int i, j;
2462   for (i = 0; i < n; i++)
2463     {
2464       if (side_effects_p (SET_SRC (XVECEXP (pat, 0, i))))
2465         return false;
2466
2467       rtx reg = SET_DEST (XVECEXP (pat, 0, i));
2468
2469       for (j = i + 1; j < n; j++)
2470         if (reg_referenced_p (reg, XVECEXP (pat, 0, j)))
2471           return false;
2472     }
2473
2474   return true;
2475 }
2476
2477 /* Return whether X is just a single_set, with the source
2478    a general_operand.  */
2479 static bool
2480 is_just_move (rtx_insn *x)
2481 {
2482   rtx set = single_set (x);
2483   if (!set)
2484     return false;
2485
2486   return general_operand (SET_SRC (set), VOIDmode);
2487 }
2488
2489 /* Callback function to count autoincs.  */
2490
2491 static int
2492 count_auto_inc (rtx, rtx, rtx, rtx, rtx, void *arg)
2493 {
2494   (*((int *) arg))++;
2495
2496   return 0;
2497 }
2498
2499 /* Try to combine the insns I0, I1 and I2 into I3.
2500    Here I0, I1 and I2 appear earlier than I3.
2501    I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2502    I3.
2503
2504    If we are combining more than two insns and the resulting insn is not
2505    recognized, try splitting it into two insns.  If that happens, I2 and I3
2506    are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2507    Otherwise, I0, I1 and I2 are pseudo-deleted.
2508
2509    Return 0 if the combination does not work.  Then nothing is changed.
2510    If we did the combination, return the insn at which combine should
2511    resume scanning.
2512
2513    Set NEW_DIRECT_JUMP_P to true if try_combine creates a
2514    new direct jump instruction.
2515
2516    LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2517    been I3 passed to an earlier try_combine within the same basic
2518    block.  */
2519
2520 static rtx_insn *
2521 try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
2522              bool *new_direct_jump_p, rtx_insn *last_combined_insn)
2523 {
2524   /* New patterns for I3 and I2, respectively.  */
2525   rtx newpat, newi2pat = 0;
2526   rtvec newpat_vec_with_clobbers = 0;
2527   bool substed_i2 = false, substed_i1 = false, substed_i0 = false;
2528   /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2529      dead.  */
2530   bool added_sets_0, added_sets_1, added_sets_2;
2531   /* Total number of SETs to put into I3.  */
2532   int total_sets;
2533   /* Nonzero if I2's or I1's body now appears in I3.  */
2534   int i2_is_used = 0, i1_is_used = 0;
2535   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
2536   int insn_code_number, i2_code_number = 0, other_code_number = 0;
2537   /* Contains I3 if the destination of I3 is used in its source, which means
2538      that the old life of I3 is being killed.  If that usage is placed into
2539      I2 and not in I3, a REG_DEAD note must be made.  */
2540   rtx i3dest_killed = 0;
2541   /* SET_DEST and SET_SRC of I2, I1 and I0.  */
2542   rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2543   /* Copy of SET_SRC of I1 and I0, if needed.  */
2544   rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2545   /* Set if I2DEST was reused as a scratch register.  */
2546   bool i2scratch = false;
2547   /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases.  */
2548   rtx i0pat = 0, i1pat = 0, i2pat = 0;
2549   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
2550   bool i2dest_in_i2src = false, i1dest_in_i1src = false;
2551   bool i2dest_in_i1src = false, i0dest_in_i0src = false;
2552   bool i1dest_in_i0src = false, i2dest_in_i0src = false;;
2553   bool i2dest_killed = false, i1dest_killed = false, i0dest_killed = false;
2554   bool i1_feeds_i2_n = false, i0_feeds_i2_n = false, i0_feeds_i1_n = false;
2555   /* Notes that must be added to REG_NOTES in I3 and I2.  */
2556   rtx new_i3_notes, new_i2_notes;
2557   /* Notes that we substituted I3 into I2 instead of the normal case.  */
2558   bool i3_subst_into_i2 = false;
2559   /* Notes that I1, I2 or I3 is a MULT operation.  */
2560   bool have_mult = false;
2561   bool swap_i2i3 = false;
2562   bool split_i2i3 = false;
2563   bool changed_i3_dest = false;
2564   bool i2_was_move = false, i3_was_move = false;
2565   int n_auto_inc = 0;
2566
2567   int maxreg;
2568   rtx_insn *temp_insn;
2569   rtx temp_expr;
2570   struct insn_link *link;
2571   rtx other_pat = 0;
2572   rtx new_other_notes;
2573   int i;
2574   scalar_int_mode dest_mode, temp_mode;
2575   bool has_non_call_exception = false;
2576
2577   /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2578      never be).  */
2579   if (i1 == i2 || i0 == i2 || (i0 && i0 == i1))
2580     return 0;
2581
2582   /* Only try four-insn combinations when there's high likelihood of
2583      success.  Look for simple insns, such as loads of constants or
2584      binary operations involving a constant.  */
2585   if (i0)
2586     {
2587       int i;
2588       int ngood = 0;
2589       int nshift = 0;
2590       rtx set0, set3;
2591
2592       if (!flag_expensive_optimizations)
2593         return 0;
2594
2595       for (i = 0; i < 4; i++)
2596         {
2597           rtx_insn *insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2598           rtx set = single_set (insn);
2599           rtx src;
2600           if (!set)
2601             continue;
2602           src = SET_SRC (set);
2603           if (CONSTANT_P (src))
2604             {
2605               ngood += 2;
2606               break;
2607             }
2608           else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2609             ngood++;
2610           else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2611                    || GET_CODE (src) == LSHIFTRT)
2612             nshift++;
2613         }
2614
2615       /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2616          are likely manipulating its value.  Ideally we'll be able to combine
2617          all four insns into a bitfield insertion of some kind.
2618
2619          Note the source in I0 might be inside a sign/zero extension and the
2620          memory modes in I0 and I3 might be different.  So extract the address
2621          from the destination of I3 and search for it in the source of I0.
2622
2623          In the event that there's a match but the source/dest do not actually
2624          refer to the same memory, the worst that happens is we try some
2625          combinations that we wouldn't have otherwise.  */
2626       if ((set0 = single_set (i0))
2627           /* Ensure the source of SET0 is a MEM, possibly buried inside
2628              an extension.  */
2629           && (GET_CODE (SET_SRC (set0)) == MEM
2630               || ((GET_CODE (SET_SRC (set0)) == ZERO_EXTEND
2631                    || GET_CODE (SET_SRC (set0)) == SIGN_EXTEND)
2632                   && GET_CODE (XEXP (SET_SRC (set0), 0)) == MEM))
2633           && (set3 = single_set (i3))
2634           /* Ensure the destination of SET3 is a MEM.  */
2635           && GET_CODE (SET_DEST (set3)) == MEM
2636           /* Would it be better to extract the base address for the MEM
2637              in SET3 and look for that?  I don't have cases where it matters
2638              but I could envision such cases.  */
2639           && rtx_referenced_p (XEXP (SET_DEST (set3), 0), SET_SRC (set0)))
2640         ngood += 2;
2641
2642       if (ngood < 2 && nshift < 2)
2643         return 0;
2644     }
2645
2646   /* Exit early if one of the insns involved can't be used for
2647      combinations.  */
2648   if (CALL_P (i2)
2649       || (i1 && CALL_P (i1))
2650       || (i0 && CALL_P (i0))
2651       || cant_combine_insn_p (i3)
2652       || cant_combine_insn_p (i2)
2653       || (i1 && cant_combine_insn_p (i1))
2654       || (i0 && cant_combine_insn_p (i0))
2655       || likely_spilled_retval_p (i3))
2656     return 0;
2657
2658   combine_attempts++;
2659   undobuf.other_insn = 0;
2660
2661   /* Reset the hard register usage information.  */
2662   CLEAR_HARD_REG_SET (newpat_used_regs);
2663
2664   if (dump_file && (dump_flags & TDF_DETAILS))
2665     {
2666       if (i0)
2667         fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2668                  INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2669       else if (i1)
2670         fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2671                  INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2672       else
2673         fprintf (dump_file, "\nTrying %d -> %d:\n",
2674                  INSN_UID (i2), INSN_UID (i3));
2675
2676       if (i0)
2677         dump_insn_slim (dump_file, i0);
2678       if (i1)
2679         dump_insn_slim (dump_file, i1);
2680       dump_insn_slim (dump_file, i2);
2681       dump_insn_slim (dump_file, i3);
2682     }
2683
2684   /* If multiple insns feed into one of I2 or I3, they can be in any
2685      order.  To simplify the code below, reorder them in sequence.  */
2686   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2687     std::swap (i0, i2);
2688   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2689     std::swap (i0, i1);
2690   if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2691     std::swap (i1, i2);
2692
2693   added_links_insn = 0;
2694   added_notes_insn = 0;
2695
2696   /* First check for one important special case that the code below will
2697      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
2698      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
2699      we may be able to replace that destination with the destination of I3.
2700      This occurs in the common code where we compute both a quotient and
2701      remainder into a structure, in which case we want to do the computation
2702      directly into the structure to avoid register-register copies.
2703
2704      Note that this case handles both multiple sets in I2 and also cases
2705      where I2 has a number of CLOBBERs inside the PARALLEL.
2706
2707      We make very conservative checks below and only try to handle the
2708      most common cases of this.  For example, we only handle the case
2709      where I2 and I3 are adjacent to avoid making difficult register
2710      usage tests.  */
2711
2712   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2713       && REG_P (SET_SRC (PATTERN (i3)))
2714       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2715       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2716       && GET_CODE (PATTERN (i2)) == PARALLEL
2717       && ! side_effects_p (SET_DEST (PATTERN (i3)))
2718       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2719          below would need to check what is inside (and reg_overlap_mentioned_p
2720          doesn't support those codes anyway).  Don't allow those destinations;
2721          the resulting insn isn't likely to be recognized anyway.  */
2722       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2723       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2724       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2725                                     SET_DEST (PATTERN (i3)))
2726       && next_active_insn (i2) == i3)
2727     {
2728       rtx p2 = PATTERN (i2);
2729
2730       /* Make sure that the destination of I3,
2731          which we are going to substitute into one output of I2,
2732          is not used within another output of I2.  We must avoid making this:
2733          (parallel [(set (mem (reg 69)) ...)
2734                     (set (reg 69) ...)])
2735          which is not well-defined as to order of actions.
2736          (Besides, reload can't handle output reloads for this.)
2737
2738          The problem can also happen if the dest of I3 is a memory ref,
2739          if another dest in I2 is an indirect memory ref.
2740
2741          Neither can this PARALLEL be an asm.  We do not allow combining
2742          that usually (see can_combine_p), so do not here either.  */
2743       bool ok = true;
2744       for (i = 0; ok && i < XVECLEN (p2, 0); i++)
2745         {
2746           if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2747                || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2748               && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2749                                           SET_DEST (XVECEXP (p2, 0, i))))
2750             ok = false;
2751           else if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2752                    && GET_CODE (SET_SRC (XVECEXP (p2, 0, i))) == ASM_OPERANDS)
2753             ok = false;
2754         }
2755
2756       if (ok)
2757         for (i = 0; i < XVECLEN (p2, 0); i++)
2758           if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2759               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2760             {
2761               combine_merges++;
2762
2763               subst_insn = i3;
2764               subst_low_luid = DF_INSN_LUID (i2);
2765
2766               added_sets_2 = added_sets_1 = added_sets_0 = false;
2767               i2src = SET_SRC (XVECEXP (p2, 0, i));
2768               i2dest = SET_DEST (XVECEXP (p2, 0, i));
2769               i2dest_killed = dead_or_set_p (i2, i2dest);
2770
2771               /* Replace the dest in I2 with our dest and make the resulting
2772                  insn the new pattern for I3.  Then skip to where we validate
2773                  the pattern.  Everything was set up above.  */
2774               SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2775               newpat = p2;
2776               i3_subst_into_i2 = true;
2777               goto validate_replacement;
2778             }
2779     }
2780
2781   /* If I2 is setting a pseudo to a constant and I3 is setting some
2782      sub-part of it to another constant, merge them by making a new
2783      constant.  */
2784   if (i1 == 0
2785       && (temp_expr = single_set (i2)) != 0
2786       && is_a <scalar_int_mode> (GET_MODE (SET_DEST (temp_expr)), &temp_mode)
2787       && CONST_SCALAR_INT_P (SET_SRC (temp_expr))
2788       && GET_CODE (PATTERN (i3)) == SET
2789       && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3)))
2790       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp_expr)))
2791     {
2792       rtx dest = SET_DEST (PATTERN (i3));
2793       rtx temp_dest = SET_DEST (temp_expr);
2794       int offset = -1;
2795       int width = 0;
2796
2797       if (GET_CODE (dest) == ZERO_EXTRACT)
2798         {
2799           if (CONST_INT_P (XEXP (dest, 1))
2800               && CONST_INT_P (XEXP (dest, 2))
2801               && is_a <scalar_int_mode> (GET_MODE (XEXP (dest, 0)),
2802                                          &dest_mode))
2803             {
2804               width = INTVAL (XEXP (dest, 1));
2805               offset = INTVAL (XEXP (dest, 2));
2806               dest = XEXP (dest, 0);
2807               if (BITS_BIG_ENDIAN)
2808                 offset = GET_MODE_PRECISION (dest_mode) - width - offset;
2809             }
2810         }
2811       else
2812         {
2813           if (GET_CODE (dest) == STRICT_LOW_PART)
2814             dest = XEXP (dest, 0);
2815           if (is_a <scalar_int_mode> (GET_MODE (dest), &dest_mode))
2816             {
2817               width = GET_MODE_PRECISION (dest_mode);
2818               offset = 0;
2819             }
2820         }
2821
2822       if (offset >= 0)
2823         {
2824           /* If this is the low part, we're done.  */
2825           if (subreg_lowpart_p (dest))
2826             ;
2827           /* Handle the case where inner is twice the size of outer.  */
2828           else if (GET_MODE_PRECISION (temp_mode)
2829                    == 2 * GET_MODE_PRECISION (dest_mode))
2830             offset += GET_MODE_PRECISION (dest_mode);
2831           /* Otherwise give up for now.  */
2832           else
2833             offset = -1;
2834         }
2835
2836       if (offset >= 0)
2837         {
2838           rtx inner = SET_SRC (PATTERN (i3));
2839           rtx outer = SET_SRC (temp_expr);
2840
2841           wide_int o = wi::insert (rtx_mode_t (outer, temp_mode),
2842                                    rtx_mode_t (inner, dest_mode),
2843                                    offset, width);
2844
2845           combine_merges++;
2846           subst_insn = i3;
2847           subst_low_luid = DF_INSN_LUID (i2);
2848           added_sets_2 = added_sets_1 = added_sets_0 = false;
2849           i2dest = temp_dest;
2850           i2dest_killed = dead_or_set_p (i2, i2dest);
2851
2852           /* Replace the source in I2 with the new constant and make the
2853              resulting insn the new pattern for I3.  Then skip to where we
2854              validate the pattern.  Everything was set up above.  */
2855           SUBST (SET_SRC (temp_expr),
2856                  immed_wide_int_const (o, temp_mode));
2857
2858           newpat = PATTERN (i2);
2859
2860           /* The dest of I3 has been replaced with the dest of I2.  */
2861           changed_i3_dest = true;
2862           goto validate_replacement;
2863         }
2864     }
2865
2866   /* If we have no I1 and I2 looks like:
2867         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2868                    (set Y OP)])
2869      make up a dummy I1 that is
2870         (set Y OP)
2871      and change I2 to be
2872         (set (reg:CC X) (compare:CC Y (const_int 0)))
2873
2874      (We can ignore any trailing CLOBBERs.)
2875
2876      This undoes a previous combination and allows us to match a branch-and-
2877      decrement insn.  */
2878
2879   if (i1 == 0
2880       && is_parallel_of_n_reg_sets (PATTERN (i2), 2)
2881       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2882           == MODE_CC)
2883       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2884       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2885       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2886                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))
2887       && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2888       && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3))
2889     {
2890       /* We make I1 with the same INSN_UID as I2.  This gives it
2891          the same DF_INSN_LUID for value tracking.  Our fake I1 will
2892          never appear in the insn stream so giving it the same INSN_UID
2893          as I2 will not cause a problem.  */
2894
2895       i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2),
2896                          XVECEXP (PATTERN (i2), 0, 1), INSN_LOCATION (i2),
2897                          -1, NULL_RTX);
2898       INSN_UID (i1) = INSN_UID (i2);
2899
2900       SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2901       SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2902              SET_DEST (PATTERN (i1)));
2903       unsigned int regno = REGNO (SET_DEST (PATTERN (i1)));
2904       SUBST_LINK (LOG_LINKS (i2),
2905                   alloc_insn_link (i1, regno, LOG_LINKS (i2)));
2906     }
2907
2908   /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2909      make those two SETs separate I1 and I2 insns, and make an I0 that is
2910      the original I1.  */
2911   if (i0 == 0
2912       && is_parallel_of_n_reg_sets (PATTERN (i2), 2)
2913       && can_split_parallel_of_n_reg_sets (i2, 2)
2914       && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2915       && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3)
2916       && !reg_set_between_p  (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2917       && !reg_set_between_p  (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3))
2918     {
2919       /* If there is no I1, there is no I0 either.  */
2920       i0 = i1;
2921
2922       /* We make I1 with the same INSN_UID as I2.  This gives it
2923          the same DF_INSN_LUID for value tracking.  Our fake I1 will
2924          never appear in the insn stream so giving it the same INSN_UID
2925          as I2 will not cause a problem.  */
2926
2927       i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2),
2928                          XVECEXP (PATTERN (i2), 0, 0), INSN_LOCATION (i2),
2929                          -1, NULL_RTX);
2930       INSN_UID (i1) = INSN_UID (i2);
2931
2932       SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 1));
2933     }
2934
2935   /* Verify that I2 and maybe I1 and I0 can be combined into I3.  */
2936   if (!can_combine_p (i2, i3, i0, i1, NULL, NULL, &i2dest, &i2src))
2937     {
2938       if (dump_file && (dump_flags & TDF_DETAILS))
2939         fprintf (dump_file, "Can't combine i2 into i3\n");
2940       undo_all ();
2941       return 0;
2942     }
2943   if (i1 && !can_combine_p (i1, i3, i0, NULL, i2, NULL, &i1dest, &i1src))
2944     {
2945       if (dump_file && (dump_flags & TDF_DETAILS))
2946         fprintf (dump_file, "Can't combine i1 into i3\n");
2947       undo_all ();
2948       return 0;
2949     }
2950   if (i0 && !can_combine_p (i0, i3, NULL, NULL, i1, i2, &i0dest, &i0src))
2951     {
2952       if (dump_file && (dump_flags & TDF_DETAILS))
2953         fprintf (dump_file, "Can't combine i0 into i3\n");
2954       undo_all ();
2955       return 0;
2956     }
2957
2958   /* With non-call exceptions we can end up trying to combine multiple
2959      insns with possible EH side effects.  Make sure we can combine
2960      that to a single insn which means there must be at most one insn
2961      in the combination with an EH side effect.  */
2962   if (cfun->can_throw_non_call_exceptions)
2963     {
2964       if (find_reg_note (i3, REG_EH_REGION, NULL_RTX)
2965           || find_reg_note (i2, REG_EH_REGION, NULL_RTX)
2966           || (i1 && find_reg_note (i1, REG_EH_REGION, NULL_RTX))
2967           || (i0 && find_reg_note (i0, REG_EH_REGION, NULL_RTX)))
2968         {
2969           has_non_call_exception = true;
2970           if (insn_could_throw_p (i3)
2971               + insn_could_throw_p (i2)
2972               + (i1 ? insn_could_throw_p (i1) : 0)
2973               + (i0 ? insn_could_throw_p (i0) : 0) > 1)
2974             {
2975               if (dump_file && (dump_flags & TDF_DETAILS))
2976                 fprintf (dump_file, "Can't combine multiple insns with EH "
2977                          "side-effects\n");
2978               undo_all ();
2979               return 0;
2980             }
2981         }
2982     }
2983
2984   /* Record whether i2 and i3 are trivial moves.  */
2985   i2_was_move = is_just_move (i2);
2986   i3_was_move = is_just_move (i3);
2987
2988   /* Record whether I2DEST is used in I2SRC and similarly for the other
2989      cases.  Knowing this will help in register status updating below.  */
2990   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2991   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2992   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2993   i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2994   i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2995   i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2996   i2dest_killed = dead_or_set_p (i2, i2dest);
2997   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2998   i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2999
3000   /* For the earlier insns, determine which of the subsequent ones they
3001      feed.  */
3002   i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
3003   i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
3004   i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
3005                           : (!reg_overlap_mentioned_p (i1dest, i0dest)
3006                              && reg_overlap_mentioned_p (i0dest, i2src))));
3007
3008   /* Ensure that I3's pattern can be the destination of combines.  */
3009   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
3010                           i1 && i2dest_in_i1src && !i1_feeds_i2_n,
3011                           i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
3012                                  || (i1dest_in_i0src && !i0_feeds_i1_n)),
3013                           &i3dest_killed))
3014     {
3015       undo_all ();
3016       return 0;
3017     }
3018
3019   /* See if any of the insns is a MULT operation.  Unless one is, we will
3020      reject a combination that is, since it must be slower.  Be conservative
3021      here.  */
3022   if (GET_CODE (i2src) == MULT
3023       || (i1 != 0 && GET_CODE (i1src) == MULT)
3024       || (i0 != 0 && GET_CODE (i0src) == MULT)
3025       || (GET_CODE (PATTERN (i3)) == SET
3026           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
3027     have_mult = true;
3028
3029   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3030      We used to do this EXCEPT in one case: I3 has a post-inc in an
3031      output operand.  However, that exception can give rise to insns like
3032         mov r3,(r3)+
3033      which is a famous insn on the PDP-11 where the value of r3 used as the
3034      source was model-dependent.  Avoid this sort of thing.  */
3035
3036 #if 0
3037   if (!(GET_CODE (PATTERN (i3)) == SET
3038         && REG_P (SET_SRC (PATTERN (i3)))
3039         && MEM_P (SET_DEST (PATTERN (i3)))
3040         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
3041             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
3042     /* It's not the exception.  */
3043 #endif
3044     if (AUTO_INC_DEC)
3045       {
3046         rtx link;
3047         for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
3048           if (REG_NOTE_KIND (link) == REG_INC
3049               && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
3050                   || (i1 != 0
3051                       && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
3052             {
3053               undo_all ();
3054               return 0;
3055             }
3056       }
3057
3058   /* See if the SETs in I1 or I2 need to be kept around in the merged
3059      instruction: whenever the value set there is still needed past I3.
3060      For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3061
3062      For the SET in I1, we have two cases: if I1 and I2 independently feed
3063      into I3, the set in I1 needs to be kept around unless I1DEST dies
3064      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
3065      in I1 needs to be kept around unless I1DEST dies or is set in either
3066      I2 or I3.  The same considerations apply to I0.  */
3067
3068   added_sets_2 = !dead_or_set_p (i3, i2dest);
3069
3070   if (i1)
3071     added_sets_1 = !(dead_or_set_p (i3, i1dest)
3072                      || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
3073   else
3074     added_sets_1 = false;
3075
3076   if (i0)
3077     added_sets_0 =  !(dead_or_set_p (i3, i0dest)
3078                       || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))
3079                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3080                           && dead_or_set_p (i2, i0dest)));
3081   else
3082     added_sets_0 = false;
3083
3084   /* We are about to copy insns for the case where they need to be kept
3085      around.  Check that they can be copied in the merged instruction.  */
3086
3087   if (targetm.cannot_copy_insn_p
3088       && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
3089           || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
3090           || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
3091     {
3092       undo_all ();
3093       return 0;
3094     }
3095
3096   /* We cannot safely duplicate volatile references in any case.  */
3097
3098   if ((added_sets_2 && volatile_refs_p (PATTERN (i2)))
3099       || (added_sets_1 && volatile_refs_p (PATTERN (i1)))
3100       || (added_sets_0 && volatile_refs_p (PATTERN (i0))))
3101     {
3102       undo_all ();
3103       return 0;
3104     }
3105
3106   /* Count how many auto_inc expressions there were in the original insns;
3107      we need to have the same number in the resulting patterns.  */
3108
3109   if (i0)
3110     for_each_inc_dec (PATTERN (i0), count_auto_inc, &n_auto_inc);
3111   if (i1)
3112     for_each_inc_dec (PATTERN (i1), count_auto_inc, &n_auto_inc);
3113   for_each_inc_dec (PATTERN (i2), count_auto_inc, &n_auto_inc);
3114   for_each_inc_dec (PATTERN (i3), count_auto_inc, &n_auto_inc);
3115
3116   /* If the set in I2 needs to be kept around, we must make a copy of
3117      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3118      PATTERN (I2), we are only substituting for the original I1DEST, not into
3119      an already-substituted copy.  This also prevents making self-referential
3120      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3121      I2DEST.  */
3122
3123   if (added_sets_2)
3124     {
3125       if (GET_CODE (PATTERN (i2)) == PARALLEL)
3126         i2pat = gen_rtx_SET (i2dest, copy_rtx (i2src));
3127       else
3128         i2pat = copy_rtx (PATTERN (i2));
3129     }
3130
3131   if (added_sets_1)
3132     {
3133       if (GET_CODE (PATTERN (i1)) == PARALLEL)
3134         i1pat = gen_rtx_SET (i1dest, copy_rtx (i1src));
3135       else
3136         i1pat = copy_rtx (PATTERN (i1));
3137     }
3138
3139   if (added_sets_0)
3140     {
3141       if (GET_CODE (PATTERN (i0)) == PARALLEL)
3142         i0pat = gen_rtx_SET (i0dest, copy_rtx (i0src));
3143       else
3144         i0pat = copy_rtx (PATTERN (i0));
3145     }
3146
3147   combine_merges++;
3148
3149   /* Substitute in the latest insn for the regs set by the earlier ones.  */
3150
3151   maxreg = max_reg_num ();
3152
3153   subst_insn = i3;
3154
3155   /* Many machines have insns that can both perform an
3156      arithmetic operation and set the condition code.  These operations will
3157      be represented as a PARALLEL with the first element of the vector
3158      being a COMPARE of an arithmetic operation with the constant zero.
3159      The second element of the vector will set some pseudo to the result
3160      of the same arithmetic operation.  If we simplify the COMPARE, we won't
3161      match such a pattern and so will generate an extra insn.   Here we test
3162      for this case, where both the comparison and the operation result are
3163      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3164      I2SRC.  Later we will make the PARALLEL that contains I2.  */
3165
3166   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
3167       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
3168       && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
3169       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
3170     {
3171       rtx newpat_dest;
3172       rtx *cc_use_loc = NULL;
3173       rtx_insn *cc_use_insn = NULL;
3174       rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
3175       machine_mode compare_mode, orig_compare_mode;
3176       enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
3177       scalar_int_mode mode;
3178
3179       newpat = PATTERN (i3);
3180       newpat_dest = SET_DEST (newpat);
3181       compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
3182
3183       if (undobuf.other_insn == 0
3184           && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
3185                                             &cc_use_insn)))
3186         {
3187           compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
3188           if (is_a <scalar_int_mode> (GET_MODE (i2dest), &mode))
3189             compare_code = simplify_compare_const (compare_code, mode,
3190                                                    &op0, &op1);
3191           target_canonicalize_comparison (&compare_code, &op0, &op1, 1);
3192         }
3193
3194       /* Do the rest only if op1 is const0_rtx, which may be the
3195          result of simplification.  */
3196       if (op1 == const0_rtx)
3197         {
3198           /* If a single use of the CC is found, prepare to modify it
3199              when SELECT_CC_MODE returns a new CC-class mode, or when
3200              the above simplify_compare_const() returned a new comparison
3201              operator.  undobuf.other_insn is assigned the CC use insn
3202              when modifying it.  */
3203           if (cc_use_loc)
3204             {
3205 #ifdef SELECT_CC_MODE
3206               machine_mode new_mode
3207                 = SELECT_CC_MODE (compare_code, op0, op1);
3208               if (new_mode != orig_compare_mode
3209                   && can_change_dest_mode (SET_DEST (newpat),
3210                                            added_sets_2, new_mode))
3211                 {
3212                   unsigned int regno = REGNO (newpat_dest);
3213                   compare_mode = new_mode;
3214                   if (regno < FIRST_PSEUDO_REGISTER)
3215                     newpat_dest = gen_rtx_REG (compare_mode, regno);
3216                   else
3217                     {
3218                       subst_mode (regno, compare_mode);
3219                       newpat_dest = regno_reg_rtx[regno];
3220                     }
3221                 }
3222 #endif
3223               /* Cases for modifying the CC-using comparison.  */
3224               if (compare_code != orig_compare_code
3225                   && COMPARISON_P (*cc_use_loc))
3226                 {
3227                   /* Replace cc_use_loc with entire new RTX.  */
3228                   SUBST (*cc_use_loc,
3229                          gen_rtx_fmt_ee (compare_code, GET_MODE (*cc_use_loc),
3230                                          newpat_dest, const0_rtx));
3231                   undobuf.other_insn = cc_use_insn;
3232                 }
3233               else if (compare_mode != orig_compare_mode)
3234                 {
3235                   subrtx_ptr_iterator::array_type array;
3236
3237                   /* Just replace the CC reg with a new mode.  */
3238                   FOR_EACH_SUBRTX_PTR (iter, array, cc_use_loc, NONCONST)
3239                     {
3240                       rtx *loc = *iter;
3241                       if (REG_P (*loc)
3242                           && REGNO (*loc) == REGNO (newpat_dest))
3243                         {
3244                           SUBST (*loc, newpat_dest);
3245                           iter.skip_subrtxes ();
3246                         }
3247                     }
3248                   undobuf.other_insn = cc_use_insn;
3249                 }
3250             }
3251
3252           /* Now we modify the current newpat:
3253              First, SET_DEST(newpat) is updated if the CC mode has been
3254              altered. For targets without SELECT_CC_MODE, this should be
3255              optimized away.  */
3256           if (compare_mode != orig_compare_mode)
3257             SUBST (SET_DEST (newpat), newpat_dest);
3258           /* This is always done to propagate i2src into newpat.  */
3259           SUBST (SET_SRC (newpat),
3260                  gen_rtx_COMPARE (compare_mode, op0, op1));
3261           /* Create new version of i2pat if needed; the below PARALLEL
3262              creation needs this to work correctly.  */
3263           if (! rtx_equal_p (i2src, op0))
3264             i2pat = gen_rtx_SET (i2dest, op0);
3265           i2_is_used = 1;
3266         }
3267     }
3268
3269   if (i2_is_used == 0)
3270     {
3271       /* It is possible that the source of I2 or I1 may be performing
3272          an unneeded operation, such as a ZERO_EXTEND of something
3273          that is known to have the high part zero.  Handle that case
3274          by letting subst look at the inner insns.
3275
3276          Another way to do this would be to have a function that tries
3277          to simplify a single insn instead of merging two or more
3278          insns.  We don't do this because of the potential of infinite
3279          loops and because of the potential extra memory required.
3280          However, doing it the way we are is a bit of a kludge and
3281          doesn't catch all cases.
3282
3283          But only do this if -fexpensive-optimizations since it slows
3284          things down and doesn't usually win.
3285
3286          This is not done in the COMPARE case above because the
3287          unmodified I2PAT is used in the PARALLEL and so a pattern
3288          with a modified I2SRC would not match.  */
3289
3290       if (flag_expensive_optimizations)
3291         {
3292           /* Pass pc_rtx so no substitutions are done, just
3293              simplifications.  */
3294           if (i1)
3295             {
3296               subst_low_luid = DF_INSN_LUID (i1);
3297               i1src = subst (i1src, pc_rtx, pc_rtx, false, false, false);
3298             }
3299
3300           subst_low_luid = DF_INSN_LUID (i2);
3301           i2src = subst (i2src, pc_rtx, pc_rtx, false, false, false);
3302         }
3303
3304       n_occurrences = 0;                /* `subst' counts here */
3305       subst_low_luid = DF_INSN_LUID (i2);
3306
3307       /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3308          copy of I2SRC each time we substitute it, in order to avoid creating
3309          self-referential RTL when we will be substituting I1SRC for I1DEST
3310          later.  Likewise if I0 feeds into I2, either directly or indirectly
3311          through I1, and I0DEST is in I0SRC.  */
3312       newpat = subst (PATTERN (i3), i2dest, i2src, false, false,
3313                       (i1_feeds_i2_n && i1dest_in_i1src)
3314                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3315                           && i0dest_in_i0src));
3316       substed_i2 = true;
3317
3318       /* Record whether I2's body now appears within I3's body.  */
3319       i2_is_used = n_occurrences;
3320     }
3321
3322   /* If we already got a failure, don't try to do more.  Otherwise, try to
3323      substitute I1 if we have it.  */
3324
3325   if (i1 && GET_CODE (newpat) != CLOBBER)
3326     {
3327       /* Before we can do this substitution, we must redo the test done
3328          above (see detailed comments there) that ensures I1DEST isn't
3329          mentioned in any SETs in NEWPAT that are field assignments.  */
3330       if (!combinable_i3pat (NULL, &newpat, i1dest, NULL_RTX, NULL_RTX,
3331                              false, false, 0))
3332         {
3333           undo_all ();
3334           return 0;
3335         }
3336
3337       n_occurrences = 0;
3338       subst_low_luid = DF_INSN_LUID (i1);
3339
3340       /* If the following substitution will modify I1SRC, make a copy of it
3341          for the case where it is substituted for I1DEST in I2PAT later.  */
3342       if (added_sets_2 && i1_feeds_i2_n)
3343         i1src_copy = copy_rtx (i1src);
3344
3345       /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3346          copy of I1SRC each time we substitute it, in order to avoid creating
3347          self-referential RTL when we will be substituting I0SRC for I0DEST
3348          later.  */
3349       newpat = subst (newpat, i1dest, i1src, false, false,
3350                       i0_feeds_i1_n && i0dest_in_i0src);
3351       substed_i1 = true;
3352
3353       /* Record whether I1's body now appears within I3's body.  */
3354       i1_is_used = n_occurrences;
3355     }
3356
3357   /* Likewise for I0 if we have it.  */
3358
3359   if (i0 && GET_CODE (newpat) != CLOBBER)
3360     {
3361       if (!combinable_i3pat (NULL, &newpat, i0dest, NULL_RTX, NULL_RTX,
3362                              false, false, 0))
3363         {
3364           undo_all ();
3365           return 0;
3366         }
3367
3368       /* If the following substitution will modify I0SRC, make a copy of it
3369          for the case where it is substituted for I0DEST in I1PAT later.  */
3370       if (added_sets_1 && i0_feeds_i1_n)
3371         i0src_copy = copy_rtx (i0src);
3372       /* And a copy for I0DEST in I2PAT substitution.  */
3373       if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3374                            || (i0_feeds_i2_n)))
3375         i0src_copy2 = copy_rtx (i0src);
3376
3377       n_occurrences = 0;
3378       subst_low_luid = DF_INSN_LUID (i0);
3379       newpat = subst (newpat, i0dest, i0src, false, false, false);
3380       substed_i0 = true;
3381     }
3382
3383   if (n_auto_inc)
3384     {
3385       int new_n_auto_inc = 0;
3386       for_each_inc_dec (newpat, count_auto_inc, &new_n_auto_inc);
3387
3388       if (n_auto_inc != new_n_auto_inc)
3389         {
3390           if (dump_file && (dump_flags & TDF_DETAILS))
3391             fprintf (dump_file, "Number of auto_inc expressions changed\n");
3392           undo_all ();
3393           return 0;
3394         }
3395     }
3396
3397   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
3398      to count all the ways that I2SRC and I1SRC can be used.  */
3399   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3400        && i2_is_used + added_sets_2 > 1)
3401       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3402           && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n) > 1))
3403       || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3404           && (n_occurrences + added_sets_0
3405               + (added_sets_1 && i0_feeds_i1_n)
3406               + (added_sets_2 && i0_feeds_i2_n) > 1))
3407       /* Fail if we tried to make a new register.  */
3408       || max_reg_num () != maxreg
3409       /* Fail if we couldn't do something and have a CLOBBER.  */
3410       || GET_CODE (newpat) == CLOBBER
3411       /* Fail if this new pattern is a MULT and we didn't have one before
3412          at the outer level.  */
3413       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3414           && ! have_mult))
3415     {
3416       undo_all ();
3417       return 0;
3418     }
3419
3420   /* If the actions of the earlier insns must be kept
3421      in addition to substituting them into the latest one,
3422      we must make a new PARALLEL for the latest insn
3423      to hold additional the SETs.  */
3424
3425   if (added_sets_0 || added_sets_1 || added_sets_2)
3426     {
3427       int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3428       combine_extras++;
3429
3430       if (GET_CODE (newpat) == PARALLEL)
3431         {
3432           rtvec old = XVEC (newpat, 0);
3433           total_sets = XVECLEN (newpat, 0) + extra_sets;
3434           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3435           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3436                   sizeof (old->elem[0]) * old->num_elem);
3437         }
3438       else
3439         {
3440           rtx old = newpat;
3441           total_sets = 1 + extra_sets;
3442           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3443           XVECEXP (newpat, 0, 0) = old;
3444         }
3445
3446       if (added_sets_0)
3447         XVECEXP (newpat, 0, --total_sets) = i0pat;
3448
3449       if (added_sets_1)
3450         {
3451           rtx t = i1pat;
3452           if (i0_feeds_i1_n)
3453             t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src,
3454                        false, false, false);
3455
3456           XVECEXP (newpat, 0, --total_sets) = t;
3457         }
3458       if (added_sets_2)
3459         {
3460           rtx t = i2pat;
3461           if (i1_feeds_i2_n)
3462             t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, false, false,
3463                        i0_feeds_i1_n && i0dest_in_i0src);
3464           if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3465             t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src,
3466                        false, false, false);
3467
3468           XVECEXP (newpat, 0, --total_sets) = t;
3469         }
3470     }
3471
3472  validate_replacement:
3473
3474   /* Note which hard regs this insn has as inputs.  */
3475   mark_used_regs_combine (newpat);
3476
3477   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
3478      consider splitting this pattern, we might need these clobbers.  */
3479   if (i1 && GET_CODE (newpat) == PARALLEL
3480       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3481     {
3482       int len = XVECLEN (newpat, 0);
3483
3484       newpat_vec_with_clobbers = rtvec_alloc (len);
3485       for (i = 0; i < len; i++)
3486         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3487     }
3488
3489   /* We have recognized nothing yet.  */
3490   insn_code_number = -1;
3491
3492   /* See if this is a PARALLEL of two SETs where one SET's destination is
3493      a register that is unused and this isn't marked as an instruction that
3494      might trap in an EH region.  In that case, we just need the other SET.
3495      We prefer this over the PARALLEL.
3496
3497      This can occur when simplifying a divmod insn.  We *must* test for this
3498      case here because the code below that splits two independent SETs doesn't
3499      handle this case correctly when it updates the register status.
3500
3501      It's pointless doing this if we originally had two sets, one from
3502      i3, and one from i2.  Combining then splitting the parallel results
3503      in the original i2 again plus an invalid insn (which we delete).
3504      The net effect is only to move instructions around, which makes
3505      debug info less accurate.
3506
3507      If the remaining SET came from I2 its destination should not be used
3508      between I2 and I3.  See PR82024.  */
3509
3510   if (!(added_sets_2 && i1 == 0)
3511       && is_parallel_of_n_reg_sets (newpat, 2)
3512       && asm_noperands (newpat) < 0)
3513     {
3514       rtx set0 = XVECEXP (newpat, 0, 0);
3515       rtx set1 = XVECEXP (newpat, 0, 1);
3516       rtx oldpat = newpat;
3517
3518       if (((REG_P (SET_DEST (set1))
3519             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3520            || (GET_CODE (SET_DEST (set1)) == SUBREG
3521                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3522           && insn_nothrow_p (i3)
3523           && !side_effects_p (SET_SRC (set1)))
3524         {
3525           newpat = set0;
3526           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3527         }
3528
3529       else if (((REG_P (SET_DEST (set0))
3530                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3531                 || (GET_CODE (SET_DEST (set0)) == SUBREG
3532                     && find_reg_note (i3, REG_UNUSED,
3533                                       SUBREG_REG (SET_DEST (set0)))))
3534                && insn_nothrow_p (i3)
3535                && !side_effects_p (SET_SRC (set0)))
3536         {
3537           rtx dest = SET_DEST (set1);
3538           if (GET_CODE (dest) == SUBREG)
3539             dest = SUBREG_REG (dest);
3540           if (!reg_used_between_p (dest, i2, i3))
3541             {
3542               newpat = set1;
3543               insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3544
3545               if (insn_code_number >= 0)
3546                 changed_i3_dest = true;
3547             }
3548         }
3549
3550       if (insn_code_number < 0)
3551         newpat = oldpat;
3552     }
3553
3554   /* Is the result of combination a valid instruction?  */
3555   if (insn_code_number < 0)
3556     insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3557
3558   /* If we were combining three insns and the result is a simple SET
3559      with no ASM_OPERANDS that wasn't recognized, try to split it into two
3560      insns.  There are two ways to do this.  It can be split using a
3561      machine-specific method (like when you have an addition of a large
3562      constant) or by combine in the function find_split_point.  */
3563
3564   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3565       && asm_noperands (newpat) < 0)
3566     {
3567       rtx parallel, *split;
3568       rtx_insn *m_split_insn;
3569
3570       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
3571          use I2DEST as a scratch register will help.  In the latter case,
3572          convert I2DEST to the mode of the source of NEWPAT if we can.  */
3573
3574       m_split_insn = combine_split_insns (newpat, i3);
3575
3576       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3577          inputs of NEWPAT.  */
3578
3579       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3580          possible to try that as a scratch reg.  This would require adding
3581          more code to make it work though.  */
3582
3583       if (m_split_insn == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3584         {
3585           machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3586
3587           /* ??? Reusing i2dest without resetting the reg_stat entry for it
3588              (temporarily, until we are committed to this instruction
3589              combination) does not work: for example, any call to nonzero_bits
3590              on the register (from a splitter in the MD file, for example)
3591              will get the old information, which is invalid.
3592
3593              Since nowadays we can create registers during combine just fine,
3594              we should just create a new one here, not reuse i2dest.  */
3595
3596           /* First try to split using the original register as a
3597              scratch register.  */
3598           parallel = gen_rtx_PARALLEL (VOIDmode,
3599                                        gen_rtvec (2, newpat,
3600                                                   gen_rtx_CLOBBER (VOIDmode,
3601                                                                    i2dest)));
3602           m_split_insn = combine_split_insns (parallel, i3);
3603
3604           /* If that didn't work, try changing the mode of I2DEST if
3605              we can.  */
3606           if (m_split_insn == 0
3607               && new_mode != GET_MODE (i2dest)
3608               && new_mode != VOIDmode
3609               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3610             {
3611               machine_mode old_mode = GET_MODE (i2dest);
3612               rtx ni2dest;
3613
3614               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3615                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3616               else
3617                 {
3618                   subst_mode (REGNO (i2dest), new_mode);
3619                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
3620                 }
3621
3622               parallel = (gen_rtx_PARALLEL
3623                           (VOIDmode,
3624                            gen_rtvec (2, newpat,
3625                                       gen_rtx_CLOBBER (VOIDmode,
3626                                                        ni2dest))));
3627               m_split_insn = combine_split_insns (parallel, i3);
3628
3629               if (m_split_insn == 0
3630                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3631                 {
3632                   struct undo *buf;
3633
3634                   adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3635                   buf = undobuf.undos;
3636                   undobuf.undos = buf->next;
3637                   buf->next = undobuf.frees;
3638                   undobuf.frees = buf;
3639                 }
3640             }
3641
3642           i2scratch = m_split_insn != 0;
3643         }
3644
3645       /* If recog_for_combine has discarded clobbers, try to use them
3646          again for the split.  */
3647       if (m_split_insn == 0 && newpat_vec_with_clobbers)
3648         {
3649           parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3650           m_split_insn = combine_split_insns (parallel, i3);
3651         }
3652
3653       if (m_split_insn && NEXT_INSN (m_split_insn) == NULL_RTX)
3654         {
3655           rtx m_split_pat = PATTERN (m_split_insn);
3656           insn_code_number = recog_for_combine (&m_split_pat, i3, &new_i3_notes);
3657           if (insn_code_number >= 0)
3658             newpat = m_split_pat;
3659         }
3660       else if (m_split_insn && NEXT_INSN (NEXT_INSN (m_split_insn)) == NULL_RTX
3661                && (next_nonnote_nondebug_insn (i2) == i3
3662                    || !modified_between_p (PATTERN (m_split_insn), i2, i3)))
3663         {
3664           rtx i2set, i3set;
3665           rtx newi3pat = PATTERN (NEXT_INSN (m_split_insn));
3666           newi2pat = PATTERN (m_split_insn);
3667
3668           i3set = single_set (NEXT_INSN (m_split_insn));
3669           i2set = single_set (m_split_insn);
3670
3671           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3672
3673           /* If I2 or I3 has multiple SETs, we won't know how to track
3674              register status, so don't use these insns.  If I2's destination
3675              is used between I2 and I3, we also can't use these insns.  */
3676
3677           if (i2_code_number >= 0 && i2set && i3set
3678               && (next_nonnote_nondebug_insn (i2) == i3
3679                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3680             insn_code_number = recog_for_combine (&newi3pat, i3,
3681                                                   &new_i3_notes);
3682           if (insn_code_number >= 0)
3683             newpat = newi3pat;
3684
3685           /* It is possible that both insns now set the destination of I3.
3686              If so, we must show an extra use of it.  */
3687
3688           if (insn_code_number >= 0)
3689             {
3690               rtx new_i3_dest = SET_DEST (i3set);
3691               rtx new_i2_dest = SET_DEST (i2set);
3692
3693               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3694                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3695                      || GET_CODE (new_i3_dest) == SUBREG)
3696                 new_i3_dest = XEXP (new_i3_dest, 0);
3697
3698               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3699                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3700                      || GET_CODE (new_i2_dest) == SUBREG)
3701                 new_i2_dest = XEXP (new_i2_dest, 0);
3702
3703               if (REG_P (new_i3_dest)
3704                   && REG_P (new_i2_dest)
3705                   && REGNO (new_i3_dest) == REGNO (new_i2_dest)
3706                   && REGNO (new_i2_dest) < reg_n_sets_max)
3707                 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3708             }
3709         }
3710
3711       /* If we can split it and use I2DEST, go ahead and see if that
3712          helps things be recognized.  Verify that none of the registers
3713          are set between I2 and I3.  */
3714       if (insn_code_number < 0
3715           && (split = find_split_point (&newpat, i3, false)) != 0
3716           /* We need I2DEST in the proper mode.  If it is a hard register
3717              or the only use of a pseudo, we can change its mode.
3718              Make sure we don't change a hard register to have a mode that
3719              isn't valid for it, or change the number of registers.  */
3720           && (GET_MODE (*split) == GET_MODE (i2dest)
3721               || GET_MODE (*split) == VOIDmode
3722               || can_change_dest_mode (i2dest, added_sets_2,
3723                                        GET_MODE (*split)))
3724           && (next_nonnote_nondebug_insn (i2) == i3
3725               || !modified_between_p (*split, i2, i3))
3726           /* We can't overwrite I2DEST if its value is still used by
3727              NEWPAT.  */
3728           && ! reg_referenced_p (i2dest, newpat)
3729           /* We should not split a possibly trapping part when we
3730              care about non-call EH and have REG_EH_REGION notes
3731              to distribute.  */
3732           && ! (cfun->can_throw_non_call_exceptions
3733                 && has_non_call_exception
3734                 && may_trap_p (*split)))
3735         {
3736           rtx newdest = i2dest;
3737           enum rtx_code split_code = GET_CODE (*split);
3738           machine_mode split_mode = GET_MODE (*split);
3739           bool subst_done = false;
3740           newi2pat = NULL_RTX;
3741
3742           i2scratch = true;
3743
3744           /* *SPLIT may be part of I2SRC, so make sure we have the
3745              original expression around for later debug processing.
3746              We should not need I2SRC any more in other cases.  */
3747           if (MAY_HAVE_DEBUG_BIND_INSNS)
3748             i2src = copy_rtx (i2src);
3749           else
3750             i2src = NULL;
3751
3752           /* Get NEWDEST as a register in the proper mode.  We have already
3753              validated that we can do this.  */
3754           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3755             {
3756               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3757                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3758               else
3759                 {
3760                   subst_mode (REGNO (i2dest), split_mode);
3761                   newdest = regno_reg_rtx[REGNO (i2dest)];
3762                 }
3763             }
3764
3765           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3766              an ASHIFT.  This can occur if it was inside a PLUS and hence
3767              appeared to be a memory address.  This is a kludge.  */
3768           if (split_code == MULT
3769               && CONST_INT_P (XEXP (*split, 1))
3770               && INTVAL (XEXP (*split, 1)) > 0
3771               && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3772             {
3773               rtx i_rtx = gen_int_shift_amount (split_mode, i);
3774               SUBST (*split, gen_rtx_ASHIFT (split_mode,
3775                                              XEXP (*split, 0), i_rtx));
3776               /* Update split_code because we may not have a multiply
3777                  anymore.  */
3778               split_code = GET_CODE (*split);
3779             }
3780
3781           /* Similarly for (plus (mult FOO (const_int pow2))).  */
3782           if (split_code == PLUS
3783               && GET_CODE (XEXP (*split, 0)) == MULT
3784               && CONST_INT_P (XEXP (XEXP (*split, 0), 1))
3785               && INTVAL (XEXP (XEXP (*split, 0), 1)) > 0
3786               && (i = exact_log2 (UINTVAL (XEXP (XEXP (*split, 0), 1)))) >= 0)
3787             {
3788               rtx nsplit = XEXP (*split, 0);
3789               rtx i_rtx = gen_int_shift_amount (GET_MODE (nsplit), i);
3790               SUBST (XEXP (*split, 0), gen_rtx_ASHIFT (GET_MODE (nsplit),
3791                                                        XEXP (nsplit, 0),
3792                                                        i_rtx));
3793               /* Update split_code because we may not have a multiply
3794                  anymore.  */
3795               split_code = GET_CODE (*split);
3796             }
3797
3798 #ifdef INSN_SCHEDULING
3799           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3800              be written as a ZERO_EXTEND.  */
3801           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3802             {
3803               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3804                  what it really is.  */
3805               if (load_extend_op (GET_MODE (SUBREG_REG (*split)))
3806                   == SIGN_EXTEND)
3807                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3808                                                     SUBREG_REG (*split)));
3809               else
3810                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3811                                                     SUBREG_REG (*split)));
3812             }
3813 #endif
3814
3815           /* Attempt to split binary operators using arithmetic identities.  */
3816           if (BINARY_P (SET_SRC (newpat))
3817               && split_mode == GET_MODE (SET_SRC (newpat))
3818               && ! side_effects_p (SET_SRC (newpat)))
3819             {
3820               rtx setsrc = SET_SRC (newpat);
3821               machine_mode mode = GET_MODE (setsrc);
3822               enum rtx_code code = GET_CODE (setsrc);
3823               rtx src_op0 = XEXP (setsrc, 0);
3824               rtx src_op1 = XEXP (setsrc, 1);
3825
3826               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
3827               if (rtx_equal_p (src_op0, src_op1))
3828                 {
3829                   newi2pat = gen_rtx_SET (newdest, src_op0);
3830                   SUBST (XEXP (setsrc, 0), newdest);
3831                   SUBST (XEXP (setsrc, 1), newdest);
3832                   subst_done = true;
3833                 }
3834               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
3835               else if ((code == PLUS || code == MULT)
3836                        && GET_CODE (src_op0) == code
3837                        && GET_CODE (XEXP (src_op0, 0)) == code
3838                        && (INTEGRAL_MODE_P (mode)
3839                            || (FLOAT_MODE_P (mode)
3840                                && flag_unsafe_math_optimizations)))
3841                 {
3842                   rtx p = XEXP (XEXP (src_op0, 0), 0);
3843                   rtx q = XEXP (XEXP (src_op0, 0), 1);
3844                   rtx r = XEXP (src_op0, 1);
3845                   rtx s = src_op1;
3846
3847                   /* Split both "((X op Y) op X) op Y" and
3848                      "((X op Y) op Y) op X" as "T op T" where T is
3849                      "X op Y".  */
3850                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3851                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3852                     {
3853                       newi2pat = gen_rtx_SET (newdest, XEXP (src_op0, 0));
3854                       SUBST (XEXP (setsrc, 0), newdest);
3855                       SUBST (XEXP (setsrc, 1), newdest);
3856                       subst_done = true;
3857                     }
3858                   /* Split "((X op X) op Y) op Y)" as "T op T" where
3859                      T is "X op Y".  */
3860                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3861                     {
3862                       rtx tmp = simplify_gen_binary (code, mode, p, r);
3863                       newi2pat = gen_rtx_SET (newdest, tmp);
3864                       SUBST (XEXP (setsrc, 0), newdest);
3865                       SUBST (XEXP (setsrc, 1), newdest);
3866                       subst_done = true;
3867                     }
3868                 }
3869             }
3870
3871           if (!subst_done)
3872             {
3873               newi2pat = gen_rtx_SET (newdest, *split);
3874               SUBST (*split, newdest);
3875             }
3876
3877           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3878
3879           /* recog_for_combine might have added CLOBBERs to newi2pat.
3880              Make sure NEWPAT does not depend on the clobbered regs.  */
3881           if (GET_CODE (newi2pat) == PARALLEL)
3882             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3883               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3884                 {
3885                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3886                   if (reg_overlap_mentioned_p (reg, newpat))
3887                     {
3888                       undo_all ();
3889                       return 0;
3890                     }
3891                 }
3892
3893           /* If the split point was a MULT and we didn't have one before,
3894              don't use one now.  */
3895           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3896             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3897         }
3898     }
3899
3900   /* Check for a case where we loaded from memory in a narrow mode and
3901      then sign extended it, but we need both registers.  In that case,
3902      we have a PARALLEL with both loads from the same memory location.
3903      We can split this into a load from memory followed by a register-register
3904      copy.  This saves at least one insn, more if register allocation can
3905      eliminate the copy.
3906
3907      We cannot do this if the involved modes have more than one elements,
3908      like for vector or complex modes.
3909
3910      We cannot do this if the destination of the first assignment is a
3911      condition code register.  We eliminate this case by making sure
3912      the SET_DEST and SET_SRC have the same mode.
3913
3914      We cannot do this if the destination of the second assignment is
3915      a register that we have already assumed is zero-extended.  Similarly
3916      for a SUBREG of such a register.  */
3917
3918   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3919            && GET_CODE (newpat) == PARALLEL
3920            && XVECLEN (newpat, 0) == 2
3921            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3922            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3923            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3924                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3925            && ! VECTOR_MODE_P (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0))))
3926            && ! COMPLEX_MODE_P (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0))))
3927            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3928            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3929                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3930            && !modified_between_p (SET_SRC (XVECEXP (newpat, 0, 1)), i2, i3)
3931            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3932            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3933            && ! (temp_expr = SET_DEST (XVECEXP (newpat, 0, 1)),
3934                  (REG_P (temp_expr)
3935                   && reg_stat[REGNO (temp_expr)].nonzero_bits != 0
3936                   && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3937                                BITS_PER_WORD)
3938                   && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3939                                HOST_BITS_PER_INT)
3940                   && (reg_stat[REGNO (temp_expr)].nonzero_bits
3941                       != GET_MODE_MASK (word_mode))))
3942            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3943                  && (temp_expr = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3944                      (REG_P (temp_expr)
3945                       && reg_stat[REGNO (temp_expr)].nonzero_bits != 0
3946                       && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3947                                    BITS_PER_WORD)
3948                       && known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3949                                    HOST_BITS_PER_INT)
3950                       && (reg_stat[REGNO (temp_expr)].nonzero_bits
3951                           != GET_MODE_MASK (word_mode)))))
3952            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3953                                          SET_SRC (XVECEXP (newpat, 0, 1)))
3954            && ! find_reg_note (i3, REG_UNUSED,
3955                                SET_DEST (XVECEXP (newpat, 0, 0))))
3956     {
3957       rtx ni2dest;
3958
3959       newi2pat = XVECEXP (newpat, 0, 0);
3960       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3961       newpat = XVECEXP (newpat, 0, 1);
3962       SUBST (SET_SRC (newpat),
3963              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3964       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3965
3966       if (i2_code_number >= 0)
3967         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3968
3969       if (insn_code_number >= 0)
3970         swap_i2i3 = 1;
3971     }
3972
3973   /* Similarly, check for a case where we have a PARALLEL of two independent
3974      SETs but we started with three insns.  In this case, we can do the sets
3975      as two separate insns.  This case occurs when some SET allows two
3976      other insns to combine, but the destination of that SET is still live.
3977
3978      Also do this if we started with two insns and (at least) one of the
3979      resulting sets is a noop; this noop will be deleted later.
3980
3981      Also do this if we started with two insns neither of which was a simple
3982      move.  */
3983
3984   else if (insn_code_number < 0 && asm_noperands (newpat) < 0
3985            && GET_CODE (newpat) == PARALLEL
3986            && XVECLEN (newpat, 0) == 2
3987            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3988            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3989            && (i1
3990                || set_noop_p (XVECEXP (newpat, 0, 0))
3991                || set_noop_p (XVECEXP (newpat, 0, 1))
3992                || (!i2_was_move && !i3_was_move))
3993            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3994            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3995            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3996            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3997            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3998                                   XVECEXP (newpat, 0, 0))
3999            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
4000                                   XVECEXP (newpat, 0, 1))
4001            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
4002                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
4003     {
4004       rtx set0 = XVECEXP (newpat, 0, 0);
4005       rtx set1 = XVECEXP (newpat, 0, 1);
4006
4007       /* Normally, it doesn't matter which of the two is done first, but
4008          one which uses any regs/memory set in between i2 and i3 can't
4009          be first.  The PARALLEL might also have been pre-existing in i3,
4010          so we need to make sure that we won't wrongly hoist a SET to i2
4011          that would conflict with a death note present in there, or would
4012          have its dest modified between i2 and i3.  */
4013       if (!modified_between_p (SET_SRC (set1), i2, i3)
4014           && !(REG_P (SET_DEST (set1))
4015                && find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
4016           && !(GET_CODE (SET_DEST (set1)) == SUBREG
4017                && find_reg_note (i2, REG_DEAD,
4018                                  SUBREG_REG (SET_DEST (set1))))
4019           && !modified_between_p (SET_DEST (set1), i2, i3)
4020           /* If I3 is a jump, ensure that set0 is a jump so that
4021              we do not create invalid RTL.  */
4022           && (!JUMP_P (i3) || SET_DEST (set0) == pc_rtx)
4023          )
4024         {
4025           newi2pat = set1;
4026           newpat = set0;
4027         }
4028       else if (!modified_between_p (SET_SRC (set0), i2, i3)
4029                && !(REG_P (SET_DEST (set0))
4030                     && find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
4031                && !(GET_CODE (SET_DEST (set0)) == SUBREG
4032                     && find_reg_note (i2, REG_DEAD,
4033                                       SUBREG_REG (SET_DEST (set0))))
4034                && !modified_between_p (SET_DEST (set0), i2, i3)
4035                /* If I3 is a jump, ensure that set1 is a jump so that
4036                   we do not create invalid RTL.  */
4037                && (!JUMP_P (i3) || SET_DEST (set1) == pc_rtx)
4038               )
4039         {
4040           newi2pat = set0;
4041           newpat = set1;
4042         }
4043       else
4044         {
4045           undo_all ();
4046           return 0;
4047         }
4048
4049       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
4050
4051       if (i2_code_number >= 0)
4052         {
4053           /* recog_for_combine might have added CLOBBERs to newi2pat.
4054              Make sure NEWPAT does not depend on the clobbered regs.  */
4055           if (GET_CODE (newi2pat) == PARALLEL)
4056             {
4057               for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
4058                 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
4059                   {
4060                     rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
4061                     if (reg_overlap_mentioned_p (reg, newpat))
4062                       {
4063                         undo_all ();
4064                         return 0;
4065                       }
4066                   }
4067             }
4068
4069           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
4070
4071           /* Likewise, recog_for_combine might have added clobbers to NEWPAT.
4072              Checking that the SET0's SET_DEST and SET1's SET_DEST aren't
4073              mentioned/clobbered, ensures NEWI2PAT's SET_DEST is live.  */
4074           if (insn_code_number >= 0 && GET_CODE (newpat) == PARALLEL)
4075             {
4076               for (i = XVECLEN (newpat, 0) - 1; i >= 0; i--)
4077                 if (GET_CODE (XVECEXP (newpat, 0, i)) == CLOBBER)
4078                   {
4079                     rtx reg = XEXP (XVECEXP (newpat, 0, i), 0);
4080                     if (reg_overlap_mentioned_p (reg, SET_DEST (set0))
4081                         || reg_overlap_mentioned_p (reg, SET_DEST (set1)))
4082                       {
4083                         undo_all ();
4084                         return 0;
4085                       }
4086                   }
4087             }
4088
4089           if (insn_code_number >= 0)
4090             split_i2i3 = true;
4091         }
4092     }
4093
4094   /* If it still isn't recognized, fail and change things back the way they
4095      were.  */
4096   if ((insn_code_number < 0
4097        /* Is the result a reasonable ASM_OPERANDS?  */
4098        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
4099     {
4100       undo_all ();
4101       return 0;
4102     }
4103
4104   /* If we had to change another insn, make sure it is valid also.  */
4105   if (undobuf.other_insn)
4106     {
4107       CLEAR_HARD_REG_SET (newpat_used_regs);
4108
4109       other_pat = PATTERN (undobuf.other_insn);
4110       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
4111                                              &new_other_notes);
4112
4113       if (other_code_number < 0 && ! check_asm_operands (other_pat))
4114         {
4115           undo_all ();
4116           return 0;
4117         }
4118     }
4119
4120   /* Only allow this combination if insn_cost reports that the
4121      replacement instructions are cheaper than the originals.  */
4122   if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
4123     {
4124       undo_all ();
4125       return 0;
4126     }
4127
4128   if (MAY_HAVE_DEBUG_BIND_INSNS)
4129     {
4130       struct undo *undo;
4131
4132       for (undo = undobuf.undos; undo; undo = undo->next)
4133         if (undo->kind == UNDO_MODE)
4134           {
4135             rtx reg = regno_reg_rtx[undo->where.regno];
4136             machine_mode new_mode = GET_MODE (reg);
4137             machine_mode old_mode = undo->old_contents.m;
4138
4139             /* Temporarily revert mode back.  */
4140             adjust_reg_mode (reg, old_mode);
4141
4142             if (reg == i2dest && i2scratch)
4143               {
4144                 /* If we used i2dest as a scratch register with a
4145                    different mode, substitute it for the original
4146                    i2src while its original mode is temporarily
4147                    restored, and then clear i2scratch so that we don't
4148                    do it again later.  */
4149                 propagate_for_debug (i2, last_combined_insn, reg, i2src,
4150                                      this_basic_block);
4151                 i2scratch = false;
4152                 /* Put back the new mode.  */
4153                 adjust_reg_mode (reg, new_mode);
4154               }
4155             else
4156               {
4157                 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
4158                 rtx_insn *first, *last;
4159
4160                 if (reg == i2dest)
4161                   {
4162                     first = i2;
4163                     last = last_combined_insn;
4164                   }
4165                 else
4166                   {
4167                     first = i3;
4168                     last = undobuf.other_insn;
4169                     gcc_assert (last);
4170                     if (DF_INSN_LUID (last)
4171                         < DF_INSN_LUID (last_combined_insn))
4172                       last = last_combined_insn;
4173                   }
4174
4175                 /* We're dealing with a reg that changed mode but not
4176                    meaning, so we want to turn it into a subreg for
4177                    the new mode.  However, because of REG sharing and
4178                    because its mode had already changed, we have to do
4179                    it in two steps.  First, replace any debug uses of
4180                    reg, with its original mode temporarily restored,
4181                    with this copy we have created; then, replace the
4182                    copy with the SUBREG of the original shared reg,
4183                    once again changed to the new mode.  */
4184                 propagate_for_debug (first, last, reg, tempreg,
4185                                      this_basic_block);
4186                 adjust_reg_mode (reg, new_mode);
4187                 propagate_for_debug (first, last, tempreg,
4188                                      lowpart_subreg (old_mode, reg, new_mode),
4189                                      this_basic_block);
4190               }
4191           }
4192     }
4193
4194   /* If we will be able to accept this, we have made a
4195      change to the destination of I3.  This requires us to
4196      do a few adjustments.  */
4197
4198   if (changed_i3_dest)
4199     {
4200       PATTERN (i3) = newpat;
4201       adjust_for_new_dest (i3);
4202     }
4203
4204   /* If I2 didn't change, this is not a combination (but a simplification or
4205      canonicalisation with context), which should not be done here.  Doing
4206      it here explodes the algorithm.  Don't.  */
4207   if (rtx_equal_p (newi2pat, PATTERN (i2)))
4208     {
4209       if (dump_file)
4210         fprintf (dump_file, "i2 didn't change, not doing this\n");
4211       undo_all ();
4212       return 0;
4213     }
4214
4215   /* We now know that we can do this combination.  Merge the insns and
4216      update the status of registers and LOG_LINKS.  */
4217
4218   if (undobuf.other_insn)
4219     {
4220       rtx note, next;
4221
4222       PATTERN (undobuf.other_insn) = other_pat;
4223
4224       /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4225          ensure that they are still valid.  Then add any non-duplicate
4226          notes added by recog_for_combine.  */
4227       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
4228         {
4229           next = XEXP (note, 1);
4230
4231           if ((REG_NOTE_KIND (note) == REG_DEAD
4232                && !reg_referenced_p (XEXP (note, 0),
4233                                      PATTERN (undobuf.other_insn)))
4234               ||(REG_NOTE_KIND (note) == REG_UNUSED
4235                  && !reg_set_p (XEXP (note, 0),
4236                                 PATTERN (undobuf.other_insn)))
4237               /* Simply drop equal note since it may be no longer valid
4238                  for other_insn.  It may be possible to record that CC
4239                  register is changed and only discard those notes, but
4240                  in practice it's unnecessary complication and doesn't
4241                  give any meaningful improvement.
4242
4243                  See PR78559.  */
4244               || REG_NOTE_KIND (note) == REG_EQUAL
4245               || REG_NOTE_KIND (note) == REG_EQUIV)
4246             remove_note (undobuf.other_insn, note);
4247         }
4248
4249       distribute_notes  (new_other_notes, undobuf.other_insn,
4250                         undobuf.other_insn, NULL, NULL_RTX, NULL_RTX,
4251                         NULL_RTX);
4252     }
4253
4254   if (swap_i2i3)
4255     {
4256       /* I3 now uses what used to be its destination and which is now
4257          I2's destination.  This requires us to do a few adjustments.  */
4258       PATTERN (i3) = newpat;
4259       adjust_for_new_dest (i3);
4260     }
4261
4262   if (swap_i2i3 || split_i2i3)
4263     {
4264       /* We might need a LOG_LINK from I3 to I2.  But then we used to
4265          have one, so we still will.
4266
4267          However, some later insn might be using I2's dest and have
4268          a LOG_LINK pointing at I3.  We should change it to point at
4269          I2 instead.  */
4270
4271       /* newi2pat is usually a SET here; however, recog_for_combine might
4272          have added some clobbers.  */
4273       rtx x = newi2pat;
4274       if (GET_CODE (x) == PARALLEL)
4275         x = XVECEXP (newi2pat, 0, 0);
4276
4277       if (REG_P (SET_DEST (x))
4278           || (GET_CODE (SET_DEST (x)) == SUBREG
4279               && REG_P (SUBREG_REG (SET_DEST (x)))))
4280         {
4281           unsigned int regno = reg_or_subregno (SET_DEST (x));
4282
4283           bool done = false;
4284           for (rtx_insn *insn = NEXT_INSN (i3);
4285                !done
4286                && insn
4287                && INSN_P (insn)
4288                && BLOCK_FOR_INSN (insn) == this_basic_block;
4289                insn = NEXT_INSN (insn))
4290             {
4291               if (DEBUG_INSN_P (insn))
4292                 continue;
4293               struct insn_link *link;
4294               FOR_EACH_LOG_LINK (link, insn)
4295                 if (link->insn == i3 && link->regno == regno)
4296                   {
4297                     link->insn = i2;
4298                     done = true;
4299                     break;
4300                   }
4301             }
4302         }
4303     }
4304
4305   {
4306     rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
4307     struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
4308     rtx midnotes = 0;
4309     int from_luid;
4310     /* Compute which registers we expect to eliminate.  newi2pat may be setting
4311        either i3dest or i2dest, so we must check it.  */
4312     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
4313                    || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4314                    || !i2dest_killed
4315                    ? 0 : i2dest);
4316     /* For i1, we need to compute both local elimination and global
4317        elimination information with respect to newi2pat because i1dest
4318        may be the same as i3dest, in which case newi2pat may be setting
4319        i1dest.  Global information is used when distributing REG_DEAD
4320        note for i2 and i3, in which case it does matter if newi2pat sets
4321        i1dest or not.
4322
4323        Local information is used when distributing REG_DEAD note for i1,
4324        in which case it doesn't matter if newi2pat sets i1dest or not.
4325        See PR62151, if we have four insns combination:
4326            i0: r0 <- i0src
4327            i1: r1 <- i1src (using r0)
4328                      REG_DEAD (r0)
4329            i2: r0 <- i2src (using r1)
4330            i3: r3 <- i3src (using r0)
4331            ix: using r0
4332        From i1's point of view, r0 is eliminated, no matter if it is set
4333        by newi2pat or not.  In other words, REG_DEAD info for r0 in i1
4334        should be discarded.
4335
4336        Note local information only affects cases in forms like "I1->I2->I3",
4337        "I0->I1->I2->I3" or "I0&I1->I2, I2->I3".  For other cases like
4338        "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4339        i0dest anyway.  */
4340     rtx local_elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4341                          || !i1dest_killed
4342                          ? 0 : i1dest);
4343     rtx elim_i1 = (local_elim_i1 == 0
4344                    || (newi2pat && reg_set_p (i1dest, newi2pat))
4345                    ? 0 : i1dest);
4346     /* Same case as i1.  */
4347     rtx local_elim_i0 = (i0 == 0 || i0dest_in_i0src || !i0dest_killed
4348                          ? 0 : i0dest);
4349     rtx elim_i0 = (local_elim_i0 == 0
4350                    || (newi2pat && reg_set_p (i0dest, newi2pat))
4351                    ? 0 : i0dest);
4352
4353     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4354        clear them.  */
4355     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4356     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4357     if (i1)
4358       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4359     if (i0)
4360       i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4361
4362     /* Ensure that we do not have something that should not be shared but
4363        occurs multiple times in the new insns.  Check this by first
4364        resetting all the `used' flags and then copying anything is shared.  */
4365
4366     reset_used_flags (i3notes);
4367     reset_used_flags (i2notes);
4368     reset_used_flags (i1notes);
4369     reset_used_flags (i0notes);
4370     reset_used_flags (newpat);
4371     reset_used_flags (newi2pat);
4372     if (undobuf.other_insn)
4373       reset_used_flags (PATTERN (undobuf.other_insn));
4374
4375     i3notes = copy_rtx_if_shared (i3notes);
4376     i2notes = copy_rtx_if_shared (i2notes);
4377     i1notes = copy_rtx_if_shared (i1notes);
4378     i0notes = copy_rtx_if_shared (i0notes);
4379     newpat = copy_rtx_if_shared (newpat);
4380     newi2pat = copy_rtx_if_shared (newi2pat);
4381     if (undobuf.other_insn)
4382       reset_used_flags (PATTERN (undobuf.other_insn));
4383
4384     INSN_CODE (i3) = insn_code_number;
4385     PATTERN (i3) = newpat;
4386
4387     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4388       {
4389         for (rtx link = CALL_INSN_FUNCTION_USAGE (i3); link;
4390              link = XEXP (link, 1))
4391           {
4392             if (substed_i2)
4393               {
4394                 /* I2SRC must still be meaningful at this point.  Some
4395                    splitting operations can invalidate I2SRC, but those
4396                    operations do not apply to calls.  */
4397                 gcc_assert (i2src);
4398                 XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4399                                                        i2dest, i2src);
4400               }
4401             if (substed_i1)
4402               XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4403                                                      i1dest, i1src);
4404             if (substed_i0)
4405               XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4406                                                      i0dest, i0src);
4407           }
4408       }
4409
4410     if (undobuf.other_insn)
4411       INSN_CODE (undobuf.other_insn) = other_code_number;
4412
4413     /* We had one special case above where I2 had more than one set and
4414        we replaced a destination of one of those sets with the destination
4415        of I3.  In that case, we have to update LOG_LINKS of insns later
4416        in this basic block.  Note that this (expensive) case is rare.
4417
4418        Also, in this case, we must pretend that all REG_NOTEs for I2
4419        actually came from I3, so that REG_UNUSED notes from I2 will be
4420        properly handled.  */
4421
4422     if (i3_subst_into_i2)
4423       {
4424         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4425           if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4426                || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4427               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4428               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4429               && ! find_reg_note (i2, REG_UNUSED,
4430                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4431             for (temp_insn = NEXT_INSN (i2);
4432                  temp_insn
4433                  && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
4434                      || BB_HEAD (this_basic_block) != temp_insn);
4435                  temp_insn = NEXT_INSN (temp_insn))
4436               if (temp_insn != i3 && NONDEBUG_INSN_P (temp_insn))
4437                 FOR_EACH_LOG_LINK (link, temp_insn)
4438                   if (link->insn == i2)
4439                     link->insn = i3;
4440
4441         if (i3notes)
4442           {
4443             rtx link = i3notes;
4444             while (XEXP (link, 1))
4445               link = XEXP (link, 1);
4446             XEXP (link, 1) = i2notes;
4447           }
4448         else
4449           i3notes = i2notes;
4450         i2notes = 0;
4451       }
4452
4453     LOG_LINKS (i3) = NULL;
4454     REG_NOTES (i3) = 0;
4455     LOG_LINKS (i2) = NULL;
4456     REG_NOTES (i2) = 0;
4457
4458     if (newi2pat)
4459       {
4460         if (MAY_HAVE_DEBUG_BIND_INSNS && i2scratch)
4461           propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4462                                this_basic_block);
4463         INSN_CODE (i2) = i2_code_number;
4464         PATTERN (i2) = newi2pat;
4465       }
4466     else
4467       {
4468         if (MAY_HAVE_DEBUG_BIND_INSNS && i2src)
4469           propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4470                                this_basic_block);
4471         SET_INSN_DELETED (i2);
4472       }
4473
4474     if (i1)
4475       {
4476         LOG_LINKS (i1) = NULL;
4477         REG_NOTES (i1) = 0;
4478         if (MAY_HAVE_DEBUG_BIND_INSNS)
4479           propagate_for_debug (i1, last_combined_insn, i1dest, i1src,
4480                                this_basic_block);
4481         SET_INSN_DELETED (i1);
4482       }
4483
4484     if (i0)
4485       {
4486         LOG_LINKS (i0) = NULL;
4487         REG_NOTES (i0) = 0;
4488         if (MAY_HAVE_DEBUG_BIND_INSNS)
4489           propagate_for_debug (i0, last_combined_insn, i0dest, i0src,
4490                                this_basic_block);
4491         SET_INSN_DELETED (i0);
4492       }
4493
4494     /* Get death notes for everything that is now used in either I3 or
4495        I2 and used to die in a previous insn.  If we built two new
4496        patterns, move from I1 to I2 then I2 to I3 so that we get the
4497        proper movement on registers that I2 modifies.  */
4498
4499     if (i0)
4500       from_luid = DF_INSN_LUID (i0);
4501     else if (i1)
4502       from_luid = DF_INSN_LUID (i1);
4503     else
4504       from_luid = DF_INSN_LUID (i2);
4505     if (newi2pat)
4506       move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4507     move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4508
4509     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
4510     if (i3notes)
4511       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL,
4512                         elim_i2, elim_i1, elim_i0);
4513     if (i2notes)
4514       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL,
4515                         elim_i2, elim_i1, elim_i0);
4516     if (i1notes)
4517       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL,
4518                         elim_i2, local_elim_i1, local_elim_i0);
4519     if (i0notes)
4520       distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL,
4521                         elim_i2, elim_i1, local_elim_i0);
4522     if (midnotes)
4523       distribute_notes (midnotes, NULL, i3, newi2pat ? i2 : NULL,
4524                         elim_i2, elim_i1, elim_i0);
4525
4526     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
4527        know these are REG_UNUSED and want them to go to the desired insn,
4528        so we always pass it as i3.  */
4529
4530     if (newi2pat && new_i2_notes)
4531       distribute_notes (new_i2_notes, i2, i2, NULL, NULL_RTX, NULL_RTX,
4532                         NULL_RTX);
4533
4534     if (new_i3_notes)
4535       distribute_notes (new_i3_notes, i3, i3, NULL, NULL_RTX, NULL_RTX,
4536                         NULL_RTX);
4537
4538     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
4539        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
4540        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
4541        in that case, it might delete I2.  Similarly for I2 and I1.
4542        Show an additional death due to the REG_DEAD note we make here.  If
4543        we discard it in distribute_notes, we will decrement it again.  */
4544
4545     if (i3dest_killed)
4546       {
4547         rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX);
4548         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4549           distribute_notes (new_note, NULL, i2, NULL, elim_i2,
4550                             elim_i1, elim_i0);
4551         else
4552           distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4553                             elim_i2, elim_i1, elim_i0);
4554       }
4555
4556     if (i2dest_in_i2src)
4557       {
4558         rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4559         if (newi2pat && reg_set_p (i2dest, newi2pat))
4560           distribute_notes (new_note,  NULL, i2, NULL, NULL_RTX,
4561                             NULL_RTX, NULL_RTX);
4562         else
4563           distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4564                             NULL_RTX, NULL_RTX, NULL_RTX);
4565       }
4566
4567     if (i1dest_in_i1src)
4568       {
4569         rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4570         if (newi2pat && reg_set_p (i1dest, newi2pat))
4571           distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4572                             NULL_RTX, NULL_RTX);
4573         else
4574           distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4575                             NULL_RTX, NULL_RTX, NULL_RTX);
4576       }
4577
4578     if (i0dest_in_i0src)
4579       {
4580         rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4581         if (newi2pat && reg_set_p (i0dest, newi2pat))
4582           distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4583                             NULL_RTX, NULL_RTX);
4584         else
4585           distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4586                             NULL_RTX, NULL_RTX, NULL_RTX);
4587       }
4588
4589     distribute_links (i3links);
4590     distribute_links (i2links);
4591     distribute_links (i1links);
4592     distribute_links (i0links);
4593
4594     if (REG_P (i2dest))
4595       {
4596         struct insn_link *link;
4597         rtx_insn *i2_insn = 0;
4598         rtx i2_val = 0, set;
4599
4600         /* The insn that used to set this register doesn't exist, and
4601            this life of the register may not exist either.  See if one of
4602            I3's links points to an insn that sets I2DEST.  If it does,
4603            that is now the last known value for I2DEST. If we don't update
4604            this and I2 set the register to a value that depended on its old
4605            contents, we will get confused.  If this insn is used, thing
4606            will be set correctly in combine_instructions.  */
4607         FOR_EACH_LOG_LINK (link, i3)
4608           if ((set = single_set (link->insn)) != 0
4609               && rtx_equal_p (i2dest, SET_DEST (set)))
4610             i2_insn = link->insn, i2_val = SET_SRC (set);
4611
4612         record_value_for_reg (i2dest, i2_insn, i2_val);
4613
4614         /* If the reg formerly set in I2 died only once and that was in I3,
4615            zero its use count so it won't make `reload' do any work.  */
4616         if (! added_sets_2
4617             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4618             && ! i2dest_in_i2src
4619             && REGNO (i2dest) < reg_n_sets_max)
4620           INC_REG_N_SETS (REGNO (i2dest), -1);
4621       }
4622
4623     if (i1 && REG_P (i1dest))
4624       {
4625         struct insn_link *link;
4626         rtx_insn *i1_insn = 0;
4627         rtx i1_val = 0, set;
4628
4629         FOR_EACH_LOG_LINK (link, i3)
4630           if ((set = single_set (link->insn)) != 0
4631               && rtx_equal_p (i1dest, SET_DEST (set)))
4632             i1_insn = link->insn, i1_val = SET_SRC (set);
4633
4634         record_value_for_reg (i1dest, i1_insn, i1_val);
4635
4636         if (! added_sets_1
4637             && ! i1dest_in_i1src
4638             && REGNO (i1dest) < reg_n_sets_max)
4639           INC_REG_N_SETS (REGNO (i1dest), -1);
4640       }
4641
4642     if (i0 && REG_P (i0dest))
4643       {
4644         struct insn_link *link;
4645         rtx_insn *i0_insn = 0;
4646         rtx i0_val = 0, set;
4647
4648         FOR_EACH_LOG_LINK (link, i3)
4649           if ((set = single_set (link->insn)) != 0
4650               && rtx_equal_p (i0dest, SET_DEST (set)))
4651             i0_insn = link->insn, i0_val = SET_SRC (set);
4652
4653         record_value_for_reg (i0dest, i0_insn, i0_val);
4654
4655         if (! added_sets_0
4656             && ! i0dest_in_i0src
4657             && REGNO (i0dest) < reg_n_sets_max)
4658           INC_REG_N_SETS (REGNO (i0dest), -1);
4659       }
4660
4661     /* Update reg_stat[].nonzero_bits et al for any changes that may have
4662        been made to this insn.  The order is important, because newi2pat
4663        can affect nonzero_bits of newpat.  */
4664     if (newi2pat)
4665       note_pattern_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4666     note_pattern_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4667   }
4668
4669   if (undobuf.other_insn != NULL_RTX)
4670     {
4671       if (dump_file)
4672         {
4673           fprintf (dump_file, "modifying other_insn ");
4674           dump_insn_slim (dump_file, undobuf.other_insn);
4675         }
4676       df_insn_rescan (undobuf.other_insn);
4677     }
4678
4679   if (i0 && !(NOTE_P (i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4680     {
4681       if (dump_file)
4682         {
4683           fprintf (dump_file, "modifying insn i0 ");
4684           dump_insn_slim (dump_file, i0);
4685         }
4686       df_insn_rescan (i0);
4687     }
4688
4689   if (i1 && !(NOTE_P (i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4690     {
4691       if (dump_file)
4692         {
4693           fprintf (dump_file, "modifying insn i1 ");
4694           dump_insn_slim (dump_file, i1);
4695         }
4696       df_insn_rescan (i1);
4697     }
4698
4699   if (i2 && !(NOTE_P (i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4700     {
4701       if (dump_file)
4702         {
4703           fprintf (dump_file, "modifying insn i2 ");
4704           dump_insn_slim (dump_file, i2);
4705         }
4706       df_insn_rescan (i2);
4707     }
4708
4709   if (i3 && !(NOTE_P (i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4710     {
4711       if (dump_file)
4712         {
4713           fprintf (dump_file, "modifying insn i3 ");
4714           dump_insn_slim (dump_file, i3);
4715         }
4716       df_insn_rescan (i3);
4717     }
4718
4719   /* Set new_direct_jump_p if a new return or simple jump instruction
4720      has been created.  Adjust the CFG accordingly.  */
4721   if (returnjump_p (i3) || any_uncondjump_p (i3))
4722     {
4723       *new_direct_jump_p = 1;
4724       mark_jump_label (PATTERN (i3), i3, 0);
4725       update_cfg_for_uncondjump (i3);
4726     }
4727
4728   if (undobuf.other_insn != NULL_RTX
4729       && (returnjump_p (undobuf.other_insn)
4730           || any_uncondjump_p (undobuf.other_insn)))
4731     {
4732       *new_direct_jump_p = 1;
4733       update_cfg_for_uncondjump (undobuf.other_insn);
4734     }
4735
4736   if (GET_CODE (PATTERN (i3)) == TRAP_IF
4737       && XEXP (PATTERN (i3), 0) == const1_rtx)
4738     {
4739       basic_block bb = BLOCK_FOR_INSN (i3);
4740       gcc_assert (bb);
4741       remove_edge (split_block (bb, i3));
4742       emit_barrier_after_bb (bb);
4743       *new_direct_jump_p = 1;
4744     }
4745
4746   if (undobuf.other_insn
4747       && GET_CODE (PATTERN (undobuf.other_insn)) == TRAP_IF
4748       && XEXP (PATTERN (undobuf.other_insn), 0) == const1_rtx)
4749     {
4750       basic_block bb = BLOCK_FOR_INSN (undobuf.other_insn);
4751       gcc_assert (bb);
4752       remove_edge (split_block (bb, undobuf.other_insn));
4753       emit_barrier_after_bb (bb);
4754       *new_direct_jump_p = 1;
4755     }
4756
4757   /* A noop might also need cleaning up of CFG, if it comes from the
4758      simplification of a jump.  */
4759   if (JUMP_P (i3)
4760       && GET_CODE (newpat) == SET
4761       && SET_SRC (newpat) == pc_rtx
4762       && SET_DEST (newpat) == pc_rtx)
4763     {
4764       *new_direct_jump_p = 1;
4765       update_cfg_for_uncondjump (i3);
4766     }
4767
4768   if (undobuf.other_insn != NULL_RTX
4769       && JUMP_P (undobuf.other_insn)
4770       && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4771       && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4772       && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4773     {
4774       *new_direct_jump_p = 1;
4775       update_cfg_for_uncondjump (undobuf.other_insn);
4776     }
4777
4778   combine_successes++;
4779   undo_commit ();
4780
4781   rtx_insn *ret = newi2pat ? i2 : i3;
4782   if (added_links_insn && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (ret))
4783     ret = added_links_insn;
4784   if (added_notes_insn && DF_INSN_LUID (added_notes_insn) < DF_INSN_LUID (ret))
4785     ret = added_notes_insn;
4786
4787   return ret;
4788 }
4789 \f
4790 /* Get a marker for undoing to the current state.  */
4791
4792 static void *
4793 get_undo_marker (void)
4794 {
4795   return undobuf.undos;
4796 }
4797
4798 /* Undo the modifications up to the marker.  */
4799
4800 static void
4801 undo_to_marker (void *marker)
4802 {
4803   struct undo *undo, *next;
4804
4805   for (undo = undobuf.undos; undo != marker; undo = next)
4806     {
4807       gcc_assert (undo);
4808
4809       next = undo->next;
4810       switch (undo->kind)
4811         {
4812         case UNDO_RTX:
4813           *undo->where.r = undo->old_contents.r;
4814           break;
4815         case UNDO_INT:
4816           *undo->where.i = undo->old_contents.i;
4817           break;
4818         case UNDO_MODE:
4819           adjust_reg_mode (regno_reg_rtx[undo->where.regno],
4820                            undo->old_contents.m);
4821           break;
4822         case UNDO_LINKS:
4823           *undo->where.l = undo->old_contents.l;
4824           break;
4825         default:
4826           gcc_unreachable ();
4827         }
4828
4829       undo->next = undobuf.frees;
4830       undobuf.frees = undo;
4831     }
4832
4833   undobuf.undos = (struct undo *) marker;
4834 }
4835
4836 /* Undo all the modifications recorded in undobuf.  */
4837
4838 static void
4839 undo_all (void)
4840 {
4841   undo_to_marker (0);
4842 }
4843
4844 /* We've committed to accepting the changes we made.  Move all
4845    of the undos to the free list.  */
4846
4847 static void
4848 undo_commit (void)
4849 {
4850   struct undo *undo, *next;
4851
4852   for (undo = undobuf.undos; undo; undo = next)
4853     {
4854       next = undo->next;
4855       undo->next = undobuf.frees;
4856       undobuf.frees = undo;
4857     }
4858   undobuf.undos = 0;
4859 }
4860 \f
4861 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4862    where we have an arithmetic expression and return that point.  LOC will
4863    be inside INSN.
4864
4865    try_combine will call this function to see if an insn can be split into
4866    two insns.  */
4867
4868 static rtx *
4869 find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
4870 {
4871   rtx x = *loc;
4872   enum rtx_code code = GET_CODE (x);
4873   rtx *split;
4874   unsigned HOST_WIDE_INT len = 0;
4875   HOST_WIDE_INT pos = 0;
4876   bool unsignedp = false;
4877   rtx inner = NULL_RTX;
4878   scalar_int_mode mode, inner_mode;
4879
4880   /* First special-case some codes.  */
4881   switch (code)
4882     {
4883     case SUBREG:
4884 #ifdef INSN_SCHEDULING
4885       /* If we are making a paradoxical SUBREG invalid, it becomes a split
4886          point.  */
4887       if (MEM_P (SUBREG_REG (x)))
4888         return loc;
4889 #endif
4890       return find_split_point (&SUBREG_REG (x), insn, false);
4891
4892     case MEM:
4893       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4894          using LO_SUM and HIGH.  */
4895       if (HAVE_lo_sum && (GET_CODE (XEXP (x, 0)) == CONST
4896                           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF))
4897         {
4898           machine_mode address_mode = get_address_mode (x);
4899
4900           SUBST (XEXP (x, 0),
4901                  gen_rtx_LO_SUM (address_mode,
4902                                  gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4903                                  XEXP (x, 0)));
4904           return &XEXP (XEXP (x, 0), 0);
4905         }
4906
4907       /* If we have a PLUS whose second operand is a constant and the
4908          address is not valid, perhaps we can split it up using
4909          the machine-specific way to split large constants.  We use
4910          the first pseudo-reg (one of the virtual regs) as a placeholder;
4911          it will not remain in the result.  */
4912       if (GET_CODE (XEXP (x, 0)) == PLUS
4913           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4914           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4915                                             MEM_ADDR_SPACE (x)))
4916         {
4917           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4918           rtx_insn *seq = combine_split_insns (gen_rtx_SET (reg, XEXP (x, 0)),
4919                                                subst_insn);
4920
4921           /* This should have produced two insns, each of which sets our
4922              placeholder.  If the source of the second is a valid address,
4923              we can put both sources together and make a split point
4924              in the middle.  */
4925
4926           if (seq
4927               && NEXT_INSN (seq) != NULL_RTX
4928               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4929               && NONJUMP_INSN_P (seq)
4930               && GET_CODE (PATTERN (seq)) == SET
4931               && SET_DEST (PATTERN (seq)) == reg
4932               && ! reg_mentioned_p (reg,
4933                                     SET_SRC (PATTERN (seq)))
4934               && NONJUMP_INSN_P (NEXT_INSN (seq))
4935               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4936               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4937               && memory_address_addr_space_p
4938                    (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4939                     MEM_ADDR_SPACE (x)))
4940             {
4941               rtx src1 = SET_SRC (PATTERN (seq));
4942               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4943
4944               /* Replace the placeholder in SRC2 with SRC1.  If we can
4945                  find where in SRC2 it was placed, that can become our
4946                  split point and we can replace this address with SRC2.
4947                  Just try two obvious places.  */
4948
4949               src2 = replace_rtx (src2, reg, src1);
4950               split = 0;
4951               if (XEXP (src2, 0) == src1)
4952                 split = &XEXP (src2, 0);
4953               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4954                        && XEXP (XEXP (src2, 0), 0) == src1)
4955                 split = &XEXP (XEXP (src2, 0), 0);
4956
4957               if (split)
4958                 {
4959                   SUBST (XEXP (x, 0), src2);
4960                   return split;
4961                 }
4962             }
4963
4964           /* If that didn't work and we have a nested plus, like:
4965              ((REG1 * CONST1) + REG2) + CONST2 and (REG1 + REG2) + CONST2
4966              is valid address, try to split (REG1 * CONST1).  */
4967           if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
4968               && !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
4969               && OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
4970               && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SUBREG
4971                     && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
4972                                                          0), 0)))))
4973             {
4974               rtx tem = XEXP (XEXP (XEXP (x, 0), 0), 0);
4975               XEXP (XEXP (XEXP (x, 0), 0), 0) = reg;
4976               if (memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4977                                                MEM_ADDR_SPACE (x)))
4978                 {
4979                   XEXP (XEXP (XEXP (x, 0), 0), 0) = tem;
4980                   return &XEXP (XEXP (XEXP (x, 0), 0), 0);
4981                 }
4982               XEXP (XEXP (XEXP (x, 0), 0), 0) = tem;
4983             }
4984           else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
4985                    && OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
4986                    && !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
4987                    && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == SUBREG
4988                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
4989                                                               0), 1)))))
4990             {
4991               rtx tem = XEXP (XEXP (XEXP (x, 0), 0), 1);
4992               XEXP (XEXP (XEXP (x, 0), 0), 1) = reg;
4993               if (memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4994                                                MEM_ADDR_SPACE (x)))
4995                 {
4996                   XEXP (XEXP (XEXP (x, 0), 0), 1) = tem;
4997                   return &XEXP (XEXP (XEXP (x, 0), 0), 1);
4998                 }
4999               XEXP (XEXP (XEXP (x, 0), 0), 1) = tem;
5000             }
5001
5002           /* If that didn't work, perhaps the first operand is complex and
5003              needs to be computed separately, so make a split point there.
5004              This will occur on machines that just support REG + CONST
5005              and have a constant moved through some previous computation.  */
5006           if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
5007               && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
5008                     && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
5009             return &XEXP (XEXP (x, 0), 0);
5010         }
5011
5012       /* If we have a PLUS whose first operand is complex, try computing it
5013          separately by making a split there.  */
5014       if (GET_CODE (XEXP (x, 0)) == PLUS
5015           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
5016                                             MEM_ADDR_SPACE (x))
5017           && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
5018           && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
5019                 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
5020         return &XEXP (XEXP (x, 0), 0);
5021       break;
5022
5023     case SET:
5024       /* See if we can split SET_SRC as it stands.  */
5025       split = find_split_point (&SET_SRC (x), insn, true);
5026       if (split && split != &SET_SRC (x))
5027         return split;
5028
5029       /* See if we can split SET_DEST as it stands.  */
5030       split = find_split_point (&SET_DEST (x), insn, false);
5031       if (split && split != &SET_DEST (x))
5032         return split;
5033
5034       /* See if this is a bitfield assignment with everything constant.  If
5035          so, this is an IOR of an AND, so split it into that.  */
5036       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5037           && is_a <scalar_int_mode> (GET_MODE (XEXP (SET_DEST (x), 0)),
5038                                      &inner_mode)
5039           && HWI_COMPUTABLE_MODE_P (inner_mode)
5040           && CONST_INT_P (XEXP (SET_DEST (x), 1))
5041           && CONST_INT_P (XEXP (SET_DEST (x), 2))
5042           && CONST_INT_P (SET_SRC (x))
5043           && ((INTVAL (XEXP (SET_DEST (x), 1))
5044                + INTVAL (XEXP (SET_DEST (x), 2)))
5045               <= GET_MODE_PRECISION (inner_mode))
5046           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
5047         {
5048           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
5049           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
5050           rtx dest = XEXP (SET_DEST (x), 0);
5051           unsigned HOST_WIDE_INT mask = (HOST_WIDE_INT_1U << len) - 1;
5052           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x)) & mask;
5053           rtx or_mask;
5054
5055           if (BITS_BIG_ENDIAN)
5056             pos = GET_MODE_PRECISION (inner_mode) - len - pos;
5057
5058           or_mask = gen_int_mode (src << pos, inner_mode);
5059           if (src == mask)
5060             SUBST (SET_SRC (x),
5061                    simplify_gen_binary (IOR, inner_mode, dest, or_mask));
5062           else
5063             {
5064               rtx negmask = gen_int_mode (~(mask << pos), inner_mode);
5065               SUBST (SET_SRC (x),
5066                      simplify_gen_binary (IOR, inner_mode,
5067                                           simplify_gen_binary (AND, inner_mode,
5068                                                                dest, negmask),
5069                                           or_mask));
5070             }
5071
5072           SUBST (SET_DEST (x), dest);
5073
5074           split = find_split_point (&SET_SRC (x), insn, true);
5075           if (split && split != &SET_SRC (x))
5076             return split;
5077         }
5078
5079       /* Otherwise, see if this is an operation that we can split into two.
5080          If so, try to split that.  */
5081       code = GET_CODE (SET_SRC (x));
5082
5083       switch (code)
5084         {
5085         case AND:
5086           /* If we are AND'ing with a large constant that is only a single
5087              bit and the result is only being used in a context where we
5088              need to know if it is zero or nonzero, replace it with a bit
5089              extraction.  This will avoid the large constant, which might
5090              have taken more than one insn to make.  If the constant were
5091              not a valid argument to the AND but took only one insn to make,
5092              this is no worse, but if it took more than one insn, it will
5093              be better.  */
5094
5095           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
5096               && REG_P (XEXP (SET_SRC (x), 0))
5097               && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
5098               && REG_P (SET_DEST (x))
5099               && (split = find_single_use (SET_DEST (x), insn, NULL)) != 0
5100               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
5101               && XEXP (*split, 0) == SET_DEST (x)
5102               && XEXP (*split, 1) == const0_rtx)
5103             {
5104               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
5105                                                 XEXP (SET_SRC (x), 0),
5106                                                 pos, NULL_RTX, 1,
5107                                                 true, false, false);
5108               if (extraction != 0)
5109                 {
5110                   SUBST (SET_SRC (x), extraction);
5111                   return find_split_point (loc, insn, false);
5112                 }
5113             }
5114           break;
5115
5116         case NE:
5117           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5118              is known to be on, this can be converted into a NEG of a shift.  */
5119           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
5120               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
5121               && ((pos = exact_log2 (nonzero_bits (XEXP (SET_SRC (x), 0),
5122                                                    GET_MODE (XEXP (SET_SRC (x),
5123                                                              0))))) >= 1))
5124             {
5125               machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
5126               rtx pos_rtx = gen_int_shift_amount (mode, pos);
5127               SUBST (SET_SRC (x),
5128                      gen_rtx_NEG (mode,
5129                                   gen_rtx_LSHIFTRT (mode,
5130                                                     XEXP (SET_SRC (x), 0),
5131                                                     pos_rtx)));
5132
5133               split = find_split_point (&SET_SRC (x), insn, true);
5134               if (split && split != &SET_SRC (x))
5135                 return split;
5136             }
5137           break;
5138
5139         case SIGN_EXTEND:
5140           inner = XEXP (SET_SRC (x), 0);
5141
5142           /* We can't optimize if either mode is a partial integer
5143              mode as we don't know how many bits are significant
5144              in those modes.  */
5145           if (!is_int_mode (GET_MODE (inner), &inner_mode)
5146               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
5147             break;
5148
5149           pos = 0;
5150           len = GET_MODE_PRECISION (inner_mode);
5151           unsignedp = false;
5152           break;
5153
5154         case SIGN_EXTRACT:
5155         case ZERO_EXTRACT:
5156           if (is_a <scalar_int_mode> (GET_MODE (XEXP (SET_SRC (x), 0)),
5157                                       &inner_mode)
5158               && CONST_INT_P (XEXP (SET_SRC (x), 1))
5159               && CONST_INT_P (XEXP (SET_SRC (x), 2)))
5160             {
5161               inner = XEXP (SET_SRC (x), 0);
5162               len = INTVAL (XEXP (SET_SRC (x), 1));
5163               pos = INTVAL (XEXP (SET_SRC (x), 2));
5164
5165               if (BITS_BIG_ENDIAN)
5166                 pos = GET_MODE_PRECISION (inner_mode) - len - pos;
5167               unsignedp = (code == ZERO_EXTRACT);
5168             }
5169           break;
5170
5171         default:
5172           break;
5173         }
5174
5175       if (len
5176           && known_subrange_p (pos, len,
5177                                0, GET_MODE_PRECISION (GET_MODE (inner)))
5178           && is_a <scalar_int_mode> (GET_MODE (SET_SRC (x)), &mode))
5179         {
5180           /* For unsigned, we have a choice of a shift followed by an
5181              AND or two shifts.  Use two shifts for field sizes where the
5182              constant might be too large.  We assume here that we can
5183              always at least get 8-bit constants in an AND insn, which is
5184              true for every current RISC.  */
5185
5186           if (unsignedp && len <= 8)
5187             {
5188               unsigned HOST_WIDE_INT mask
5189                 = (HOST_WIDE_INT_1U << len) - 1;
5190               rtx pos_rtx = gen_int_shift_amount (mode, pos);
5191               SUBST (SET_SRC (x),
5192                      gen_rtx_AND (mode,
5193                                   gen_rtx_LSHIFTRT
5194                                   (mode, gen_lowpart (mode, inner), pos_rtx),
5195                                   gen_int_mode (mask, mode)));
5196
5197               split = find_split_point (&SET_SRC (x), insn, true);
5198               if (split && split != &SET_SRC (x))
5199                 return split;
5200             }
5201           else
5202             {
5203               int left_bits = GET_MODE_PRECISION (mode) - len - pos;
5204               int right_bits = GET_MODE_PRECISION (mode) - len;
5205               SUBST (SET_SRC (x),
5206                      gen_rtx_fmt_ee
5207                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
5208                       gen_rtx_ASHIFT (mode,
5209                                       gen_lowpart (mode, inner),
5210                                       gen_int_shift_amount (mode, left_bits)),
5211                       gen_int_shift_amount (mode, right_bits)));
5212
5213               split = find_split_point (&SET_SRC (x), insn, true);
5214               if (split && split != &SET_SRC (x))
5215                 return split;
5216             }
5217         }
5218
5219       /* See if this is a simple operation with a constant as the second
5220          operand.  It might be that this constant is out of range and hence
5221          could be used as a split point.  */
5222       if (BINARY_P (SET_SRC (x))
5223           && CONSTANT_P (XEXP (SET_SRC (x), 1))
5224           && (OBJECT_P (XEXP (SET_SRC (x), 0))
5225               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
5226                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
5227         return &XEXP (SET_SRC (x), 1);
5228
5229       /* Finally, see if this is a simple operation with its first operand
5230          not in a register.  The operation might require this operand in a
5231          register, so return it as a split point.  We can always do this
5232          because if the first operand were another operation, we would have
5233          already found it as a split point.  */
5234       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
5235           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
5236         return &XEXP (SET_SRC (x), 0);
5237
5238       return 0;
5239
5240     case AND:
5241     case IOR:
5242       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5243          it is better to write this as (not (ior A B)) so we can split it.
5244          Similarly for IOR.  */
5245       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
5246         {
5247           SUBST (*loc,
5248                  gen_rtx_NOT (GET_MODE (x),
5249                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
5250                                               GET_MODE (x),
5251                                               XEXP (XEXP (x, 0), 0),
5252                                               XEXP (XEXP (x, 1), 0))));
5253           return find_split_point (loc, insn, set_src);
5254         }
5255
5256       /* Many RISC machines have a large set of logical insns.  If the
5257          second operand is a NOT, put it first so we will try to split the
5258          other operand first.  */
5259       if (GET_CODE (XEXP (x, 1)) == NOT)
5260         {
5261           rtx tem = XEXP (x, 0);
5262           SUBST (XEXP (x, 0), XEXP (x, 1));
5263           SUBST (XEXP (x, 1), tem);
5264         }
5265       break;
5266
5267     case PLUS:
5268     case MINUS:
5269       /* Canonicalization can produce (minus A (mult B C)), where C is a
5270          constant.  It may be better to try splitting (plus (mult B -C) A)
5271          instead if this isn't a multiply by a power of two.  */
5272       if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
5273           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
5274           && !pow2p_hwi (INTVAL (XEXP (XEXP (x, 1), 1))))
5275         {
5276           machine_mode mode = GET_MODE (x);
5277           unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
5278           HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
5279           SUBST (*loc, gen_rtx_PLUS (mode,
5280                                      gen_rtx_MULT (mode,
5281                                                    XEXP (XEXP (x, 1), 0),
5282                                                    gen_int_mode (other_int,
5283                                                                  mode)),
5284                                      XEXP (x, 0)));
5285           return find_split_point (loc, insn, set_src);
5286         }
5287
5288       /* Split at a multiply-accumulate instruction.  However if this is
5289          the SET_SRC, we likely do not have such an instruction and it's
5290          worthless to try this split.  */
5291       if (!set_src
5292           && (GET_CODE (XEXP (x, 0)) == MULT
5293               || (GET_CODE (XEXP (x, 0)) == ASHIFT
5294                   && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
5295         return loc;
5296
5297     default:
5298       break;
5299     }
5300
5301   /* Otherwise, select our actions depending on our rtx class.  */
5302   switch (GET_RTX_CLASS (code))
5303     {
5304     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
5305     case RTX_TERNARY:
5306       split = find_split_point (&XEXP (x, 2), insn, false);
5307       if (split)
5308         return split;
5309       /* fall through */
5310     case RTX_BIN_ARITH:
5311     case RTX_COMM_ARITH:
5312     case RTX_COMPARE:
5313     case RTX_COMM_COMPARE:
5314       split = find_split_point (&XEXP (x, 1), insn, false);
5315       if (split)
5316         return split;
5317       /* fall through */
5318     case RTX_UNARY:
5319       /* Some machines have (and (shift ...) ...) insns.  If X is not
5320          an AND, but XEXP (X, 0) is, use it as our split point.  */
5321       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
5322         return &XEXP (x, 0);
5323
5324       split = find_split_point (&XEXP (x, 0), insn, false);
5325       if (split)
5326         return split;
5327       return loc;
5328
5329     default:
5330       /* Otherwise, we don't have a split point.  */
5331       return 0;
5332     }
5333 }
5334 \f
5335 /* Throughout X, replace FROM with TO, and return the result.
5336    The result is TO if X is FROM;
5337    otherwise the result is X, but its contents may have been modified.
5338    If they were modified, a record was made in undobuf so that
5339    undo_all will (among other things) return X to its original state.
5340
5341    If the number of changes necessary is too much to record to undo,
5342    the excess changes are not made, so the result is invalid.
5343    The changes already made can still be undone.
5344    undobuf.num_undo is incremented for such changes, so by testing that
5345    the caller can tell whether the result is valid.
5346
5347    `n_occurrences' is incremented each time FROM is replaced.
5348
5349    IN_DEST is true if we are processing the SET_DEST of a SET.
5350
5351    IN_COND is true if we are at the top level of a condition.
5352
5353    UNIQUE_COPY is true if each substitution must be unique.  We do this
5354    by copying if `n_occurrences' is nonzero.  */
5355
5356 static rtx
5357 subst (rtx x, rtx from, rtx to, bool in_dest, bool in_cond, bool unique_copy)
5358 {
5359   enum rtx_code code = GET_CODE (x);
5360   machine_mode op0_mode = VOIDmode;
5361   const char *fmt;
5362   int len, i;
5363   rtx new_rtx;
5364
5365 /* Two expressions are equal if they are identical copies of a shared
5366    RTX or if they are both registers with the same register number
5367    and mode.  */
5368
5369 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
5370   ((X) == (Y)                                           \
5371    || (REG_P (X) && REG_P (Y)   \
5372        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5373
5374   /* Do not substitute into clobbers of regs -- this will never result in
5375      valid RTL.  */
5376   if (GET_CODE (x) == CLOBBER && REG_P (XEXP (x, 0)))
5377     return x;
5378
5379   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
5380     {
5381       n_occurrences++;
5382       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
5383     }
5384
5385   /* If X and FROM are the same register but different modes, they
5386      will not have been seen as equal above.  However, the log links code
5387      will make a LOG_LINKS entry for that case.  If we do nothing, we
5388      will try to rerecognize our original insn and, when it succeeds,
5389      we will delete the feeding insn, which is incorrect.
5390
5391      So force this insn not to match in this (rare) case.  */
5392   if (! in_dest && code == REG && REG_P (from)
5393       && reg_overlap_mentioned_p (x, from))
5394     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
5395
5396   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5397      of which may contain things that can be combined.  */
5398   if (code != MEM && code != LO_SUM && OBJECT_P (x))
5399     return x;
5400
5401   /* It is possible to have a subexpression appear twice in the insn.
5402      Suppose that FROM is a register that appears within TO.
5403      Then, after that subexpression has been scanned once by `subst',
5404      the second time it is scanned, TO may be found.  If we were
5405      to scan TO here, we would find FROM within it and create a
5406      self-referent rtl structure which is completely wrong.  */
5407   if (COMBINE_RTX_EQUAL_P (x, to))
5408     return to;
5409
5410   /* Parallel asm_operands need special attention because all of the
5411      inputs are shared across the arms.  Furthermore, unsharing the
5412      rtl results in recognition failures.  Failure to handle this case
5413      specially can result in circular rtl.
5414
5415      Solve this by doing a normal pass across the first entry of the
5416      parallel, and only processing the SET_DESTs of the subsequent
5417      entries.  Ug.  */
5418
5419   if (code == PARALLEL
5420       && GET_CODE (XVECEXP (x, 0, 0)) == SET
5421       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5422     {
5423       new_rtx = subst (XVECEXP (x, 0, 0), from, to, false, false, unique_copy);
5424
5425       /* If this substitution failed, this whole thing fails.  */
5426       if (GET_CODE (new_rtx) == CLOBBER
5427           && XEXP (new_rtx, 0) == const0_rtx)
5428         return new_rtx;
5429
5430       SUBST (XVECEXP (x, 0, 0), new_rtx);
5431
5432       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5433         {
5434           rtx dest = SET_DEST (XVECEXP (x, 0, i));
5435
5436           if (!REG_P (dest) && GET_CODE (dest) != PC)
5437             {
5438               new_rtx = subst (dest, from, to, false, false, unique_copy);
5439
5440               /* If this substitution failed, this whole thing fails.  */
5441               if (GET_CODE (new_rtx) == CLOBBER
5442                   && XEXP (new_rtx, 0) == const0_rtx)
5443                 return new_rtx;
5444
5445               SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5446             }
5447         }
5448     }
5449   else
5450     {
5451       len = GET_RTX_LENGTH (code);
5452       fmt = GET_RTX_FORMAT (code);
5453
5454       /* We don't need to process a SET_DEST that is a register or PC, so
5455          set up to skip this common case.  All other cases where we want
5456          to suppress replacing something inside a SET_SRC are handled via
5457          the IN_DEST operand.  */
5458       if (code == SET
5459           && (REG_P (SET_DEST (x))
5460               || GET_CODE (SET_DEST (x)) == PC))
5461         fmt = "ie";
5462
5463       /* Trying to simplify the operands of a widening MULT is not likely
5464          to create RTL matching a machine insn.  */
5465       if (code == MULT
5466           && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5467               || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
5468           && (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND
5469               || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
5470           && REG_P (XEXP (XEXP (x, 0), 0))
5471           && REG_P (XEXP (XEXP (x, 1), 0))
5472           && from == to)
5473         return x;
5474
5475
5476       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5477          constant.  */
5478       if (fmt[0] == 'e')
5479         op0_mode = GET_MODE (XEXP (x, 0));
5480
5481       for (i = 0; i < len; i++)
5482         {
5483           if (fmt[i] == 'E')
5484             {
5485               int j;
5486               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5487                 {
5488                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5489                     {
5490                       new_rtx = (unique_copy && n_occurrences
5491                              ? copy_rtx (to) : to);
5492                       n_occurrences++;
5493                     }
5494                   else
5495                     {
5496                       new_rtx = subst (XVECEXP (x, i, j), from, to,
5497                                        false, false, unique_copy);
5498
5499                       /* If this substitution failed, this whole thing
5500                          fails.  */
5501                       if (GET_CODE (new_rtx) == CLOBBER
5502                           && XEXP (new_rtx, 0) == const0_rtx)
5503                         return new_rtx;
5504                     }
5505
5506                   SUBST (XVECEXP (x, i, j), new_rtx);
5507                 }
5508             }
5509           else if (fmt[i] == 'e')
5510             {
5511               /* If this is a register being set, ignore it.  */
5512               new_rtx = XEXP (x, i);
5513               if (in_dest
5514                   && i == 0
5515                   && (((code == SUBREG || code == ZERO_EXTRACT)
5516                        && REG_P (new_rtx))
5517                       || code == STRICT_LOW_PART))
5518                 ;
5519
5520               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5521                 {
5522                   /* In general, don't install a subreg involving two
5523                      modes not tieable.  It can worsen register
5524                      allocation, and can even make invalid reload
5525                      insns, since the reg inside may need to be copied
5526                      from in the outside mode, and that may be invalid
5527                      if it is an fp reg copied in integer mode.
5528
5529                      We allow an exception to this: It is valid if
5530                      it is inside another SUBREG and the mode of that
5531                      SUBREG and the mode of the inside of TO is
5532                      tieable.  */
5533
5534                   if (GET_CODE (to) == SUBREG
5535                       && !targetm.modes_tieable_p (GET_MODE (to),
5536                                                    GET_MODE (SUBREG_REG (to)))
5537                       && ! (code == SUBREG
5538                             && (targetm.modes_tieable_p
5539                                 (GET_MODE (x), GET_MODE (SUBREG_REG (to))))))
5540                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5541
5542                   if (code == SUBREG
5543                       && REG_P (to)
5544                       && REGNO (to) < FIRST_PSEUDO_REGISTER
5545                       && simplify_subreg_regno (REGNO (to), GET_MODE (to),
5546                                                 SUBREG_BYTE (x),
5547                                                 GET_MODE (x)) < 0)
5548                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5549
5550                   new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5551                   n_occurrences++;
5552                 }
5553               else
5554                 /* If we are in a SET_DEST, suppress most cases unless we
5555                    have gone inside a MEM, in which case we want to
5556                    simplify the address.  We assume here that things that
5557                    are actually part of the destination have their inner
5558                    parts in the first expression.  This is true for SUBREG,
5559                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5560                    things aside from REG and MEM that should appear in a
5561                    SET_DEST.  */
5562                 new_rtx = subst (XEXP (x, i), from, to,
5563                              (((in_dest
5564                                 && (code == SUBREG || code == STRICT_LOW_PART
5565                                     || code == ZERO_EXTRACT))
5566                                || code == SET)
5567                               && i == 0),
5568                                  code == IF_THEN_ELSE && i == 0,
5569                                  unique_copy);
5570
5571               /* If we found that we will have to reject this combination,
5572                  indicate that by returning the CLOBBER ourselves, rather than
5573                  an expression containing it.  This will speed things up as
5574                  well as prevent accidents where two CLOBBERs are considered
5575                  to be equal, thus producing an incorrect simplification.  */
5576
5577               if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5578                 return new_rtx;
5579
5580               if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
5581                 {
5582                   machine_mode mode = GET_MODE (x);
5583
5584                   x = simplify_subreg (GET_MODE (x), new_rtx,
5585                                        GET_MODE (SUBREG_REG (x)),
5586                                        SUBREG_BYTE (x));
5587                   if (! x)
5588                     x = gen_rtx_CLOBBER (mode, const0_rtx);
5589                 }
5590               else if (CONST_SCALAR_INT_P (new_rtx)
5591                        && (GET_CODE (x) == ZERO_EXTEND
5592                            || GET_CODE (x) == SIGN_EXTEND
5593                            || GET_CODE (x) == FLOAT
5594                            || GET_CODE (x) == UNSIGNED_FLOAT))
5595                 {
5596                   x = simplify_unary_operation (GET_CODE (x), GET_MODE (x),
5597                                                 new_rtx,
5598                                                 GET_MODE (XEXP (x, 0)));
5599                   if (!x)
5600                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5601                 }
5602               /* CONST_INTs shouldn't be substituted into PRE_DEC, PRE_MODIFY
5603                  etc. arguments, otherwise we can ICE before trying to recog
5604                  it.  See PR104446.  */
5605               else if (CONST_SCALAR_INT_P (new_rtx)
5606                        && GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC)
5607                 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5608               else
5609                 SUBST (XEXP (x, i), new_rtx);
5610             }
5611         }
5612     }
5613
5614   /* Check if we are loading something from the constant pool via float
5615      extension; in this case we would undo compress_float_constant
5616      optimization and degenerate constant load to an immediate value.  */
5617   if (GET_CODE (x) == FLOAT_EXTEND
5618       && MEM_P (XEXP (x, 0))
5619       && MEM_READONLY_P (XEXP (x, 0)))
5620     {
5621       rtx tmp = avoid_constant_pool_reference (x);
5622       if (x != tmp)
5623         return x;
5624     }
5625
5626   /* Try to simplify X.  If the simplification changed the code, it is likely
5627      that further simplification will help, so loop, but limit the number
5628      of repetitions that will be performed.  */
5629
5630   for (i = 0; i < 4; i++)
5631     {
5632       /* If X is sufficiently simple, don't bother trying to do anything
5633          with it.  */
5634       if (code != CONST_INT && code != REG && code != CLOBBER)
5635         x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5636
5637       if (GET_CODE (x) == code)
5638         break;
5639
5640       code = GET_CODE (x);
5641
5642       /* We no longer know the original mode of operand 0 since we
5643          have changed the form of X)  */
5644       op0_mode = VOIDmode;
5645     }
5646
5647   return x;
5648 }
5649 \f
5650 /* If X is a commutative operation whose operands are not in the canonical
5651    order, use substitutions to swap them.  */
5652
5653 static void
5654 maybe_swap_commutative_operands (rtx x)
5655 {
5656   if (COMMUTATIVE_ARITH_P (x)
5657       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5658     {
5659       rtx temp = XEXP (x, 0);
5660       SUBST (XEXP (x, 0), XEXP (x, 1));
5661       SUBST (XEXP (x, 1), temp);
5662     }
5663
5664   /* Canonicalize (vec_merge (fma op2 op1 op3) op1 mask) to
5665      (vec_merge (fma op1 op2 op3) op1 mask).  */
5666   if (GET_CODE (x) == VEC_MERGE
5667       && GET_CODE (XEXP (x, 0)) == FMA)
5668     {
5669       rtx fma_op1 = XEXP (XEXP (x, 0), 0);
5670       rtx fma_op2 = XEXP (XEXP (x, 0), 1);
5671       rtx masked_op = XEXP (x, 1);
5672       if (rtx_equal_p (masked_op, fma_op2))
5673         {
5674           if (GET_CODE (fma_op1) == NEG)
5675             {
5676               /* Keep the negate canonicalized to the first operand.  */
5677               fma_op1 = XEXP (fma_op1, 0);
5678               SUBST (XEXP (XEXP (XEXP (x, 0), 0), 0), fma_op2);
5679               SUBST (XEXP (XEXP (x, 0), 1), fma_op1);
5680             }
5681           else
5682             {
5683               SUBST (XEXP (XEXP (x, 0), 0), fma_op2);
5684               SUBST (XEXP (XEXP (x, 0), 1), fma_op1);
5685             }
5686         }
5687     }
5688
5689   unsigned n_elts = 0;
5690   if (GET_CODE (x) == VEC_MERGE
5691       && CONST_INT_P (XEXP (x, 2))
5692       && GET_MODE_NUNITS (GET_MODE (x)).is_constant (&n_elts)
5693       && (swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))
5694           /* Two operands have same precedence, then
5695              first bit of mask select first operand.  */
5696           || (!swap_commutative_operands_p (XEXP (x, 1), XEXP (x, 0))
5697               && !(UINTVAL (XEXP (x, 2)) & 1))))
5698     {
5699       rtx temp = XEXP (x, 0);
5700       unsigned HOST_WIDE_INT sel = UINTVAL (XEXP (x, 2));
5701       unsigned HOST_WIDE_INT mask = HOST_WIDE_INT_1U;
5702       if (n_elts == HOST_BITS_PER_WIDE_INT)
5703         mask = -1;
5704       else
5705         mask = (HOST_WIDE_INT_1U << n_elts) - 1;
5706       SUBST (XEXP (x, 0), XEXP (x, 1));
5707       SUBST (XEXP (x, 1), temp);
5708       SUBST (XEXP (x, 2), GEN_INT (~sel & mask));
5709     }
5710 }
5711
5712 /* Simplify X, a piece of RTL.  We just operate on the expression at the
5713    outer level; call `subst' to simplify recursively.  Return the new
5714    expression.
5715
5716    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is true
5717    if we are inside a SET_DEST.  IN_COND is true if we are at the top level
5718    of a condition.  */
5719
5720 static rtx
5721 combine_simplify_rtx (rtx x, machine_mode op0_mode, bool in_dest, bool in_cond)
5722 {
5723   enum rtx_code code = GET_CODE (x);
5724   machine_mode mode = GET_MODE (x);
5725   scalar_int_mode int_mode;
5726   rtx temp;
5727   int i;
5728
5729   /* If this is a commutative operation, put a constant last and a complex
5730      expression first.  We don't need to do this for comparisons here.  */
5731   maybe_swap_commutative_operands (x);
5732
5733   /* Try to fold this expression in case we have constants that weren't
5734      present before.  */
5735   temp = 0;
5736   switch (GET_RTX_CLASS (code))
5737     {
5738     case RTX_UNARY:
5739       if (op0_mode == VOIDmode)
5740         op0_mode = GET_MODE (XEXP (x, 0));
5741       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5742       break;
5743     case RTX_COMPARE:
5744     case RTX_COMM_COMPARE:
5745       {
5746         machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5747         if (cmp_mode == VOIDmode)
5748           {
5749             cmp_mode = GET_MODE (XEXP (x, 1));
5750             if (cmp_mode == VOIDmode)
5751               cmp_mode = op0_mode;
5752           }
5753         temp = simplify_relational_operation (code, mode, cmp_mode,
5754                                               XEXP (x, 0), XEXP (x, 1));
5755       }
5756       break;
5757     case RTX_COMM_ARITH:
5758     case RTX_BIN_ARITH:
5759       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5760       break;
5761     case RTX_BITFIELD_OPS:
5762     case RTX_TERNARY:
5763       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5764                                          XEXP (x, 1), XEXP (x, 2));
5765       break;
5766     default:
5767       break;
5768     }
5769
5770   if (temp)
5771     {
5772       x = temp;
5773       code = GET_CODE (temp);
5774       op0_mode = VOIDmode;
5775       mode = GET_MODE (temp);
5776     }
5777
5778   /* If this is a simple operation applied to an IF_THEN_ELSE, try
5779      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
5780      things.  Check for cases where both arms are testing the same
5781      condition.
5782
5783      Don't do anything if all operands are very simple.  */
5784
5785   if ((BINARY_P (x)
5786        && ((!OBJECT_P (XEXP (x, 0))
5787             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5788                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5789            || (!OBJECT_P (XEXP (x, 1))
5790                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5791                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5792       || (UNARY_P (x)
5793           && (!OBJECT_P (XEXP (x, 0))
5794                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5795                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5796     {
5797       rtx cond, true_rtx, false_rtx;
5798
5799       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5800       if (cond != 0
5801           /* If everything is a comparison, what we have is highly unlikely
5802              to be simpler, so don't use it.  */
5803           && ! (COMPARISON_P (x)
5804                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx)))
5805           /* Similarly, if we end up with one of the expressions the same
5806              as the original, it is certainly not simpler.  */
5807           && ! rtx_equal_p (x, true_rtx)
5808           && ! rtx_equal_p (x, false_rtx))
5809         {
5810           rtx cop1 = const0_rtx;
5811           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5812
5813           if (cond_code == NE && COMPARISON_P (cond))
5814             return x;
5815
5816           /* Simplify the alternative arms; this may collapse the true and
5817              false arms to store-flag values.  Be careful to use copy_rtx
5818              here since true_rtx or false_rtx might share RTL with x as a
5819              result of the if_then_else_cond call above.  */
5820           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx,
5821                             false, false, false);
5822           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx,
5823                              false, false, false);
5824
5825           /* If true_rtx and false_rtx are not general_operands, an if_then_else
5826              is unlikely to be simpler.  */
5827           if (general_operand (true_rtx, VOIDmode)
5828               && general_operand (false_rtx, VOIDmode))
5829             {
5830               enum rtx_code reversed;
5831
5832               /* Restarting if we generate a store-flag expression will cause
5833                  us to loop.  Just drop through in this case.  */
5834
5835               /* If the result values are STORE_FLAG_VALUE and zero, we can
5836                  just make the comparison operation.  */
5837               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5838                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5839                                              cond, cop1);
5840               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5841                        && ((reversed = reversed_comparison_code_parts
5842                                         (cond_code, cond, cop1, NULL))
5843                            != UNKNOWN))
5844                 x = simplify_gen_relational (reversed, mode, VOIDmode,
5845                                              cond, cop1);
5846
5847               /* Likewise, we can make the negate of a comparison operation
5848                  if the result values are - STORE_FLAG_VALUE and zero.  */
5849               else if (CONST_INT_P (true_rtx)
5850                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5851                        && false_rtx == const0_rtx)
5852                 x = simplify_gen_unary (NEG, mode,
5853                                         simplify_gen_relational (cond_code,
5854                                                                  mode, VOIDmode,
5855                                                                  cond, cop1),
5856                                         mode);
5857               else if (CONST_INT_P (false_rtx)
5858                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5859                        && true_rtx == const0_rtx
5860                        && ((reversed = reversed_comparison_code_parts
5861                                         (cond_code, cond, cop1, NULL))
5862                            != UNKNOWN))
5863                 x = simplify_gen_unary (NEG, mode,
5864                                         simplify_gen_relational (reversed,
5865                                                                  mode, VOIDmode,
5866                                                                  cond, cop1),
5867                                         mode);
5868
5869               code = GET_CODE (x);
5870               op0_mode = VOIDmode;
5871             }
5872         }
5873     }
5874
5875   /* First see if we can apply the inverse distributive law.  */
5876   if (code == PLUS || code == MINUS
5877       || code == AND || code == IOR || code == XOR)
5878     {
5879       x = apply_distributive_law (x);
5880       code = GET_CODE (x);
5881       op0_mode = VOIDmode;
5882     }
5883
5884   /* If CODE is an associative operation not otherwise handled, see if we
5885      can associate some operands.  This can win if they are constants or
5886      if they are logically related (i.e. (a & b) & a).  */
5887   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5888        || code == AND || code == IOR || code == XOR
5889        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5890       && ((INTEGRAL_MODE_P (mode) && code != DIV)
5891           || (flag_associative_math && FLOAT_MODE_P (mode))))
5892     {
5893       if (GET_CODE (XEXP (x, 0)) == code)
5894         {
5895           rtx other = XEXP (XEXP (x, 0), 0);
5896           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5897           rtx inner_op1 = XEXP (x, 1);
5898           rtx inner;
5899
5900           /* Make sure we pass the constant operand if any as the second
5901              one if this is a commutative operation.  */
5902           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5903             std::swap (inner_op0, inner_op1);
5904           inner = simplify_binary_operation (code == MINUS ? PLUS
5905                                              : code == DIV ? MULT
5906                                              : code,
5907                                              mode, inner_op0, inner_op1);
5908
5909           /* For commutative operations, try the other pair if that one
5910              didn't simplify.  */
5911           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5912             {
5913               other = XEXP (XEXP (x, 0), 1);
5914               inner = simplify_binary_operation (code, mode,
5915                                                  XEXP (XEXP (x, 0), 0),
5916                                                  XEXP (x, 1));
5917             }
5918
5919           if (inner)
5920             return simplify_gen_binary (code, mode, other, inner);
5921         }
5922     }
5923
5924   /* A little bit of algebraic simplification here.  */
5925   switch (code)
5926     {
5927     case MEM:
5928       /* Ensure that our address has any ASHIFTs converted to MULT in case
5929          address-recognizing predicates are called later.  */
5930       temp = make_compound_operation (XEXP (x, 0), MEM);
5931       SUBST (XEXP (x, 0), temp);
5932       break;
5933
5934     case SUBREG:
5935       if (op0_mode == VOIDmode)
5936         op0_mode = GET_MODE (SUBREG_REG (x));
5937
5938       /* See if this can be moved to simplify_subreg.  */
5939       if (CONSTANT_P (SUBREG_REG (x))
5940           && known_eq (subreg_lowpart_offset (mode, op0_mode), SUBREG_BYTE (x))
5941              /* Don't call gen_lowpart if the inner mode
5942                 is VOIDmode and we cannot simplify it, as SUBREG without
5943                 inner mode is invalid.  */
5944           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5945               || gen_lowpart_common (mode, SUBREG_REG (x))))
5946         return gen_lowpart (mode, SUBREG_REG (x));
5947
5948       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5949         break;
5950       {
5951         rtx temp;
5952         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5953                                 SUBREG_BYTE (x));
5954         if (temp)
5955           return temp;
5956
5957         /* If op is known to have all lower bits zero, the result is zero.  */
5958         scalar_int_mode int_mode, int_op0_mode;
5959         if (!in_dest
5960             && is_a <scalar_int_mode> (mode, &int_mode)
5961             && is_a <scalar_int_mode> (op0_mode, &int_op0_mode)
5962             && (GET_MODE_PRECISION (int_mode)
5963                 < GET_MODE_PRECISION (int_op0_mode))
5964             && known_eq (subreg_lowpart_offset (int_mode, int_op0_mode),
5965                          SUBREG_BYTE (x))
5966             && HWI_COMPUTABLE_MODE_P (int_op0_mode)
5967             && ((nonzero_bits (SUBREG_REG (x), int_op0_mode)
5968                  & GET_MODE_MASK (int_mode)) == 0)
5969             && !side_effects_p (SUBREG_REG (x)))
5970           return CONST0_RTX (int_mode);
5971       }
5972
5973       /* Don't change the mode of the MEM if that would change the meaning
5974          of the address.  */
5975       if (MEM_P (SUBREG_REG (x))
5976           && (MEM_VOLATILE_P (SUBREG_REG (x))
5977               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0),
5978                                            MEM_ADDR_SPACE (SUBREG_REG (x)))))
5979         return gen_rtx_CLOBBER (mode, const0_rtx);
5980
5981       /* Note that we cannot do any narrowing for non-constants since
5982          we might have been counting on using the fact that some bits were
5983          zero.  We now do this in the SET.  */
5984
5985       break;
5986
5987     case NEG:
5988       temp = expand_compound_operation (XEXP (x, 0));
5989
5990       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5991          replaced by (lshiftrt X C).  This will convert
5992          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
5993
5994       if (GET_CODE (temp) == ASHIFTRT
5995           && CONST_INT_P (XEXP (temp, 1))
5996           && INTVAL (XEXP (temp, 1)) == GET_MODE_UNIT_PRECISION (mode) - 1)
5997         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5998                                      INTVAL (XEXP (temp, 1)));
5999
6000       /* If X has only a single bit that might be nonzero, say, bit I, convert
6001          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
6002          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
6003          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
6004          or a SUBREG of one since we'd be making the expression more
6005          complex if it was just a register.  */
6006
6007       if (!REG_P (temp)
6008           && ! (GET_CODE (temp) == SUBREG
6009                 && REG_P (SUBREG_REG (temp)))
6010           && is_a <scalar_int_mode> (mode, &int_mode)
6011           && (i = exact_log2 (nonzero_bits (temp, int_mode))) >= 0)
6012         {
6013           rtx temp1 = simplify_shift_const
6014             (NULL_RTX, ASHIFTRT, int_mode,
6015              simplify_shift_const (NULL_RTX, ASHIFT, int_mode, temp,
6016                                    GET_MODE_PRECISION (int_mode) - 1 - i),
6017              GET_MODE_PRECISION (int_mode) - 1 - i);
6018
6019           /* If all we did was surround TEMP with the two shifts, we
6020              haven't improved anything, so don't use it.  Otherwise,
6021              we are better off with TEMP1.  */
6022           if (GET_CODE (temp1) != ASHIFTRT
6023               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
6024               || XEXP (XEXP (temp1, 0), 0) != temp)
6025             return temp1;
6026         }
6027       break;
6028
6029     case TRUNCATE:
6030       /* We can't handle truncation to a partial integer mode here
6031          because we don't know the real bitsize of the partial
6032          integer mode.  */
6033       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
6034         break;
6035
6036       if (HWI_COMPUTABLE_MODE_P (mode))
6037         SUBST (XEXP (x, 0),
6038                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
6039                               GET_MODE_MASK (mode), false));
6040
6041       /* We can truncate a constant value and return it.  */
6042       {
6043         poly_int64 c;
6044         if (poly_int_rtx_p (XEXP (x, 0), &c))
6045           return gen_int_mode (c, mode);
6046       }
6047
6048       /* Similarly to what we do in simplify-rtx.cc, a truncate of a register
6049          whose value is a comparison can be replaced with a subreg if
6050          STORE_FLAG_VALUE permits.  */
6051       if (HWI_COMPUTABLE_MODE_P (mode)
6052           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
6053           && (temp = get_last_value (XEXP (x, 0)))
6054           && COMPARISON_P (temp)
6055           && TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (XEXP (x, 0))))
6056         return gen_lowpart (mode, XEXP (x, 0));
6057       break;
6058
6059     case CONST:
6060       /* (const (const X)) can become (const X).  Do it this way rather than
6061          returning the inner CONST since CONST can be shared with a
6062          REG_EQUAL note.  */
6063       if (GET_CODE (XEXP (x, 0)) == CONST)
6064         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
6065       break;
6066
6067     case LO_SUM:
6068       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
6069          can add in an offset.  find_split_point will split this address up
6070          again if it doesn't match.  */
6071       if (HAVE_lo_sum && GET_CODE (XEXP (x, 0)) == HIGH
6072           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
6073         return XEXP (x, 1);
6074       break;
6075
6076     case PLUS:
6077       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6078          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6079          bit-field and can be replaced by either a sign_extend or a
6080          sign_extract.  The `and' may be a zero_extend and the two
6081          <c>, -<c> constants may be reversed.  */
6082       if (GET_CODE (XEXP (x, 0)) == XOR
6083           && is_a <scalar_int_mode> (mode, &int_mode)
6084           && CONST_INT_P (XEXP (x, 1))
6085           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
6086           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
6087           && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
6088               || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
6089           && HWI_COMPUTABLE_MODE_P (int_mode)
6090           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
6091                && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
6092                && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
6093                    == (HOST_WIDE_INT_1U << (i + 1)) - 1))
6094               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
6095                   && known_eq ((GET_MODE_PRECISION
6096                                 (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))),
6097                                (unsigned int) i + 1))))
6098         return simplify_shift_const
6099           (NULL_RTX, ASHIFTRT, int_mode,
6100            simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6101                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
6102                                  GET_MODE_PRECISION (int_mode) - (i + 1)),
6103            GET_MODE_PRECISION (int_mode) - (i + 1));
6104
6105       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6106          can become (ashiftrt (ashift (xor x 1) C) C) where C is
6107          the bitsize of the mode - 1.  This allows simplification of
6108          "a = (b & 8) == 0;"  */
6109       if (XEXP (x, 1) == constm1_rtx
6110           && !REG_P (XEXP (x, 0))
6111           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
6112                 && REG_P (SUBREG_REG (XEXP (x, 0))))
6113           && is_a <scalar_int_mode> (mode, &int_mode)
6114           && nonzero_bits (XEXP (x, 0), int_mode) == 1)
6115         return simplify_shift_const
6116           (NULL_RTX, ASHIFTRT, int_mode,
6117            simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6118                                  gen_rtx_XOR (int_mode, XEXP (x, 0),
6119                                               const1_rtx),
6120                                  GET_MODE_PRECISION (int_mode) - 1),
6121            GET_MODE_PRECISION (int_mode) - 1);
6122
6123       /* If we are adding two things that have no bits in common, convert
6124          the addition into an IOR.  This will often be further simplified,
6125          for example in cases like ((a & 1) + (a & 2)), which can
6126          become a & 3.  */
6127
6128       if (HWI_COMPUTABLE_MODE_P (mode)
6129           && (nonzero_bits (XEXP (x, 0), mode)
6130               & nonzero_bits (XEXP (x, 1), mode)) == 0)
6131         {
6132           /* Try to simplify the expression further.  */
6133           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
6134           temp = combine_simplify_rtx (tor, VOIDmode, in_dest, false);
6135
6136           /* If we could, great.  If not, do not go ahead with the IOR
6137              replacement, since PLUS appears in many special purpose
6138              address arithmetic instructions.  */
6139           if (GET_CODE (temp) != CLOBBER
6140               && (GET_CODE (temp) != IOR
6141                   || ((XEXP (temp, 0) != XEXP (x, 0)
6142                        || XEXP (temp, 1) != XEXP (x, 1))
6143                       && (XEXP (temp, 0) != XEXP (x, 1)
6144                           || XEXP (temp, 1) != XEXP (x, 0)))))
6145             return temp;
6146         }
6147
6148       /* Canonicalize x + x into x << 1.  */
6149       if (GET_MODE_CLASS (mode) == MODE_INT
6150           && rtx_equal_p (XEXP (x, 0), XEXP (x, 1))
6151           && !side_effects_p (XEXP (x, 0)))
6152         return simplify_gen_binary (ASHIFT, mode, XEXP (x, 0), const1_rtx);
6153
6154       break;
6155
6156     case MINUS:
6157       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6158          (and <foo> (const_int pow2-1))  */
6159       if (is_a <scalar_int_mode> (mode, &int_mode)
6160           && GET_CODE (XEXP (x, 1)) == AND
6161           && CONST_INT_P (XEXP (XEXP (x, 1), 1))
6162           && pow2p_hwi (-UINTVAL (XEXP (XEXP (x, 1), 1)))
6163           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
6164         return simplify_and_const_int (NULL_RTX, int_mode, XEXP (x, 0),
6165                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
6166       break;
6167
6168     case MULT:
6169       /* If we have (mult (plus A B) C), apply the distributive law and then
6170          the inverse distributive law to see if things simplify.  This
6171          occurs mostly in addresses, often when unrolling loops.  */
6172
6173       if (GET_CODE (XEXP (x, 0)) == PLUS)
6174         {
6175           rtx result = distribute_and_simplify_rtx (x, 0);
6176           if (result)
6177             return result;
6178         }
6179
6180       /* Try simplify a*(b/c) as (a*b)/c.  */
6181       if (FLOAT_MODE_P (mode) && flag_associative_math
6182           && GET_CODE (XEXP (x, 0)) == DIV)
6183         {
6184           rtx tem = simplify_binary_operation (MULT, mode,
6185                                                XEXP (XEXP (x, 0), 0),
6186                                                XEXP (x, 1));
6187           if (tem)
6188             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
6189         }
6190       break;
6191
6192     case UDIV:
6193       /* If this is a divide by a power of two, treat it as a shift if
6194          its first operand is a shift.  */
6195       if (is_a <scalar_int_mode> (mode, &int_mode)
6196           && CONST_INT_P (XEXP (x, 1))
6197           && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
6198           && (GET_CODE (XEXP (x, 0)) == ASHIFT
6199               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
6200               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
6201               || GET_CODE (XEXP (x, 0)) == ROTATE
6202               || GET_CODE (XEXP (x, 0)) == ROTATERT))
6203         return simplify_shift_const (NULL_RTX, LSHIFTRT, int_mode,
6204                                      XEXP (x, 0), i);
6205       break;
6206
6207     case EQ:  case NE:
6208     case GT:  case GTU:  case GE:  case GEU:
6209     case LT:  case LTU:  case LE:  case LEU:
6210     case UNEQ:  case LTGT:
6211     case UNGT:  case UNGE:
6212     case UNLT:  case UNLE:
6213     case UNORDERED: case ORDERED:
6214       /* If the first operand is a condition code, we can't do anything
6215          with it.  */
6216       if (GET_CODE (XEXP (x, 0)) == COMPARE
6217           || GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC)
6218         {
6219           rtx op0 = XEXP (x, 0);
6220           rtx op1 = XEXP (x, 1);
6221           enum rtx_code new_code;
6222
6223           if (GET_CODE (op0) == COMPARE)
6224             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
6225
6226           /* Simplify our comparison, if possible.  */
6227           new_code = simplify_comparison (code, &op0, &op1);
6228
6229           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6230              if only the low-order bit is possibly nonzero in X (such as when
6231              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
6232              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
6233              known to be either 0 or -1, NE becomes a NEG and EQ becomes
6234              (plus X 1).
6235
6236              Remove any ZERO_EXTRACT we made when thinking this was a
6237              comparison.  It may now be simpler to use, e.g., an AND.  If a
6238              ZERO_EXTRACT is indeed appropriate, it will be placed back by
6239              the call to make_compound_operation in the SET case.
6240
6241              Don't apply these optimizations if the caller would
6242              prefer a comparison rather than a value.
6243              E.g., for the condition in an IF_THEN_ELSE most targets need
6244              an explicit comparison.  */
6245
6246           if (in_cond)
6247             ;
6248
6249           else if (STORE_FLAG_VALUE == 1
6250                    && new_code == NE
6251                    && is_int_mode (mode, &int_mode)
6252                    && op1 == const0_rtx
6253                    && int_mode == GET_MODE (op0)
6254                    && nonzero_bits (op0, int_mode) == 1)
6255             return gen_lowpart (int_mode,
6256                                 expand_compound_operation (op0));
6257
6258           else if (STORE_FLAG_VALUE == 1
6259                    && new_code == NE
6260                    && is_int_mode (mode, &int_mode)
6261                    && op1 == const0_rtx
6262                    && int_mode == GET_MODE (op0)
6263                    && (num_sign_bit_copies (op0, int_mode)
6264                        == GET_MODE_PRECISION (int_mode)))
6265             {
6266               op0 = expand_compound_operation (op0);
6267               return simplify_gen_unary (NEG, int_mode,
6268                                          gen_lowpart (int_mode, op0),
6269                                          int_mode);
6270             }
6271
6272           else if (STORE_FLAG_VALUE == 1
6273                    && new_code == EQ
6274                    && is_int_mode (mode, &int_mode)
6275                    && op1 == const0_rtx
6276                    && int_mode == GET_MODE (op0)
6277                    && nonzero_bits (op0, int_mode) == 1)
6278             {
6279               op0 = expand_compound_operation (op0);
6280               return simplify_gen_binary (XOR, int_mode,
6281                                           gen_lowpart (int_mode, op0),
6282                                           const1_rtx);
6283             }
6284
6285           else if (STORE_FLAG_VALUE == 1
6286                    && new_code == EQ
6287                    && is_int_mode (mode, &int_mode)
6288                    && op1 == const0_rtx
6289                    && int_mode == GET_MODE (op0)
6290                    && (num_sign_bit_copies (op0, int_mode)
6291                        == GET_MODE_PRECISION (int_mode)))
6292             {
6293               op0 = expand_compound_operation (op0);
6294               return plus_constant (int_mode, gen_lowpart (int_mode, op0), 1);
6295             }
6296
6297           /* If STORE_FLAG_VALUE is -1, we have cases similar to
6298              those above.  */
6299           if (in_cond)
6300             ;
6301
6302           else if (STORE_FLAG_VALUE == -1
6303                    && new_code == NE
6304                    && is_int_mode (mode, &int_mode)
6305                    && op1 == const0_rtx
6306                    && int_mode == GET_MODE (op0)
6307                    && (num_sign_bit_copies (op0, int_mode)
6308                        == GET_MODE_PRECISION (int_mode)))
6309             return gen_lowpart (int_mode, expand_compound_operation (op0));
6310
6311           else if (STORE_FLAG_VALUE == -1
6312                    && new_code == NE
6313                    && is_int_mode (mode, &int_mode)
6314                    && op1 == const0_rtx
6315                    && int_mode == GET_MODE (op0)
6316                    && nonzero_bits (op0, int_mode) == 1)
6317             {
6318               op0 = expand_compound_operation (op0);
6319               return simplify_gen_unary (NEG, int_mode,
6320                                          gen_lowpart (int_mode, op0),
6321                                          int_mode);
6322             }
6323
6324           else if (STORE_FLAG_VALUE == -1
6325                    && new_code == EQ
6326                    && is_int_mode (mode, &int_mode)
6327                    && op1 == const0_rtx
6328                    && int_mode == GET_MODE (op0)
6329                    && (num_sign_bit_copies (op0, int_mode)
6330                        == GET_MODE_PRECISION (int_mode)))
6331             {
6332               op0 = expand_compound_operation (op0);
6333               return simplify_gen_unary (NOT, int_mode,
6334                                          gen_lowpart (int_mode, op0),
6335                                          int_mode);
6336             }
6337
6338           /* If X is 0/1, (eq X 0) is X-1.  */
6339           else if (STORE_FLAG_VALUE == -1
6340                    && new_code == EQ
6341                    && is_int_mode (mode, &int_mode)
6342                    && op1 == const0_rtx
6343                    && int_mode == GET_MODE (op0)
6344                    && nonzero_bits (op0, int_mode) == 1)
6345             {
6346               op0 = expand_compound_operation (op0);
6347               return plus_constant (int_mode, gen_lowpart (int_mode, op0), -1);
6348             }
6349
6350           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6351              one bit that might be nonzero, we can convert (ne x 0) to
6352              (ashift x c) where C puts the bit in the sign bit.  Remove any
6353              AND with STORE_FLAG_VALUE when we are done, since we are only
6354              going to test the sign bit.  */
6355           if (new_code == NE
6356               && is_int_mode (mode, &int_mode)
6357               && HWI_COMPUTABLE_MODE_P (int_mode)
6358               && val_signbit_p (int_mode, STORE_FLAG_VALUE)
6359               && op1 == const0_rtx
6360               && int_mode == GET_MODE (op0)
6361               && (i = exact_log2 (nonzero_bits (op0, int_mode))) >= 0)
6362             {
6363               x = simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6364                                         expand_compound_operation (op0),
6365                                         GET_MODE_PRECISION (int_mode) - 1 - i);
6366               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
6367                 return XEXP (x, 0);
6368               else
6369                 return x;
6370             }
6371
6372           /* If the code changed, return a whole new comparison.
6373              We also need to avoid using SUBST in cases where
6374              simplify_comparison has widened a comparison with a CONST_INT,
6375              since in that case the wider CONST_INT may fail the sanity
6376              checks in do_SUBST.  */
6377           if (new_code != code
6378               || (CONST_INT_P (op1)
6379                   && GET_MODE (op0) != GET_MODE (XEXP (x, 0))
6380                   && GET_MODE (op0) != GET_MODE (XEXP (x, 1))))
6381             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
6382
6383           /* Otherwise, keep this operation, but maybe change its operands.
6384              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
6385           SUBST (XEXP (x, 0), op0);
6386           SUBST (XEXP (x, 1), op1);
6387         }
6388       break;
6389
6390     case IF_THEN_ELSE:
6391       return simplify_if_then_else (x);
6392
6393     case ZERO_EXTRACT:
6394     case SIGN_EXTRACT:
6395     case ZERO_EXTEND:
6396     case SIGN_EXTEND:
6397       /* If we are processing SET_DEST, we are done.  */
6398       if (in_dest)
6399         return x;
6400
6401       return expand_compound_operation (x);
6402
6403     case SET:
6404       return simplify_set (x);
6405
6406     case AND:
6407     case IOR:
6408       return simplify_logical (x);
6409
6410     case ASHIFT:
6411     case LSHIFTRT:
6412     case ASHIFTRT:
6413     case ROTATE:
6414     case ROTATERT:
6415       /* If this is a shift by a constant amount, simplify it.  */
6416       if (CONST_INT_P (XEXP (x, 1)))
6417         return simplify_shift_const (x, code, mode, XEXP (x, 0),
6418                                      INTVAL (XEXP (x, 1)));
6419
6420       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
6421         SUBST (XEXP (x, 1),
6422                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
6423                               (HOST_WIDE_INT_1U
6424                                << exact_log2 (GET_MODE_UNIT_BITSIZE
6425                                               (GET_MODE (x)))) - 1, false));
6426       break;
6427     case VEC_SELECT:
6428       {
6429         rtx trueop0 = XEXP (x, 0);
6430         mode = GET_MODE (trueop0);
6431         rtx trueop1 = XEXP (x, 1);
6432         /* If we select a low-part subreg, return that.  */
6433         if (vec_series_lowpart_p (GET_MODE (x), mode, trueop1))
6434           {
6435             rtx new_rtx = lowpart_subreg (GET_MODE (x), trueop0, mode);
6436             if (new_rtx != NULL_RTX)
6437               return new_rtx;
6438           }
6439       }
6440
6441     default:
6442       break;
6443     }
6444
6445   return x;
6446 }
6447 \f
6448 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
6449
6450 static rtx
6451 simplify_if_then_else (rtx x)
6452 {
6453   machine_mode mode = GET_MODE (x);
6454   rtx cond = XEXP (x, 0);
6455   rtx true_rtx = XEXP (x, 1);
6456   rtx false_rtx = XEXP (x, 2);
6457   enum rtx_code true_code = GET_CODE (cond);
6458   bool comparison_p = COMPARISON_P (cond);
6459   rtx temp;
6460   int i;
6461   enum rtx_code false_code;
6462   rtx reversed;
6463   scalar_int_mode int_mode, inner_mode;
6464
6465   /* Simplify storing of the truth value.  */
6466   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
6467     return simplify_gen_relational (true_code, mode, VOIDmode,
6468                                     XEXP (cond, 0), XEXP (cond, 1));
6469
6470   /* Also when the truth value has to be reversed.  */
6471   if (comparison_p
6472       && true_rtx == const0_rtx && false_rtx == const_true_rtx
6473       && (reversed = reversed_comparison (cond, mode)))
6474     return reversed;
6475
6476   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6477      in it is being compared against certain values.  Get the true and false
6478      comparisons and see if that says anything about the value of each arm.  */
6479
6480   if (comparison_p
6481       && ((false_code = reversed_comparison_code (cond, NULL))
6482           != UNKNOWN)
6483       && REG_P (XEXP (cond, 0)))
6484     {
6485       HOST_WIDE_INT nzb;
6486       rtx from = XEXP (cond, 0);
6487       rtx true_val = XEXP (cond, 1);
6488       rtx false_val = true_val;
6489       bool swapped = false;
6490
6491       /* If FALSE_CODE is EQ, swap the codes and arms.  */
6492
6493       if (false_code == EQ)
6494         {
6495           swapped = true, true_code = EQ, false_code = NE;
6496           std::swap (true_rtx, false_rtx);
6497         }
6498
6499       scalar_int_mode from_mode;
6500       if (is_a <scalar_int_mode> (GET_MODE (from), &from_mode))
6501         {
6502           /* If we are comparing against zero and the expression being
6503              tested has only a single bit that might be nonzero, that is
6504              its value when it is not equal to zero.  Similarly if it is
6505              known to be -1 or 0.  */
6506           if (true_code == EQ
6507               && true_val == const0_rtx
6508               && pow2p_hwi (nzb = nonzero_bits (from, from_mode)))
6509             {
6510               false_code = EQ;
6511               false_val = gen_int_mode (nzb, from_mode);
6512             }
6513           else if (true_code == EQ
6514                    && true_val == const0_rtx
6515                    && (num_sign_bit_copies (from, from_mode)
6516                        == GET_MODE_PRECISION (from_mode)))
6517             {
6518               false_code = EQ;
6519               false_val = constm1_rtx;
6520             }
6521         }
6522
6523       /* Now simplify an arm if we know the value of the register in the
6524          branch and it is used in the arm.  Be careful due to the potential
6525          of locally-shared RTL.  */
6526
6527       if (reg_mentioned_p (from, true_rtx))
6528         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
6529                                       from, true_val),
6530                           pc_rtx, pc_rtx, false, false, false);
6531       if (reg_mentioned_p (from, false_rtx))
6532         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
6533                                        from, false_val),
6534                            pc_rtx, pc_rtx, false, false, false);
6535
6536       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
6537       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
6538
6539       true_rtx = XEXP (x, 1);
6540       false_rtx = XEXP (x, 2);
6541       true_code = GET_CODE (cond);
6542     }
6543
6544   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6545      reversed, do so to avoid needing two sets of patterns for
6546      subtract-and-branch insns.  Similarly if we have a constant in the true
6547      arm, the false arm is the same as the first operand of the comparison, or
6548      the false arm is more complicated than the true arm.  */
6549
6550   if (comparison_p
6551       && reversed_comparison_code (cond, NULL) != UNKNOWN
6552       && (true_rtx == pc_rtx
6553           || (CONSTANT_P (true_rtx)
6554               && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
6555           || true_rtx == const0_rtx
6556           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6557           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6558               && !OBJECT_P (false_rtx))
6559           || reg_mentioned_p (true_rtx, false_rtx)
6560           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
6561     {
6562       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6563       SUBST (XEXP (x, 1), false_rtx);
6564       SUBST (XEXP (x, 2), true_rtx);
6565
6566       std::swap (true_rtx, false_rtx);
6567       cond = XEXP (x, 0);
6568
6569       /* It is possible that the conditional has been simplified out.  */
6570       true_code = GET_CODE (cond);
6571       comparison_p = COMPARISON_P (cond);
6572     }
6573
6574   /* If the two arms are identical, we don't need the comparison.  */
6575
6576   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6577     return true_rtx;
6578
6579   /* Convert a == b ? b : a to "a".  */
6580   if (true_code == EQ && ! side_effects_p (cond)
6581       && !HONOR_NANS (mode)
6582       && rtx_equal_p (XEXP (cond, 0), false_rtx)
6583       && rtx_equal_p (XEXP (cond, 1), true_rtx))
6584     return false_rtx;
6585   else if (true_code == NE && ! side_effects_p (cond)
6586            && !HONOR_NANS (mode)
6587            && rtx_equal_p (XEXP (cond, 0), true_rtx)
6588            && rtx_equal_p (XEXP (cond, 1), false_rtx))
6589     return true_rtx;
6590
6591   /* Look for cases where we have (abs x) or (neg (abs X)).  */
6592
6593   if (GET_MODE_CLASS (mode) == MODE_INT
6594       && comparison_p
6595       && XEXP (cond, 1) == const0_rtx
6596       && GET_CODE (false_rtx) == NEG
6597       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6598       && rtx_equal_p (true_rtx, XEXP (cond, 0))
6599       && ! side_effects_p (true_rtx))
6600     switch (true_code)
6601       {
6602       case GT:
6603       case GE:
6604         return simplify_gen_unary (ABS, mode, true_rtx, mode);
6605       case LT:
6606       case LE:
6607         return
6608           simplify_gen_unary (NEG, mode,
6609                               simplify_gen_unary (ABS, mode, true_rtx, mode),
6610                               mode);
6611       default:
6612         break;
6613       }
6614
6615   /* Look for MIN or MAX.  */
6616
6617   if ((! FLOAT_MODE_P (mode)
6618        || (flag_unsafe_math_optimizations
6619            && !HONOR_NANS (mode)
6620            && !HONOR_SIGNED_ZEROS (mode)))
6621       && comparison_p
6622       && rtx_equal_p (XEXP (cond, 0), true_rtx)
6623       && rtx_equal_p (XEXP (cond, 1), false_rtx)
6624       && ! side_effects_p (cond))
6625     switch (true_code)
6626       {
6627       case GE:
6628       case GT:
6629         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6630       case LE:
6631       case LT:
6632         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6633       case GEU:
6634       case GTU:
6635         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6636       case LEU:
6637       case LTU:
6638         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6639       default:
6640         break;
6641       }
6642
6643   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6644      second operand is zero, this can be done as (OP Z (mult COND C2)) where
6645      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6646      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6647      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6648      neither 1 or -1, but it isn't worth checking for.  */
6649
6650   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6651       && comparison_p
6652       && is_int_mode (mode, &int_mode)
6653       && ! side_effects_p (x))
6654     {
6655       rtx t = make_compound_operation (true_rtx, SET);
6656       rtx f = make_compound_operation (false_rtx, SET);
6657       rtx cond_op0 = XEXP (cond, 0);
6658       rtx cond_op1 = XEXP (cond, 1);
6659       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6660       scalar_int_mode m = int_mode;
6661       rtx z = 0, c1 = NULL_RTX;
6662
6663       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6664            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6665            || GET_CODE (t) == ASHIFT
6666            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6667           && rtx_equal_p (XEXP (t, 0), f))
6668         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6669
6670       /* If an identity-zero op is commutative, check whether there
6671          would be a match if we swapped the operands.  */
6672       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6673                 || GET_CODE (t) == XOR)
6674                && rtx_equal_p (XEXP (t, 1), f))
6675         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6676       else if (GET_CODE (t) == SIGN_EXTEND
6677                && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6678                && (GET_CODE (XEXP (t, 0)) == PLUS
6679                    || GET_CODE (XEXP (t, 0)) == MINUS
6680                    || GET_CODE (XEXP (t, 0)) == IOR
6681                    || GET_CODE (XEXP (t, 0)) == XOR
6682                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6683                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6684                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6685                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6686                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6687                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6688                && (num_sign_bit_copies (f, GET_MODE (f))
6689                    > (unsigned int)
6690                      (GET_MODE_PRECISION (int_mode)
6691                       - GET_MODE_PRECISION (inner_mode))))
6692         {
6693           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6694           extend_op = SIGN_EXTEND;
6695           m = inner_mode;
6696         }
6697       else if (GET_CODE (t) == SIGN_EXTEND
6698                && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6699                && (GET_CODE (XEXP (t, 0)) == PLUS
6700                    || GET_CODE (XEXP (t, 0)) == IOR
6701                    || GET_CODE (XEXP (t, 0)) == XOR)
6702                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6703                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6704                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6705                && (num_sign_bit_copies (f, GET_MODE (f))
6706                    > (unsigned int)
6707                      (GET_MODE_PRECISION (int_mode)
6708                       - GET_MODE_PRECISION (inner_mode))))
6709         {
6710           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6711           extend_op = SIGN_EXTEND;
6712           m = inner_mode;
6713         }
6714       else if (GET_CODE (t) == ZERO_EXTEND
6715                && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6716                && (GET_CODE (XEXP (t, 0)) == PLUS
6717                    || GET_CODE (XEXP (t, 0)) == MINUS
6718                    || GET_CODE (XEXP (t, 0)) == IOR
6719                    || GET_CODE (XEXP (t, 0)) == XOR
6720                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6721                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6722                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6723                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6724                && HWI_COMPUTABLE_MODE_P (int_mode)
6725                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6726                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6727                && ((nonzero_bits (f, GET_MODE (f))
6728                     & ~GET_MODE_MASK (inner_mode))
6729                    == 0))
6730         {
6731           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6732           extend_op = ZERO_EXTEND;
6733           m = inner_mode;
6734         }
6735       else if (GET_CODE (t) == ZERO_EXTEND
6736                && is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), &inner_mode)
6737                && (GET_CODE (XEXP (t, 0)) == PLUS
6738                    || GET_CODE (XEXP (t, 0)) == IOR
6739                    || GET_CODE (XEXP (t, 0)) == XOR)
6740                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6741                && HWI_COMPUTABLE_MODE_P (int_mode)
6742                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6743                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6744                && ((nonzero_bits (f, GET_MODE (f))
6745                     & ~GET_MODE_MASK (inner_mode))
6746                    == 0))
6747         {
6748           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6749           extend_op = ZERO_EXTEND;
6750           m = inner_mode;
6751         }
6752
6753       if (z)
6754         {
6755           machine_mode cm = m;
6756           if ((op == ASHIFT || op == LSHIFTRT || op == ASHIFTRT)
6757               && GET_MODE (c1) != VOIDmode)
6758             cm = GET_MODE (c1);
6759           temp = subst (simplify_gen_relational (true_code, cm, VOIDmode,
6760                                                  cond_op0, cond_op1),
6761                         pc_rtx, pc_rtx, false, false, false);
6762           temp = simplify_gen_binary (MULT, cm, temp,
6763                                       simplify_gen_binary (MULT, cm, c1,
6764                                                            const_true_rtx));
6765           temp = subst (temp, pc_rtx, pc_rtx, false, false, false);
6766           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6767
6768           if (extend_op != UNKNOWN)
6769             temp = simplify_gen_unary (extend_op, int_mode, temp, m);
6770
6771           return temp;
6772         }
6773     }
6774
6775   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6776      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6777      negation of a single bit, we can convert this operation to a shift.  We
6778      can actually do this more generally, but it doesn't seem worth it.  */
6779
6780   if (true_code == NE
6781       && is_a <scalar_int_mode> (mode, &int_mode)
6782       && XEXP (cond, 1) == const0_rtx
6783       && false_rtx == const0_rtx
6784       && CONST_INT_P (true_rtx)
6785       && ((nonzero_bits (XEXP (cond, 0), int_mode) == 1
6786            && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6787           || ((num_sign_bit_copies (XEXP (cond, 0), int_mode)
6788                == GET_MODE_PRECISION (int_mode))
6789               && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6790     return
6791       simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6792                             gen_lowpart (int_mode, XEXP (cond, 0)), i);
6793
6794   /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6795      non-zero bit in A is C1.  */
6796   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6797       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6798       && is_a <scalar_int_mode> (mode, &int_mode)
6799       && is_a <scalar_int_mode> (GET_MODE (XEXP (cond, 0)), &inner_mode)
6800       && (UINTVAL (true_rtx) & GET_MODE_MASK (int_mode))
6801           == nonzero_bits (XEXP (cond, 0), inner_mode)
6802       && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (int_mode))) >= 0)
6803     {
6804       rtx val = XEXP (cond, 0);
6805       if (inner_mode == int_mode)
6806         return val;
6807       else if (GET_MODE_PRECISION (inner_mode) < GET_MODE_PRECISION (int_mode))
6808         return simplify_gen_unary (ZERO_EXTEND, int_mode, val, inner_mode);
6809     }
6810
6811   return x;
6812 }
6813 \f
6814 /* Simplify X, a SET expression.  Return the new expression.  */
6815
6816 static rtx
6817 simplify_set (rtx x)
6818 {
6819   rtx src = SET_SRC (x);
6820   rtx dest = SET_DEST (x);
6821   machine_mode mode
6822     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6823   rtx_insn *other_insn;
6824   rtx *cc_use;
6825   scalar_int_mode int_mode;
6826
6827   /* (set (pc) (return)) gets written as (return).  */
6828   if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6829     return src;
6830
6831   /* Now that we know for sure which bits of SRC we are using, see if we can
6832      simplify the expression for the object knowing that we only need the
6833      low-order bits.  */
6834
6835   if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6836     {
6837       src = force_to_mode (src, mode, HOST_WIDE_INT_M1U, false);
6838       SUBST (SET_SRC (x), src);
6839     }
6840
6841   /* If the source is a COMPARE, look for the use of the comparison result
6842      and try to simplify it unless we already have used undobuf.other_insn.  */
6843   if ((GET_MODE_CLASS (mode) == MODE_CC || GET_CODE (src) == COMPARE)
6844       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6845       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6846       && COMPARISON_P (*cc_use)
6847       && rtx_equal_p (XEXP (*cc_use, 0), dest))
6848     {
6849       enum rtx_code old_code = GET_CODE (*cc_use);
6850       enum rtx_code new_code;
6851       rtx op0, op1, tmp;
6852       bool other_changed = false;
6853       rtx inner_compare = NULL_RTX;
6854       machine_mode compare_mode = GET_MODE (dest);
6855
6856       if (GET_CODE (src) == COMPARE)
6857         {
6858           op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6859           if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6860             {
6861               inner_compare = op0;
6862               op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6863             }
6864         }
6865       else
6866         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6867
6868       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6869                                            op0, op1);
6870       if (!tmp)
6871         new_code = old_code;
6872       else if (!CONSTANT_P (tmp))
6873         {
6874           new_code = GET_CODE (tmp);
6875           op0 = XEXP (tmp, 0);
6876           op1 = XEXP (tmp, 1);
6877         }
6878       else
6879         {
6880           rtx pat = PATTERN (other_insn);
6881           undobuf.other_insn = other_insn;
6882           SUBST (*cc_use, tmp);
6883
6884           /* Attempt to simplify CC user.  */
6885           if (GET_CODE (pat) == SET)
6886             {
6887               rtx new_rtx = simplify_rtx (SET_SRC (pat));
6888               if (new_rtx != NULL_RTX)
6889                 SUBST (SET_SRC (pat), new_rtx);
6890             }
6891
6892           /* Convert X into a no-op move.  */
6893           SUBST (SET_DEST (x), pc_rtx);
6894           SUBST (SET_SRC (x), pc_rtx);
6895           return x;
6896         }
6897
6898       /* Simplify our comparison, if possible.  */
6899       new_code = simplify_comparison (new_code, &op0, &op1);
6900
6901 #ifdef SELECT_CC_MODE
6902       /* If this machine has CC modes other than CCmode, check to see if we
6903          need to use a different CC mode here.  */
6904       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6905         compare_mode = GET_MODE (op0);
6906       else if (inner_compare
6907                && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6908                && new_code == old_code
6909                && op0 == XEXP (inner_compare, 0)
6910                && op1 == XEXP (inner_compare, 1))
6911         compare_mode = GET_MODE (inner_compare);
6912       else
6913         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6914
6915       /* If the mode changed, we have to change SET_DEST, the mode in the
6916          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
6917          a hard register, just build new versions with the proper mode.  If it
6918          is a pseudo, we lose unless it is only time we set the pseudo, in
6919          which case we can safely change its mode.  */
6920       if (compare_mode != GET_MODE (dest))
6921         {
6922           if (can_change_dest_mode (dest, 0, compare_mode))
6923             {
6924               unsigned int regno = REGNO (dest);
6925               rtx new_dest;
6926
6927               if (regno < FIRST_PSEUDO_REGISTER)
6928                 new_dest = gen_rtx_REG (compare_mode, regno);
6929               else
6930                 {
6931                   subst_mode (regno, compare_mode);
6932                   new_dest = regno_reg_rtx[regno];
6933                 }
6934
6935               SUBST (SET_DEST (x), new_dest);
6936               SUBST (XEXP (*cc_use, 0), new_dest);
6937               other_changed = true;
6938
6939               dest = new_dest;
6940             }
6941         }
6942 #endif  /* SELECT_CC_MODE */
6943
6944       /* If the code changed, we have to build a new comparison in
6945          undobuf.other_insn.  */
6946       if (new_code != old_code)
6947         {
6948           bool other_changed_previously = other_changed;
6949           unsigned HOST_WIDE_INT mask;
6950           rtx old_cc_use = *cc_use;
6951
6952           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6953                                           dest, const0_rtx));
6954           other_changed = true;
6955
6956           /* If the only change we made was to change an EQ into an NE or
6957              vice versa, OP0 has only one bit that might be nonzero, and OP1
6958              is zero, check if changing the user of the condition code will
6959              produce a valid insn.  If it won't, we can keep the original code
6960              in that insn by surrounding our operation with an XOR.  */
6961
6962           if (((old_code == NE && new_code == EQ)
6963                || (old_code == EQ && new_code == NE))
6964               && ! other_changed_previously && op1 == const0_rtx
6965               && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6966               && pow2p_hwi (mask = nonzero_bits (op0, GET_MODE (op0))))
6967             {
6968               rtx pat = PATTERN (other_insn), note = 0;
6969
6970               if ((recog_for_combine (&pat, other_insn, &note) < 0
6971                    && ! check_asm_operands (pat)))
6972                 {
6973                   *cc_use = old_cc_use;
6974                   other_changed = false;
6975
6976                   op0 = simplify_gen_binary (XOR, GET_MODE (op0), op0,
6977                                              gen_int_mode (mask,
6978                                                            GET_MODE (op0)));
6979                 }
6980             }
6981         }
6982
6983       if (other_changed)
6984         undobuf.other_insn = other_insn;
6985
6986       /* Don't generate a compare of a CC with 0, just use that CC.  */
6987       if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6988         {
6989           SUBST (SET_SRC (x), op0);
6990           src = SET_SRC (x);
6991         }
6992       /* Otherwise, if we didn't previously have the same COMPARE we
6993          want, create it from scratch.  */
6994       else if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode
6995                || XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6996         {
6997           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6998           src = SET_SRC (x);
6999         }
7000     }
7001   else
7002     {
7003       /* Get SET_SRC in a form where we have placed back any
7004          compound expressions.  Then do the checks below.  */
7005       src = make_compound_operation (src, SET);
7006       SUBST (SET_SRC (x), src);
7007     }
7008
7009   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
7010      and X being a REG or (subreg (reg)), we may be able to convert this to
7011      (set (subreg:m2 x) (op)).
7012
7013      We can always do this if M1 is narrower than M2 because that means that
7014      we only care about the low bits of the result.
7015
7016      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
7017      perform a narrower operation than requested since the high-order bits will
7018      be undefined.  On machine where it is defined, this transformation is safe
7019      as long as M1 and M2 have the same number of words.  */
7020
7021   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
7022       && !OBJECT_P (SUBREG_REG (src))
7023       && (known_equal_after_align_up
7024           (GET_MODE_SIZE (GET_MODE (src)),
7025            GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))),
7026            UNITS_PER_WORD))
7027       && (WORD_REGISTER_OPERATIONS || !paradoxical_subreg_p (src))
7028       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
7029             && !REG_CAN_CHANGE_MODE_P (REGNO (dest),
7030                                        GET_MODE (SUBREG_REG (src)),
7031                                        GET_MODE (src)))
7032       && (REG_P (dest)
7033           || (GET_CODE (dest) == SUBREG
7034               && REG_P (SUBREG_REG (dest)))))
7035     {
7036       SUBST (SET_DEST (x),
7037              gen_lowpart (GET_MODE (SUBREG_REG (src)),
7038                                       dest));
7039       SUBST (SET_SRC (x), SUBREG_REG (src));
7040
7041       src = SET_SRC (x), dest = SET_DEST (x);
7042     }
7043
7044   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
7045      would require a paradoxical subreg.  Replace the subreg with a
7046      zero_extend to avoid the reload that would otherwise be required.
7047      Don't do this unless we have a scalar integer mode, otherwise the
7048      transformation is incorrect.  */
7049
7050   enum rtx_code extend_op;
7051   if (paradoxical_subreg_p (src)
7052       && MEM_P (SUBREG_REG (src))
7053       && SCALAR_INT_MODE_P (GET_MODE (src))
7054       && (extend_op = load_extend_op (GET_MODE (SUBREG_REG (src)))) != UNKNOWN)
7055     {
7056       SUBST (SET_SRC (x),
7057              gen_rtx_fmt_e (extend_op, GET_MODE (src), SUBREG_REG (src)));
7058
7059       src = SET_SRC (x);
7060     }
7061
7062   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
7063      are comparing an item known to be 0 or -1 against 0, use a logical
7064      operation instead. Check for one of the arms being an IOR of the other
7065      arm with some value.  We compute three terms to be IOR'ed together.  In
7066      practice, at most two will be nonzero.  Then we do the IOR's.  */
7067
7068   if (GET_CODE (dest) != PC
7069       && GET_CODE (src) == IF_THEN_ELSE
7070       && is_int_mode (GET_MODE (src), &int_mode)
7071       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
7072       && XEXP (XEXP (src, 0), 1) == const0_rtx
7073       && int_mode == GET_MODE (XEXP (XEXP (src, 0), 0))
7074       && (!HAVE_conditional_move
7075           || ! can_conditionally_move_p (int_mode))
7076       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), int_mode)
7077           == GET_MODE_PRECISION (int_mode))
7078       && ! side_effects_p (src))
7079     {
7080       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
7081                       ? XEXP (src, 1) : XEXP (src, 2));
7082       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
7083                    ? XEXP (src, 2) : XEXP (src, 1));
7084       rtx term1 = const0_rtx, term2, term3;
7085
7086       if (GET_CODE (true_rtx) == IOR
7087           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
7088         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
7089       else if (GET_CODE (true_rtx) == IOR
7090                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
7091         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
7092       else if (GET_CODE (false_rtx) == IOR
7093                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
7094         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
7095       else if (GET_CODE (false_rtx) == IOR
7096                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
7097         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
7098
7099       term2 = simplify_gen_binary (AND, int_mode,
7100                                    XEXP (XEXP (src, 0), 0), true_rtx);
7101       term3 = simplify_gen_binary (AND, int_mode,
7102                                    simplify_gen_unary (NOT, int_mode,
7103                                                        XEXP (XEXP (src, 0), 0),
7104                                                        int_mode),
7105                                    false_rtx);
7106
7107       SUBST (SET_SRC (x),
7108              simplify_gen_binary (IOR, int_mode,
7109                                   simplify_gen_binary (IOR, int_mode,
7110                                                        term1, term2),
7111                                   term3));
7112
7113       src = SET_SRC (x);
7114     }
7115
7116   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7117      whole thing fail.  */
7118   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
7119     return src;
7120   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
7121     return dest;
7122   else
7123     /* Convert this into a field assignment operation, if possible.  */
7124     return make_field_assignment (x);
7125 }
7126 \f
7127 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7128    result.  */
7129
7130 static rtx
7131 simplify_logical (rtx x)
7132 {
7133   rtx op0 = XEXP (x, 0);
7134   rtx op1 = XEXP (x, 1);
7135   scalar_int_mode mode;
7136
7137   switch (GET_CODE (x))
7138     {
7139     case AND:
7140       /* We can call simplify_and_const_int only if we don't lose
7141          any (sign) bits when converting INTVAL (op1) to
7142          "unsigned HOST_WIDE_INT".  */
7143       if (is_a <scalar_int_mode> (GET_MODE (x), &mode)
7144           && CONST_INT_P (op1)
7145           && (HWI_COMPUTABLE_MODE_P (mode)
7146               || INTVAL (op1) > 0))
7147         {
7148           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
7149           if (GET_CODE (x) != AND)
7150             return x;
7151
7152           op0 = XEXP (x, 0);
7153           op1 = XEXP (x, 1);
7154         }
7155
7156       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7157          apply the distributive law and then the inverse distributive
7158          law to see if things simplify.  */
7159       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
7160         {
7161           rtx result = distribute_and_simplify_rtx (x, 0);
7162           if (result)
7163             return result;
7164         }
7165       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
7166         {
7167           rtx result = distribute_and_simplify_rtx (x, 1);
7168           if (result)
7169             return result;
7170         }
7171       break;
7172
7173     case IOR:
7174       /* If we have (ior (and A B) C), apply the distributive law and then
7175          the inverse distributive law to see if things simplify.  */
7176
7177       if (GET_CODE (op0) == AND)
7178         {
7179           rtx result = distribute_and_simplify_rtx (x, 0);
7180           if (result)
7181             return result;
7182         }
7183
7184       if (GET_CODE (op1) == AND)
7185         {
7186           rtx result = distribute_and_simplify_rtx (x, 1);
7187           if (result)
7188             return result;
7189         }
7190       break;
7191
7192     default:
7193       gcc_unreachable ();
7194     }
7195
7196   return x;
7197 }
7198 \f
7199 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7200    operations" because they can be replaced with two more basic operations.
7201    ZERO_EXTEND is also considered "compound" because it can be replaced with
7202    an AND operation, which is simpler, though only one operation.
7203
7204    The function expand_compound_operation is called with an rtx expression
7205    and will convert it to the appropriate shifts and AND operations,
7206    simplifying at each stage.
7207
7208    The function make_compound_operation is called to convert an expression
7209    consisting of shifts and ANDs into the equivalent compound expression.
7210    It is the inverse of this function, loosely speaking.  */
7211
7212 static rtx
7213 expand_compound_operation (rtx x)
7214 {
7215   unsigned HOST_WIDE_INT pos = 0, len;
7216   bool unsignedp = false;
7217   unsigned int modewidth;
7218   rtx tem;
7219   scalar_int_mode inner_mode;
7220
7221   switch (GET_CODE (x))
7222     {
7223     case ZERO_EXTEND:
7224       unsignedp = true;
7225       /* FALLTHRU */
7226     case SIGN_EXTEND:
7227       /* We can't necessarily use a const_int for a multiword mode;
7228          it depends on implicitly extending the value.
7229          Since we don't know the right way to extend it,
7230          we can't tell whether the implicit way is right.
7231
7232          Even for a mode that is no wider than a const_int,
7233          we can't win, because we need to sign extend one of its bits through
7234          the rest of it, and we don't know which bit.  */
7235       if (CONST_INT_P (XEXP (x, 0)))
7236         return x;
7237
7238       /* Reject modes that aren't scalar integers because turning vector
7239          or complex modes into shifts causes problems.  */
7240       if (!is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode))
7241         return x;
7242
7243       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7244          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
7245          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7246          reloaded. If not for that, MEM's would very rarely be safe.
7247
7248          Reject modes bigger than a word, because we might not be able
7249          to reference a two-register group starting with an arbitrary register
7250          (and currently gen_lowpart might crash for a SUBREG).  */
7251
7252       if (GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7253         return x;
7254
7255       len = GET_MODE_PRECISION (inner_mode);
7256       /* If the inner object has VOIDmode (the only way this can happen
7257          is if it is an ASM_OPERANDS), we can't do anything since we don't
7258          know how much masking to do.  */
7259       if (len == 0)
7260         return x;
7261
7262       break;
7263
7264     case ZERO_EXTRACT:
7265       unsignedp = true;
7266
7267       /* fall through */
7268
7269     case SIGN_EXTRACT:
7270       /* If the operand is a CLOBBER, just return it.  */
7271       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
7272         return XEXP (x, 0);
7273
7274       if (!CONST_INT_P (XEXP (x, 1))
7275           || !CONST_INT_P (XEXP (x, 2)))
7276         return x;
7277
7278       /* Reject modes that aren't scalar integers because turning vector
7279          or complex modes into shifts causes problems.  */
7280       if (!is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode))
7281         return x;
7282
7283       len = INTVAL (XEXP (x, 1));
7284       pos = INTVAL (XEXP (x, 2));
7285
7286       /* This should stay within the object being extracted, fail otherwise.  */
7287       if (len + pos > GET_MODE_PRECISION (inner_mode))
7288         return x;
7289
7290       if (BITS_BIG_ENDIAN)
7291         pos = GET_MODE_PRECISION (inner_mode) - len - pos;
7292
7293       break;
7294
7295     default:
7296       return x;
7297     }
7298
7299   /* We've rejected non-scalar operations by now.  */
7300   scalar_int_mode mode = as_a <scalar_int_mode> (GET_MODE (x));
7301
7302   /* Convert sign extension to zero extension, if we know that the high
7303      bit is not set, as this is easier to optimize.  It will be converted
7304      back to cheaper alternative in make_extraction.  */
7305   if (GET_CODE (x) == SIGN_EXTEND
7306       && HWI_COMPUTABLE_MODE_P (mode)
7307       && ((nonzero_bits (XEXP (x, 0), inner_mode)
7308            & ~(((unsigned HOST_WIDE_INT) GET_MODE_MASK (inner_mode)) >> 1))
7309           == 0))
7310     {
7311       rtx temp = gen_rtx_ZERO_EXTEND (mode, XEXP (x, 0));
7312       rtx temp2 = expand_compound_operation (temp);
7313
7314       /* Make sure this is a profitable operation.  */
7315       if (set_src_cost (x, mode, optimize_this_for_speed_p)
7316           > set_src_cost (temp2, mode, optimize_this_for_speed_p))
7317        return temp2;
7318       else if (set_src_cost (x, mode, optimize_this_for_speed_p)
7319                > set_src_cost (temp, mode, optimize_this_for_speed_p))
7320        return temp;
7321       else
7322        return x;
7323     }
7324
7325   /* We can optimize some special cases of ZERO_EXTEND.  */
7326   if (GET_CODE (x) == ZERO_EXTEND)
7327     {
7328       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7329          know that the last value didn't have any inappropriate bits
7330          set.  */
7331       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
7332           && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode
7333           && HWI_COMPUTABLE_MODE_P (mode)
7334           && (nonzero_bits (XEXP (XEXP (x, 0), 0), mode)
7335               & ~GET_MODE_MASK (inner_mode)) == 0)
7336         return XEXP (XEXP (x, 0), 0);
7337
7338       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
7339       if (GET_CODE (XEXP (x, 0)) == SUBREG
7340           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
7341           && subreg_lowpart_p (XEXP (x, 0))
7342           && HWI_COMPUTABLE_MODE_P (mode)
7343           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), mode)
7344               & ~GET_MODE_MASK (inner_mode)) == 0)
7345         return SUBREG_REG (XEXP (x, 0));
7346
7347       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7348          is a comparison and STORE_FLAG_VALUE permits.  This is like
7349          the first case, but it works even when MODE is larger
7350          than HOST_WIDE_INT.  */
7351       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
7352           && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode
7353           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
7354           && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
7355           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (inner_mode)) == 0)
7356         return XEXP (XEXP (x, 0), 0);
7357
7358       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
7359       if (GET_CODE (XEXP (x, 0)) == SUBREG
7360           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
7361           && subreg_lowpart_p (XEXP (x, 0))
7362           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
7363           && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
7364           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (inner_mode)) == 0)
7365         return SUBREG_REG (XEXP (x, 0));
7366
7367     }
7368
7369   /* If we reach here, we want to return a pair of shifts.  The inner
7370      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
7371      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
7372      logical depending on the value of UNSIGNEDP.
7373
7374      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7375      converted into an AND of a shift.
7376
7377      We must check for the case where the left shift would have a negative
7378      count.  This can happen in a case like (x >> 31) & 255 on machines
7379      that can't shift by a constant.  On those machines, we would first
7380      combine the shift with the AND to produce a variable-position
7381      extraction.  Then the constant of 31 would be substituted in
7382      to produce such a position.  */
7383
7384   modewidth = GET_MODE_PRECISION (mode);
7385   if (modewidth >= pos + len)
7386     {
7387       tem = gen_lowpart (mode, XEXP (x, 0));
7388       if (!tem || GET_CODE (tem) == CLOBBER)
7389         return x;
7390       tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
7391                                   tem, modewidth - pos - len);
7392       tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
7393                                   mode, tem, modewidth - len);
7394     }
7395   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
7396     {
7397       tem = simplify_shift_const (NULL_RTX, LSHIFTRT, inner_mode,
7398                                   XEXP (x, 0), pos);
7399       tem = gen_lowpart (mode, tem);
7400       if (!tem || GET_CODE (tem) == CLOBBER)
7401         return x;
7402       tem = simplify_and_const_int (NULL_RTX, mode, tem,
7403                                     (HOST_WIDE_INT_1U << len) - 1);
7404     }
7405   else
7406     /* Any other cases we can't handle.  */
7407     return x;
7408
7409   /* If we couldn't do this for some reason, return the original
7410      expression.  */
7411   if (GET_CODE (tem) == CLOBBER)
7412     return x;
7413
7414   return tem;
7415 }
7416 \f
7417 /* X is a SET which contains an assignment of one object into
7418    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7419    or certain SUBREGS). If possible, convert it into a series of
7420    logical operations.
7421
7422    We half-heartedly support variable positions, but do not at all
7423    support variable lengths.  */
7424
7425 static const_rtx
7426 expand_field_assignment (const_rtx x)
7427 {
7428   rtx inner;
7429   rtx pos;                      /* Always counts from low bit.  */
7430   int len, inner_len;
7431   rtx mask, cleared, masked;
7432   scalar_int_mode compute_mode;
7433
7434   /* Loop until we find something we can't simplify.  */
7435   while (1)
7436     {
7437       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
7438           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
7439         {
7440           rtx x0 = XEXP (SET_DEST (x), 0);
7441           if (!GET_MODE_PRECISION (GET_MODE (x0)).is_constant (&len))
7442             break;
7443           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
7444           pos = gen_int_mode (subreg_lsb (XEXP (SET_DEST (x), 0)),
7445                               MAX_MODE_INT);
7446         }
7447       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
7448                && CONST_INT_P (XEXP (SET_DEST (x), 1)))
7449         {
7450           inner = XEXP (SET_DEST (x), 0);
7451           if (!GET_MODE_PRECISION (GET_MODE (inner)).is_constant (&inner_len))
7452             break;
7453
7454           len = INTVAL (XEXP (SET_DEST (x), 1));
7455           pos = XEXP (SET_DEST (x), 2);
7456
7457           /* A constant position should stay within the width of INNER.  */
7458           if (CONST_INT_P (pos) && INTVAL (pos) + len > inner_len)
7459             break;
7460
7461           if (BITS_BIG_ENDIAN)
7462             {
7463               if (CONST_INT_P (pos))
7464                 pos = GEN_INT (inner_len - len - INTVAL (pos));
7465               else if (GET_CODE (pos) == MINUS
7466                        && CONST_INT_P (XEXP (pos, 1))
7467                        && INTVAL (XEXP (pos, 1)) == inner_len - len)
7468                 /* If position is ADJUST - X, new position is X.  */
7469                 pos = XEXP (pos, 0);
7470               else
7471                 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
7472                                            gen_int_mode (inner_len - len,
7473                                                          GET_MODE (pos)),
7474                                            pos);
7475             }
7476         }
7477
7478       /* If the destination is a subreg that overwrites the whole of the inner
7479          register, we can move the subreg to the source.  */
7480       else if (GET_CODE (SET_DEST (x)) == SUBREG
7481                /* We need SUBREGs to compute nonzero_bits properly.  */
7482                && nonzero_sign_valid
7483                && !read_modify_subreg_p (SET_DEST (x)))
7484         {
7485           x = gen_rtx_SET (SUBREG_REG (SET_DEST (x)),
7486                            gen_lowpart
7487                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
7488                             SET_SRC (x)));
7489           continue;
7490         }
7491       else
7492         break;
7493
7494       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7495         inner = SUBREG_REG (inner);
7496
7497       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
7498       if (!is_a <scalar_int_mode> (GET_MODE (inner), &compute_mode))
7499         {
7500           /* Don't do anything for vector or complex integral types.  */
7501           if (! FLOAT_MODE_P (GET_MODE (inner)))
7502             break;
7503
7504           /* Try to find an integral mode to pun with.  */
7505           if (!int_mode_for_size (GET_MODE_BITSIZE (GET_MODE (inner)), 0)
7506               .exists (&compute_mode))
7507             break;
7508
7509           inner = gen_lowpart (compute_mode, inner);
7510         }
7511
7512       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
7513       if (len >= HOST_BITS_PER_WIDE_INT)
7514         break;
7515
7516       /* Don't try to compute in too wide unsupported modes.  */
7517       if (!targetm.scalar_mode_supported_p (compute_mode))
7518         break;
7519
7520       /* gen_lowpart_for_combine returns CLOBBER on failure.  */
7521       rtx lowpart = gen_lowpart (compute_mode, SET_SRC (x));
7522       if (GET_CODE (lowpart) == CLOBBER)
7523         break;
7524
7525       /* Now compute the equivalent expression.  Make a copy of INNER
7526          for the SET_DEST in case it is a MEM into which we will substitute;
7527          we don't want shared RTL in that case.  */
7528       mask = gen_int_mode ((HOST_WIDE_INT_1U << len) - 1,
7529                            compute_mode);
7530       cleared = simplify_gen_binary (AND, compute_mode,
7531                                      simplify_gen_unary (NOT, compute_mode,
7532                                        simplify_gen_binary (ASHIFT,
7533                                                             compute_mode,
7534                                                             mask, pos),
7535                                        compute_mode),
7536                                      inner);
7537       masked = simplify_gen_binary (ASHIFT, compute_mode,
7538                                     simplify_gen_binary (
7539                                       AND, compute_mode, lowpart, mask),
7540                                     pos);
7541
7542       x = gen_rtx_SET (copy_rtx (inner),
7543                        simplify_gen_binary (IOR, compute_mode,
7544                                             cleared, masked));
7545     }
7546
7547   return x;
7548 }
7549 \f
7550 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
7551    it is an RTX that represents the (variable) starting position; otherwise,
7552    POS is the (constant) starting bit position.  Both are counted from the LSB.
7553
7554    UNSIGNEDP is true for an unsigned reference and zero for a signed one.
7555
7556    IN_DEST is true if this is a reference in the destination of a SET.
7557    This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
7558    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7559    be used.
7560
7561    IN_COMPARE is true if we are in a COMPARE.  This means that a
7562    ZERO_EXTRACT should be built even for bits starting at bit 0.
7563
7564    MODE is the desired mode of the result (if IN_DEST == 0).
7565
7566    The result is an RTX for the extraction or NULL_RTX if the target
7567    can't handle it.  */
7568
7569 static rtx
7570 make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7571                  rtx pos_rtx, unsigned HOST_WIDE_INT len, bool unsignedp,
7572                  bool in_dest, bool in_compare)
7573 {
7574   /* This mode describes the size of the storage area
7575      to fetch the overall value from.  Within that, we
7576      ignore the POS lowest bits, etc.  */
7577   machine_mode is_mode = GET_MODE (inner);
7578   machine_mode inner_mode;
7579   scalar_int_mode wanted_inner_mode;
7580   scalar_int_mode wanted_inner_reg_mode = word_mode;
7581   scalar_int_mode pos_mode = word_mode;
7582   machine_mode extraction_mode = word_mode;
7583   rtx new_rtx = 0;
7584   rtx orig_pos_rtx = pos_rtx;
7585   HOST_WIDE_INT orig_pos;
7586
7587   if (pos_rtx && CONST_INT_P (pos_rtx))
7588     pos = INTVAL (pos_rtx), pos_rtx = 0;
7589
7590   if (GET_CODE (inner) == SUBREG
7591       && subreg_lowpart_p (inner)
7592       && (paradoxical_subreg_p (inner)
7593           /* If trying or potentionally trying to extract
7594              bits outside of is_mode, don't look through
7595              non-paradoxical SUBREGs.  See PR82192.  */
7596           || (pos_rtx == NULL_RTX
7597               && known_le (pos + len, GET_MODE_PRECISION (is_mode)))))
7598     {
7599       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7600          consider just the QI as the memory to extract from.
7601          The subreg adds or removes high bits; its mode is
7602          irrelevant to the meaning of this extraction,
7603          since POS and LEN count from the lsb.  */
7604       if (MEM_P (SUBREG_REG (inner)))
7605         is_mode = GET_MODE (SUBREG_REG (inner));
7606       inner = SUBREG_REG (inner);
7607     }
7608   else if (GET_CODE (inner) == ASHIFT
7609            && CONST_INT_P (XEXP (inner, 1))
7610            && pos_rtx == 0 && pos == 0
7611            && len > UINTVAL (XEXP (inner, 1)))
7612     {
7613       /* We're extracting the least significant bits of an rtx
7614          (ashift X (const_int C)), where LEN > C.  Extract the
7615          least significant (LEN - C) bits of X, giving an rtx
7616          whose mode is MODE, then shift it left C times.  */
7617       new_rtx = make_extraction (mode, XEXP (inner, 0),
7618                              0, 0, len - INTVAL (XEXP (inner, 1)),
7619                              unsignedp, in_dest, in_compare);
7620       if (new_rtx != 0)
7621         return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7622     }
7623   else if (GET_CODE (inner) == MULT
7624            && CONST_INT_P (XEXP (inner, 1))
7625            && pos_rtx == 0 && pos == 0)
7626     {
7627       /* We're extracting the least significant bits of an rtx
7628          (mult X (const_int 2^C)), where LEN > C.  Extract the
7629          least significant (LEN - C) bits of X, giving an rtx
7630          whose mode is MODE, then multiply it by 2^C.  */
7631       const HOST_WIDE_INT shift_amt = exact_log2 (INTVAL (XEXP (inner, 1)));
7632       if (len > 1 && IN_RANGE (shift_amt, 1, len - 1))
7633         {
7634           new_rtx = make_extraction (mode, XEXP (inner, 0),
7635                                      0, 0, len - shift_amt,
7636                                      unsignedp, in_dest, in_compare);
7637           if (new_rtx)
7638             return gen_rtx_MULT (mode, new_rtx, XEXP (inner, 1));
7639         }
7640     }
7641   else if (GET_CODE (inner) == TRUNCATE
7642            /* If trying or potentionally trying to extract
7643               bits outside of is_mode, don't look through
7644               TRUNCATE.  See PR82192.  */
7645            && pos_rtx == NULL_RTX
7646            && known_le (pos + len, GET_MODE_PRECISION (is_mode)))
7647     inner = XEXP (inner, 0);
7648
7649   inner_mode = GET_MODE (inner);
7650
7651   /* See if this can be done without an extraction.  We never can if the
7652      width of the field is not the same as that of some integer mode. For
7653      registers, we can only avoid the extraction if the position is at the
7654      low-order bit and this is either not in the destination or we have the
7655      appropriate STRICT_LOW_PART operation available.
7656
7657      For MEM, we can avoid an extract if the field starts on an appropriate
7658      boundary and we can change the mode of the memory reference.  */
7659
7660   scalar_int_mode tmode;
7661   if (int_mode_for_size (len, 1).exists (&tmode)
7662       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7663            && !MEM_P (inner)
7664            && (pos == 0 || REG_P (inner))
7665            && (inner_mode == tmode
7666                || !REG_P (inner)
7667                || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7668                || reg_truncated_to_mode (tmode, inner))
7669            && (! in_dest
7670                || (REG_P (inner)
7671                    && have_insn_for (STRICT_LOW_PART, tmode))))
7672           || (MEM_P (inner) && pos_rtx == 0
7673               && (pos
7674                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7675                      : BITS_PER_UNIT)) == 0
7676               /* We can't do this if we are widening INNER_MODE (it
7677                  may not be aligned, for one thing).  */
7678               && !paradoxical_subreg_p (tmode, inner_mode)
7679               && known_le (pos + len, GET_MODE_PRECISION (is_mode))
7680               && (inner_mode == tmode
7681                   || (! mode_dependent_address_p (XEXP (inner, 0),
7682                                                   MEM_ADDR_SPACE (inner))
7683                       && ! MEM_VOLATILE_P (inner))))))
7684     {
7685       /* If INNER is a MEM, make a new MEM that encompasses just the desired
7686          field.  If the original and current mode are the same, we need not
7687          adjust the offset.  Otherwise, we do if bytes big endian.
7688
7689          If INNER is not a MEM, get a piece consisting of just the field
7690          of interest (in this case POS % BITS_PER_WORD must be 0).  */
7691
7692       if (MEM_P (inner))
7693         {
7694           poly_int64 offset;
7695
7696           /* POS counts from lsb, but make OFFSET count in memory order.  */
7697           if (BYTES_BIG_ENDIAN)
7698             offset = bits_to_bytes_round_down (GET_MODE_PRECISION (is_mode)
7699                                                - len - pos);
7700           else
7701             offset = pos / BITS_PER_UNIT;
7702
7703           new_rtx = adjust_address_nv (inner, tmode, offset);
7704         }
7705       else if (REG_P (inner))
7706         {
7707           if (tmode != inner_mode)
7708             {
7709               /* We can't call gen_lowpart in a DEST since we
7710                  always want a SUBREG (see below) and it would sometimes
7711                  return a new hard register.  */
7712               if (pos || in_dest)
7713                 {
7714                   poly_uint64 offset
7715                     = subreg_offset_from_lsb (tmode, inner_mode, pos);
7716
7717                   /* Avoid creating invalid subregs, for example when
7718                      simplifying (x>>32)&255.  */
7719                   if (!validate_subreg (tmode, inner_mode, inner, offset))
7720                     return NULL_RTX;
7721
7722                   new_rtx = gen_rtx_SUBREG (tmode, inner, offset);
7723                 }
7724               else
7725                 new_rtx = gen_lowpart (tmode, inner);
7726             }
7727           else
7728             new_rtx = inner;
7729         }
7730       else
7731         new_rtx = force_to_mode (inner, tmode,
7732                                  len >= HOST_BITS_PER_WIDE_INT
7733                                  ? HOST_WIDE_INT_M1U
7734                                  : (HOST_WIDE_INT_1U << len) - 1, false);
7735
7736       /* If this extraction is going into the destination of a SET,
7737          make a STRICT_LOW_PART unless we made a MEM.  */
7738
7739       if (in_dest)
7740         return (MEM_P (new_rtx) ? new_rtx
7741                 : (GET_CODE (new_rtx) != SUBREG
7742                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
7743                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7744
7745       if (mode == tmode)
7746         return new_rtx;
7747
7748       if (CONST_SCALAR_INT_P (new_rtx))
7749         return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7750                                          mode, new_rtx, tmode);
7751
7752       /* If we know that no extraneous bits are set, and that the high
7753          bit is not set, convert the extraction to the cheaper of
7754          sign and zero extension, that are equivalent in these cases.  */
7755       if (flag_expensive_optimizations
7756           && (HWI_COMPUTABLE_MODE_P (tmode)
7757               && ((nonzero_bits (new_rtx, tmode)
7758                    & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7759                   == 0)))
7760         {
7761           rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7762           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7763
7764           /* Prefer ZERO_EXTENSION, since it gives more information to
7765              backends.  */
7766           if (set_src_cost (temp, mode, optimize_this_for_speed_p)
7767               <= set_src_cost (temp1, mode, optimize_this_for_speed_p))
7768             return temp;
7769           return temp1;
7770         }
7771
7772       /* Otherwise, sign- or zero-extend unless we already are in the
7773          proper mode.  */
7774
7775       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7776                              mode, new_rtx));
7777     }
7778
7779   /* Unless this is a COMPARE or we have a funny memory reference,
7780      don't do anything with zero-extending field extracts starting at
7781      the low-order bit since they are simple AND operations.  */
7782   if (pos_rtx == 0 && pos == 0 && ! in_dest
7783       && ! in_compare && unsignedp)
7784     return 0;
7785
7786   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7787      if the position is not a constant and the length is not 1.  In all
7788      other cases, we would only be going outside our object in cases when
7789      an original shift would have been undefined.  */
7790   if (MEM_P (inner)
7791       && ((pos_rtx == 0 && maybe_gt (pos + len, GET_MODE_PRECISION (is_mode)))
7792           || (pos_rtx != 0 && len != 1)))
7793     return 0;
7794
7795   enum extraction_pattern pattern = (in_dest ? EP_insv
7796                                      : unsignedp ? EP_extzv : EP_extv);
7797
7798   /* If INNER is not from memory, we want it to have the mode of a register
7799      extraction pattern's structure operand, or word_mode if there is no
7800      such pattern.  The same applies to extraction_mode and pos_mode
7801      and their respective operands.
7802
7803      For memory, assume that the desired extraction_mode and pos_mode
7804      are the same as for a register operation, since at present we don't
7805      have named patterns for aligned memory structures.  */
7806   class extraction_insn insn;
7807   unsigned int inner_size;
7808   if (GET_MODE_BITSIZE (inner_mode).is_constant (&inner_size)
7809       && get_best_reg_extraction_insn (&insn, pattern, inner_size, mode))
7810     {
7811       wanted_inner_reg_mode = insn.struct_mode.require ();
7812       pos_mode = insn.pos_mode;
7813       extraction_mode = insn.field_mode;
7814     }
7815
7816   /* Never narrow an object, since that might not be safe.  */
7817
7818   if (mode != VOIDmode
7819       && partial_subreg_p (extraction_mode, mode))
7820     extraction_mode = mode;
7821
7822   /* Punt if len is too large for extraction_mode.  */
7823   if (maybe_gt (len, GET_MODE_PRECISION (extraction_mode)))
7824     return NULL_RTX;
7825
7826   if (!MEM_P (inner))
7827     wanted_inner_mode = wanted_inner_reg_mode;
7828   else
7829     {
7830       /* Be careful not to go beyond the extracted object and maintain the
7831          natural alignment of the memory.  */
7832       wanted_inner_mode = smallest_int_mode_for_size (len).require ();
7833       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7834              > GET_MODE_BITSIZE (wanted_inner_mode))
7835         wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode).require ();
7836     }
7837
7838   orig_pos = pos;
7839
7840   if (BITS_BIG_ENDIAN)
7841     {
7842       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7843          BITS_BIG_ENDIAN style.  If position is constant, compute new
7844          position.  Otherwise, build subtraction.
7845          Note that POS is relative to the mode of the original argument.
7846          If it's a MEM we need to recompute POS relative to that.
7847          However, if we're extracting from (or inserting into) a register,
7848          we want to recompute POS relative to wanted_inner_mode.  */
7849       int width;
7850       if (!MEM_P (inner))
7851         width = GET_MODE_BITSIZE (wanted_inner_mode);
7852       else if (!GET_MODE_BITSIZE (is_mode).is_constant (&width))
7853         return NULL_RTX;
7854
7855       if (pos_rtx == 0)
7856         pos = width - len - pos;
7857       else
7858         pos_rtx
7859           = gen_rtx_MINUS (GET_MODE (pos_rtx),
7860                            gen_int_mode (width - len, GET_MODE (pos_rtx)),
7861                            pos_rtx);
7862       /* POS may be less than 0 now, but we check for that below.
7863          Note that it can only be less than 0 if !MEM_P (inner).  */
7864     }
7865
7866   /* If INNER has a wider mode, and this is a constant extraction, try to
7867      make it smaller and adjust the byte to point to the byte containing
7868      the value.  */
7869   if (wanted_inner_mode != VOIDmode
7870       && inner_mode != wanted_inner_mode
7871       && ! pos_rtx
7872       && partial_subreg_p (wanted_inner_mode, is_mode)
7873       && MEM_P (inner)
7874       && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner))
7875       && ! MEM_VOLATILE_P (inner))
7876     {
7877       poly_int64 offset = 0;
7878
7879       /* The computations below will be correct if the machine is big
7880          endian in both bits and bytes or little endian in bits and bytes.
7881          If it is mixed, we must adjust.  */
7882
7883       /* If bytes are big endian and we had a paradoxical SUBREG, we must
7884          adjust OFFSET to compensate.  */
7885       if (BYTES_BIG_ENDIAN
7886           && paradoxical_subreg_p (is_mode, inner_mode))
7887         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7888
7889       /* We can now move to the desired byte.  */
7890       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7891                 * GET_MODE_SIZE (wanted_inner_mode);
7892       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7893
7894       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7895           && is_mode != wanted_inner_mode)
7896         offset = (GET_MODE_SIZE (is_mode)
7897                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
7898
7899       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7900     }
7901
7902   /* If INNER is not memory, get it into the proper mode.  If we are changing
7903      its mode, POS must be a constant and smaller than the size of the new
7904      mode.  */
7905   else if (!MEM_P (inner))
7906     {
7907       /* On the LHS, don't create paradoxical subregs implicitely truncating
7908          the register unless TARGET_TRULY_NOOP_TRUNCATION.  */
7909       if (in_dest
7910           && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7911                                              wanted_inner_mode))
7912         return NULL_RTX;
7913
7914       if (GET_MODE (inner) != wanted_inner_mode
7915           && (pos_rtx != 0
7916               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7917         return NULL_RTX;
7918
7919       if (orig_pos < 0)
7920         return NULL_RTX;
7921
7922       inner = force_to_mode (inner, wanted_inner_mode,
7923                              pos_rtx
7924                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7925                              ? HOST_WIDE_INT_M1U
7926                              : (((HOST_WIDE_INT_1U << len) - 1)
7927                                 << orig_pos), false);
7928     }
7929
7930   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
7931      have to zero extend.  Otherwise, we can just use a SUBREG.
7932
7933      We dealt with constant rtxes earlier, so pos_rtx cannot
7934      have VOIDmode at this point.  */
7935   if (pos_rtx != 0
7936       && (GET_MODE_SIZE (pos_mode)
7937           > GET_MODE_SIZE (as_a <scalar_int_mode> (GET_MODE (pos_rtx)))))
7938     {
7939       rtx temp = simplify_gen_unary (ZERO_EXTEND, pos_mode, pos_rtx,
7940                                      GET_MODE (pos_rtx));
7941
7942       /* If we know that no extraneous bits are set, and that the high
7943          bit is not set, convert extraction to cheaper one - either
7944          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7945          cases.  */
7946       if (flag_expensive_optimizations
7947           && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7948               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7949                    & ~(((unsigned HOST_WIDE_INT)
7950                         GET_MODE_MASK (GET_MODE (pos_rtx)))
7951                        >> 1))
7952                   == 0)))
7953         {
7954           rtx temp1 = simplify_gen_unary (SIGN_EXTEND, pos_mode, pos_rtx,
7955                                           GET_MODE (pos_rtx));
7956
7957           /* Prefer ZERO_EXTENSION, since it gives more information to
7958              backends.  */
7959           if (set_src_cost (temp1, pos_mode, optimize_this_for_speed_p)
7960               < set_src_cost (temp, pos_mode, optimize_this_for_speed_p))
7961             temp = temp1;
7962         }
7963       pos_rtx = temp;
7964     }
7965
7966   /* Make POS_RTX unless we already have it and it is correct.  If we don't
7967      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7968      be a CONST_INT.  */
7969   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7970     pos_rtx = orig_pos_rtx;
7971
7972   else if (pos_rtx == 0)
7973     pos_rtx = GEN_INT (pos);
7974
7975   /* Make the required operation.  See if we can use existing rtx.  */
7976   new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7977                          extraction_mode, inner, GEN_INT (len), pos_rtx);
7978   if (! in_dest)
7979     new_rtx = gen_lowpart (mode, new_rtx);
7980
7981   return new_rtx;
7982 }
7983 \f
7984 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
7985    can be commuted with any other operations in X.  Return X without
7986    that shift if so.  */
7987
7988 static rtx
7989 extract_left_shift (scalar_int_mode mode, rtx x, int count)
7990 {
7991   enum rtx_code code = GET_CODE (x);
7992   rtx tem;
7993
7994   switch (code)
7995     {
7996     case ASHIFT:
7997       /* This is the shift itself.  If it is wide enough, we will return
7998          either the value being shifted if the shift count is equal to
7999          COUNT or a shift for the difference.  */
8000       if (CONST_INT_P (XEXP (x, 1))
8001           && INTVAL (XEXP (x, 1)) >= count)
8002         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
8003                                      INTVAL (XEXP (x, 1)) - count);
8004       break;
8005
8006     case NEG:  case NOT:
8007       if ((tem = extract_left_shift (mode, XEXP (x, 0), count)) != 0)
8008         return simplify_gen_unary (code, mode, tem, mode);
8009
8010       break;
8011
8012     case PLUS:  case IOR:  case XOR:  case AND:
8013       /* If we can safely shift this constant and we find the inner shift,
8014          make a new operation.  */
8015       if (CONST_INT_P (XEXP (x, 1))
8016           && (UINTVAL (XEXP (x, 1))
8017               & (((HOST_WIDE_INT_1U << count)) - 1)) == 0
8018           && (tem = extract_left_shift (mode, XEXP (x, 0), count)) != 0)
8019         {
8020           HOST_WIDE_INT val = INTVAL (XEXP (x, 1)) >> count;
8021           return simplify_gen_binary (code, mode, tem,
8022                                       gen_int_mode (val, mode));
8023         }
8024       break;
8025
8026     default:
8027       break;
8028     }
8029
8030   return 0;
8031 }
8032 \f
8033 /* Subroutine of make_compound_operation.  *X_PTR is the rtx at the current
8034    level of the expression and MODE is its mode.  IN_CODE is as for
8035    make_compound_operation.  *NEXT_CODE_PTR is the value of IN_CODE
8036    that should be used when recursing on operands of *X_PTR.
8037
8038    There are two possible actions:
8039
8040    - Return null.  This tells the caller to recurse on *X_PTR with IN_CODE
8041      equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
8042
8043    - Return a new rtx, which the caller returns directly.  */
8044
8045 static rtx
8046 make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
8047                              enum rtx_code in_code,
8048                              enum rtx_code *next_code_ptr)
8049 {
8050   rtx x = *x_ptr;
8051   enum rtx_code next_code = *next_code_ptr;
8052   enum rtx_code code = GET_CODE (x);
8053   int mode_width = GET_MODE_PRECISION (mode);
8054   rtx rhs, lhs;
8055   rtx new_rtx = 0;
8056   int i;
8057   rtx tem;
8058   scalar_int_mode inner_mode;
8059   bool equality_comparison = false;
8060
8061   if (in_code == EQ)
8062     {
8063       equality_comparison = true;
8064       in_code = COMPARE;
8065     }
8066
8067   /* Process depending on the code of this operation.  If NEW is set
8068      nonzero, it will be returned.  */
8069
8070   switch (code)
8071     {
8072     case ASHIFT:
8073       /* Convert shifts by constants into multiplications if inside
8074          an address.  */
8075       if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
8076           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8077           && INTVAL (XEXP (x, 1)) >= 0)
8078         {
8079           HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
8080           HOST_WIDE_INT multval = HOST_WIDE_INT_1 << count;
8081
8082           new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8083           if (GET_CODE (new_rtx) == NEG)
8084             {
8085               new_rtx = XEXP (new_rtx, 0);
8086               multval = -multval;
8087             }
8088           multval = trunc_int_for_mode (multval, mode);
8089           new_rtx = gen_rtx_MULT (mode, new_rtx, gen_int_mode (multval, mode));
8090         }
8091       break;
8092
8093     case PLUS:
8094       lhs = XEXP (x, 0);
8095       rhs = XEXP (x, 1);
8096       lhs = make_compound_operation (lhs, next_code);
8097       rhs = make_compound_operation (rhs, next_code);
8098       if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG)
8099         {
8100           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
8101                                      XEXP (lhs, 1));
8102           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
8103         }
8104       else if (GET_CODE (lhs) == MULT
8105                && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
8106         {
8107           tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
8108                                      simplify_gen_unary (NEG, mode,
8109                                                          XEXP (lhs, 1),
8110                                                          mode));
8111           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
8112         }
8113       else
8114         {
8115           SUBST (XEXP (x, 0), lhs);
8116           SUBST (XEXP (x, 1), rhs);
8117         }
8118       maybe_swap_commutative_operands (x);
8119       return x;
8120
8121     case MINUS:
8122       lhs = XEXP (x, 0);
8123       rhs = XEXP (x, 1);
8124       lhs = make_compound_operation (lhs, next_code);
8125       rhs = make_compound_operation (rhs, next_code);
8126       if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG)
8127         {
8128           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
8129                                      XEXP (rhs, 1));
8130           return simplify_gen_binary (PLUS, mode, tem, lhs);
8131         }
8132       else if (GET_CODE (rhs) == MULT
8133                && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
8134         {
8135           tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
8136                                      simplify_gen_unary (NEG, mode,
8137                                                          XEXP (rhs, 1),
8138                                                          mode));
8139           return simplify_gen_binary (PLUS, mode, tem, lhs);
8140         }
8141       else
8142         {
8143           SUBST (XEXP (x, 0), lhs);
8144           SUBST (XEXP (x, 1), rhs);
8145           return x;
8146         }
8147
8148     case AND:
8149       /* If the second operand is not a constant, we can't do anything
8150          with it.  */
8151       if (!CONST_INT_P (XEXP (x, 1)))
8152         break;
8153
8154       /* If the constant is a power of two minus one and the first operand
8155          is a logical right shift, make an extraction.  */
8156       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8157           && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8158         {
8159           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
8160           new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1),
8161                                      i, true, false, in_code == COMPARE);
8162         }
8163
8164       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
8165       else if (GET_CODE (XEXP (x, 0)) == SUBREG
8166                && subreg_lowpart_p (XEXP (x, 0))
8167                && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (XEXP (x, 0))),
8168                                           &inner_mode)
8169                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
8170                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8171         {
8172           rtx inner_x0 = SUBREG_REG (XEXP (x, 0));
8173           new_rtx = make_compound_operation (XEXP (inner_x0, 0), next_code);
8174           new_rtx = make_extraction (inner_mode, new_rtx, 0,
8175                                      XEXP (inner_x0, 1),
8176                                      i, true, false, in_code == COMPARE);
8177
8178           /* If we narrowed the mode when dropping the subreg, then we lose.  */
8179           if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode))
8180             new_rtx = NULL;
8181
8182           /* If that didn't give anything, see if the AND simplifies on
8183              its own.  */
8184           if (!new_rtx && i >= 0)
8185             {
8186               new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8187               new_rtx = make_extraction (mode, new_rtx, 0, NULL_RTX, i,
8188                                          true, false, in_code == COMPARE);
8189             }
8190         }
8191       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
8192       else if ((GET_CODE (XEXP (x, 0)) == XOR
8193                 || GET_CODE (XEXP (x, 0)) == IOR)
8194                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
8195                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
8196                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8197         {
8198           /* Apply the distributive law, and then try to make extractions.  */
8199           new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
8200                                     gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
8201                                                  XEXP (x, 1)),
8202                                     gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
8203                                                  XEXP (x, 1)));
8204           new_rtx = make_compound_operation (new_rtx, in_code);
8205         }
8206
8207       /* If we are have (and (rotate X C) M) and C is larger than the number
8208          of bits in M, this is an extraction.  */
8209
8210       else if (GET_CODE (XEXP (x, 0)) == ROTATE
8211                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8212                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
8213                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
8214         {
8215           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
8216           new_rtx = make_extraction (mode, new_rtx,
8217                                      (GET_MODE_PRECISION (mode)
8218                                       - INTVAL (XEXP (XEXP (x, 0), 1))),
8219                                      NULL_RTX, i, true, false,
8220                                      in_code == COMPARE);
8221         }
8222
8223       /* On machines without logical shifts, if the operand of the AND is
8224          a logical shift and our mask turns off all the propagated sign
8225          bits, we can replace the logical shift with an arithmetic shift.  */
8226       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8227                && !have_insn_for (LSHIFTRT, mode)
8228                && have_insn_for (ASHIFTRT, mode)
8229                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8230                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8231                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8232                && mode_width <= HOST_BITS_PER_WIDE_INT)
8233         {
8234           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
8235
8236           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
8237           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
8238             SUBST (XEXP (x, 0),
8239                    gen_rtx_ASHIFTRT (mode,
8240                                      make_compound_operation (XEXP (XEXP (x,
8241                                                                           0),
8242                                                                     0),
8243                                                               next_code),
8244                                      XEXP (XEXP (x, 0), 1)));
8245         }
8246
8247       /* If the constant is one less than a power of two, this might be
8248          representable by an extraction even if no shift is present.
8249          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8250          we are in a COMPARE.  */
8251       else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8252         new_rtx = make_extraction (mode,
8253                                    make_compound_operation (XEXP (x, 0),
8254                                                             next_code),
8255                                    0, NULL_RTX, i,
8256                                    true, false, in_code == COMPARE);
8257
8258       /* If we are in a comparison and this is an AND with a power of two,
8259          convert this into the appropriate bit extract.  */
8260       else if (in_code == COMPARE
8261                && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
8262                && (equality_comparison || i < GET_MODE_PRECISION (mode) - 1))
8263         new_rtx = make_extraction (mode,
8264                                    make_compound_operation (XEXP (x, 0),
8265                                                             next_code),
8266                                    i, NULL_RTX, 1, true, false, true);
8267
8268       /* If the one operand is a paradoxical subreg of a register or memory and
8269          the constant (limited to the smaller mode) has only zero bits where
8270          the sub expression has known zero bits, this can be expressed as
8271          a zero_extend.  */
8272       else if (GET_CODE (XEXP (x, 0)) == SUBREG)
8273         {
8274           rtx sub;
8275
8276           sub = XEXP (XEXP (x, 0), 0);
8277           machine_mode sub_mode = GET_MODE (sub);
8278           int sub_width;
8279           if ((REG_P (sub) || MEM_P (sub))
8280               && GET_MODE_PRECISION (sub_mode).is_constant (&sub_width)
8281               && sub_width < mode_width
8282               && (!WORD_REGISTER_OPERATIONS
8283                   || sub_width >= BITS_PER_WORD
8284                   /* On WORD_REGISTER_OPERATIONS targets the bits
8285                      beyond sub_mode aren't considered undefined,
8286                      so optimize only if it is a MEM load when MEM loads
8287                      zero extend, because then the upper bits are all zero.  */
8288                   || (MEM_P (sub)
8289                       && load_extend_op (sub_mode) == ZERO_EXTEND)))
8290             {
8291               unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (sub_mode);
8292               unsigned HOST_WIDE_INT mask;
8293
8294               /* Original AND constant with all the known zero bits set.  */
8295               mask = UINTVAL (XEXP (x, 1)) | (~nonzero_bits (sub, sub_mode));
8296               if ((mask & mode_mask) == mode_mask)
8297                 {
8298                   new_rtx = make_compound_operation (sub, next_code);
8299                   new_rtx = make_extraction (mode, new_rtx, 0, 0, sub_width,
8300                                              true, false, in_code == COMPARE);
8301                 }
8302             }
8303         }
8304
8305       break;
8306
8307     case LSHIFTRT:
8308       /* If the sign bit is known to be zero, replace this with an
8309          arithmetic shift.  */
8310       if (have_insn_for (ASHIFTRT, mode)
8311           && ! have_insn_for (LSHIFTRT, mode)
8312           && mode_width <= HOST_BITS_PER_WIDE_INT
8313           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
8314         {
8315           new_rtx = gen_rtx_ASHIFTRT (mode,
8316                                       make_compound_operation (XEXP (x, 0),
8317                                                                next_code),
8318                                       XEXP (x, 1));
8319           break;
8320         }
8321
8322       /* fall through */
8323
8324     case ASHIFTRT:
8325       lhs = XEXP (x, 0);
8326       rhs = XEXP (x, 1);
8327
8328       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8329          this is a SIGN_EXTRACT.  */
8330       if (CONST_INT_P (rhs)
8331           && GET_CODE (lhs) == ASHIFT
8332           && CONST_INT_P (XEXP (lhs, 1))
8333           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
8334           && INTVAL (XEXP (lhs, 1)) >= 0
8335           && INTVAL (rhs) < mode_width)
8336         {
8337           new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
8338           new_rtx = make_extraction (mode, new_rtx,
8339                                      INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
8340                                      NULL_RTX, mode_width - INTVAL (rhs),
8341                                      code == LSHIFTRT, false,
8342                                      in_code == COMPARE);
8343           break;
8344         }
8345
8346       /* See if we have operations between an ASHIFTRT and an ASHIFT.
8347          If so, try to merge the shifts into a SIGN_EXTEND.  We could
8348          also do this for some cases of SIGN_EXTRACT, but it doesn't
8349          seem worth the effort; the case checked for occurs on Alpha.  */
8350
8351       if (!OBJECT_P (lhs)
8352           && ! (GET_CODE (lhs) == SUBREG
8353                 && (OBJECT_P (SUBREG_REG (lhs))))
8354           && CONST_INT_P (rhs)
8355           && INTVAL (rhs) >= 0
8356           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
8357           && INTVAL (rhs) < mode_width
8358           && (new_rtx = extract_left_shift (mode, lhs, INTVAL (rhs))) != 0)
8359         new_rtx = make_extraction (mode, make_compound_operation (new_rtx,
8360                                                                   next_code),
8361                                    0, NULL_RTX, mode_width - INTVAL (rhs),
8362                                    code == LSHIFTRT, false, in_code == COMPARE);
8363
8364       break;
8365
8366     case SUBREG:
8367       /* Call ourselves recursively on the inner expression.  If we are
8368          narrowing the object and it has a different RTL code from
8369          what it originally did, do this SUBREG as a force_to_mode.  */
8370       {
8371         rtx inner = SUBREG_REG (x), simplified;
8372         enum rtx_code subreg_code = in_code;
8373
8374         /* If the SUBREG is masking of a logical right shift,
8375            make an extraction.  */
8376         if (GET_CODE (inner) == LSHIFTRT
8377             && is_a <scalar_int_mode> (GET_MODE (inner), &inner_mode)
8378             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (inner_mode)
8379             && CONST_INT_P (XEXP (inner, 1))
8380             && UINTVAL (XEXP (inner, 1)) < GET_MODE_PRECISION (inner_mode)
8381             && subreg_lowpart_p (x))
8382           {
8383             new_rtx = make_compound_operation (XEXP (inner, 0), next_code);
8384             int width = GET_MODE_PRECISION (inner_mode)
8385                         - INTVAL (XEXP (inner, 1));
8386             if (width > mode_width)
8387               width = mode_width;
8388             new_rtx = make_extraction (mode, new_rtx, 0, XEXP (inner, 1),
8389                                        width, true, false, in_code == COMPARE);
8390             break;
8391           }
8392
8393         /* If in_code is COMPARE, it isn't always safe to pass it through
8394            to the recursive make_compound_operation call.  */
8395         if (subreg_code == COMPARE
8396             && (!subreg_lowpart_p (x)
8397                 || GET_CODE (inner) == SUBREG
8398                 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8399                    is (const_int 0), rather than
8400                    (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8401                    Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8402                    for non-equality comparisons against 0 is not equivalent
8403                    to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0).  */
8404                 || (GET_CODE (inner) == AND
8405                     && CONST_INT_P (XEXP (inner, 1))
8406                     && partial_subreg_p (x)
8407                     && exact_log2 (UINTVAL (XEXP (inner, 1)))
8408                        >= GET_MODE_BITSIZE (mode) - 1)))
8409           subreg_code = SET;
8410
8411         tem = make_compound_operation (inner, subreg_code);
8412
8413         simplified
8414           = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
8415         if (simplified)
8416           tem = simplified;
8417
8418         if (GET_CODE (tem) != GET_CODE (inner)
8419             && partial_subreg_p (x)
8420             && subreg_lowpart_p (x))
8421           {
8422             rtx newer
8423               = force_to_mode (tem, mode, HOST_WIDE_INT_M1U, false);
8424
8425             /* If we have something other than a SUBREG, we might have
8426                done an expansion, so rerun ourselves.  */
8427             if (GET_CODE (newer) != SUBREG)
8428               newer = make_compound_operation (newer, in_code);
8429
8430             /* force_to_mode can expand compounds.  If it just re-expanded
8431                the compound, use gen_lowpart to convert to the desired
8432                mode.  */
8433             if (rtx_equal_p (newer, x)
8434                 /* Likewise if it re-expanded the compound only partially.
8435                    This happens for SUBREG of ZERO_EXTRACT if they extract
8436                    the same number of bits.  */
8437                 || (GET_CODE (newer) == SUBREG
8438                     && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
8439                         || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
8440                     && GET_CODE (inner) == AND
8441                     && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
8442               return gen_lowpart (GET_MODE (x), tem);
8443
8444             return newer;
8445           }
8446
8447         if (simplified)
8448           return tem;
8449       }
8450       break;
8451
8452     default:
8453       break;
8454     }
8455
8456   if (new_rtx)
8457     *x_ptr = gen_lowpart (mode, new_rtx);
8458   *next_code_ptr = next_code;
8459   return NULL_RTX;
8460 }
8461
8462 /* Look at the expression rooted at X.  Look for expressions
8463    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8464    Form these expressions.
8465
8466    Return the new rtx, usually just X.
8467
8468    Also, for machines like the VAX that don't have logical shift insns,
8469    try to convert logical to arithmetic shift operations in cases where
8470    they are equivalent.  This undoes the canonicalizations to logical
8471    shifts done elsewhere.
8472
8473    We try, as much as possible, to re-use rtl expressions to save memory.
8474
8475    IN_CODE says what kind of expression we are processing.  Normally, it is
8476    SET.  In a memory address it is MEM.  When processing the arguments of
8477    a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8478    precisely it is an equality comparison against zero.  */
8479
8480 rtx
8481 make_compound_operation (rtx x, enum rtx_code in_code)
8482 {
8483   enum rtx_code code = GET_CODE (x);
8484   const char *fmt;
8485   int i, j;
8486   enum rtx_code next_code;
8487   rtx new_rtx, tem;
8488
8489   /* Select the code to be used in recursive calls.  Once we are inside an
8490      address, we stay there.  If we have a comparison, set to COMPARE,
8491      but once inside, go back to our default of SET.  */
8492
8493   next_code = (code == MEM ? MEM
8494                : ((code == COMPARE || COMPARISON_P (x))
8495                   && XEXP (x, 1) == const0_rtx) ? COMPARE
8496                : in_code == COMPARE || in_code == EQ ? SET : in_code);
8497
8498   scalar_int_mode mode;
8499   if (is_a <scalar_int_mode> (GET_MODE (x), &mode))
8500     {
8501       rtx new_rtx = make_compound_operation_int (mode, &x, in_code,
8502                                                  &next_code);
8503       if (new_rtx)
8504         return new_rtx;
8505       code = GET_CODE (x);
8506     }
8507
8508   /* Now recursively process each operand of this operation.  We need to
8509      handle ZERO_EXTEND specially so that we don't lose track of the
8510      inner mode.  */
8511   if (code == ZERO_EXTEND)
8512     {
8513       new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8514       tem = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8515                                       new_rtx, GET_MODE (XEXP (x, 0)));
8516       if (tem)
8517         return tem;
8518       SUBST (XEXP (x, 0), new_rtx);
8519       return x;
8520     }
8521
8522   fmt = GET_RTX_FORMAT (code);
8523   for (i = 0; i < GET_RTX_LENGTH (code); i++)
8524     if (fmt[i] == 'e')
8525       {
8526         new_rtx = make_compound_operation (XEXP (x, i), next_code);
8527         SUBST (XEXP (x, i), new_rtx);
8528       }
8529     else if (fmt[i] == 'E')
8530       for (j = 0; j < XVECLEN (x, i); j++)
8531         {
8532           new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
8533           SUBST (XVECEXP (x, i, j), new_rtx);
8534         }
8535
8536   maybe_swap_commutative_operands (x);
8537   return x;
8538 }
8539 \f
8540 /* Given M see if it is a value that would select a field of bits
8541    within an item, but not the entire word.  Return -1 if not.
8542    Otherwise, return the starting position of the field, where 0 is the
8543    low-order bit.
8544
8545    *PLEN is set to the length of the field.  */
8546
8547 static int
8548 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
8549 {
8550   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
8551   int pos = m ? ctz_hwi (m) : -1;
8552   int len = 0;
8553
8554   if (pos >= 0)
8555     /* Now shift off the low-order zero bits and see if we have a
8556        power of two minus 1.  */
8557     len = exact_log2 ((m >> pos) + 1);
8558
8559   if (len <= 0)
8560     pos = -1;
8561
8562   *plen = len;
8563   return pos;
8564 }
8565 \f
8566 /* If X refers to a register that equals REG in value, replace these
8567    references with REG.  */
8568 static rtx
8569 canon_reg_for_combine (rtx x, rtx reg)
8570 {
8571   rtx op0, op1, op2;
8572   const char *fmt;
8573   int i;
8574   bool copied;
8575
8576   enum rtx_code code = GET_CODE (x);
8577   switch (GET_RTX_CLASS (code))
8578     {
8579     case RTX_UNARY:
8580       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8581       if (op0 != XEXP (x, 0))
8582         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
8583                                    GET_MODE (reg));
8584       break;
8585
8586     case RTX_BIN_ARITH:
8587     case RTX_COMM_ARITH:
8588       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8589       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8590       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8591         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
8592       break;
8593
8594     case RTX_COMPARE:
8595     case RTX_COMM_COMPARE:
8596       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8597       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8598       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8599         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
8600                                         GET_MODE (op0), op0, op1);
8601       break;
8602
8603     case RTX_TERNARY:
8604     case RTX_BITFIELD_OPS:
8605       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8606       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8607       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
8608       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
8609         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
8610                                      GET_MODE (op0), op0, op1, op2);
8611       /* FALLTHRU */
8612
8613     case RTX_OBJ:
8614       if (REG_P (x))
8615         {
8616           if (rtx_equal_p (get_last_value (reg), x)
8617               || rtx_equal_p (reg, get_last_value (x)))
8618             return reg;
8619           else
8620             break;
8621         }
8622
8623       /* fall through */
8624
8625     default:
8626       fmt = GET_RTX_FORMAT (code);
8627       copied = false;
8628       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8629         if (fmt[i] == 'e')
8630           {
8631             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
8632             if (op != XEXP (x, i))
8633               {
8634                 if (!copied)
8635                   {
8636                     copied = true;
8637                     x = copy_rtx (x);
8638                   }
8639                 XEXP (x, i) = op;
8640               }
8641           }
8642         else if (fmt[i] == 'E')
8643           {
8644             int j;
8645             for (j = 0; j < XVECLEN (x, i); j++)
8646               {
8647                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
8648                 if (op != XVECEXP (x, i, j))
8649                   {
8650                     if (!copied)
8651                       {
8652                         copied = true;
8653                         x = copy_rtx (x);
8654                       }
8655                     XVECEXP (x, i, j) = op;
8656                   }
8657               }
8658           }
8659
8660       break;
8661     }
8662
8663   return x;
8664 }
8665
8666 /* Return X converted to MODE.  If the value is already truncated to
8667    MODE we can just return a subreg even though in the general case we
8668    would need an explicit truncation.  */
8669
8670 static rtx
8671 gen_lowpart_or_truncate (machine_mode mode, rtx x)
8672 {
8673   if (!CONST_INT_P (x)
8674       && partial_subreg_p (mode, GET_MODE (x))
8675       && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
8676       && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
8677     {
8678       /* Bit-cast X into an integer mode.  */
8679       if (!SCALAR_INT_MODE_P (GET_MODE (x)))
8680         x = gen_lowpart (int_mode_for_mode (GET_MODE (x)).require (), x);
8681       x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode).require (),
8682                               x, GET_MODE (x));
8683     }
8684
8685   return gen_lowpart (mode, x);
8686 }
8687
8688 /* See if X can be simplified knowing that we will only refer to it in
8689    MODE and will only refer to those bits that are nonzero in MASK.
8690    If other bits are being computed or if masking operations are done
8691    that select a superset of the bits in MASK, they can sometimes be
8692    ignored.
8693
8694    Return a possibly simplified expression, but always convert X to
8695    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
8696
8697    If JUST_SELECT is true, don't optimize by noticing that bits in MASK
8698    are all off in X.  This is used when X will be complemented, by either
8699    NOT, NEG, or XOR.  */
8700
8701 static rtx
8702 force_to_mode (rtx x, machine_mode mode, unsigned HOST_WIDE_INT mask,
8703                bool just_select)
8704 {
8705   enum rtx_code code = GET_CODE (x);
8706   bool next_select = just_select || code == XOR || code == NOT || code == NEG;
8707   machine_mode op_mode;
8708   unsigned HOST_WIDE_INT nonzero;
8709
8710   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
8711      code below will do the wrong thing since the mode of such an
8712      expression is VOIDmode.
8713
8714      Also do nothing if X is a CLOBBER; this can happen if X was
8715      the return value from a call to gen_lowpart.  */
8716   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8717     return x;
8718
8719   /* We want to perform the operation in its present mode unless we know
8720      that the operation is valid in MODE, in which case we do the operation
8721      in MODE.  */
8722   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8723               && have_insn_for (code, mode))
8724              ? mode : GET_MODE (x));
8725
8726   /* It is not valid to do a right-shift in a narrower mode
8727      than the one it came in with.  */
8728   if ((code == LSHIFTRT || code == ASHIFTRT)
8729       && partial_subreg_p (mode, GET_MODE (x)))
8730     op_mode = GET_MODE (x);
8731
8732   /* Truncate MASK to fit OP_MODE.  */
8733   if (op_mode)
8734     mask &= GET_MODE_MASK (op_mode);
8735
8736   /* Determine what bits of X are guaranteed to be (non)zero.  */
8737   nonzero = nonzero_bits (x, mode);
8738
8739   /* If none of the bits in X are needed, return a zero.  */
8740   if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8741     x = const0_rtx;
8742
8743   /* If X is a CONST_INT, return a new one.  Do this here since the
8744      test below will fail.  */
8745   if (CONST_INT_P (x))
8746     {
8747       if (SCALAR_INT_MODE_P (mode))
8748         return gen_int_mode (INTVAL (x) & mask, mode);
8749       else
8750         {
8751           x = GEN_INT (INTVAL (x) & mask);
8752           return gen_lowpart_common (mode, x);
8753         }
8754     }
8755
8756   /* If X is narrower than MODE and we want all the bits in X's mode, just
8757      get X in the proper mode.  */
8758   if (paradoxical_subreg_p (mode, GET_MODE (x))
8759       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8760     return gen_lowpart (mode, x);
8761
8762   /* We can ignore the effect of a SUBREG if it narrows the mode or
8763      if the constant masks to zero all the bits the mode doesn't have.  */
8764   if (GET_CODE (x) == SUBREG
8765       && subreg_lowpart_p (x)
8766       && (partial_subreg_p (x)
8767           || (mask
8768               & GET_MODE_MASK (GET_MODE (x))
8769               & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))) == 0))
8770     return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8771
8772   scalar_int_mode int_mode, xmode;
8773   if (is_a <scalar_int_mode> (mode, &int_mode)
8774       && is_a <scalar_int_mode> (GET_MODE (x), &xmode))
8775     /* OP_MODE is either MODE or XMODE, so it must be a scalar
8776        integer too.  */
8777     return force_int_to_mode (x, int_mode, xmode,
8778                               as_a <scalar_int_mode> (op_mode),
8779                               mask, just_select);
8780
8781   return gen_lowpart_or_truncate (mode, x);
8782 }
8783
8784 /* Subroutine of force_to_mode that handles cases in which both X and
8785    the result are scalar integers.  MODE is the mode of the result,
8786    XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8787    is preferred for simplified versions of X.  The other arguments
8788    are as for force_to_mode.  */
8789
8790 static rtx
8791 force_int_to_mode (rtx x, scalar_int_mode mode, scalar_int_mode xmode,
8792                    scalar_int_mode op_mode, unsigned HOST_WIDE_INT mask,
8793                    bool just_select)
8794 {
8795   enum rtx_code code = GET_CODE (x);
8796   bool next_select = just_select || code == XOR || code == NOT || code == NEG;
8797   unsigned HOST_WIDE_INT fuller_mask;
8798   rtx op0, op1, temp;
8799   poly_int64 const_op0;
8800
8801   /* When we have an arithmetic operation, or a shift whose count we
8802      do not know, we need to assume that all bits up to the highest-order
8803      bit in MASK will be needed.  This is how we form such a mask.  */
8804   if (mask & (HOST_WIDE_INT_1U << (HOST_BITS_PER_WIDE_INT - 1)))
8805     fuller_mask = HOST_WIDE_INT_M1U;
8806   else
8807     fuller_mask = ((HOST_WIDE_INT_1U << (floor_log2 (mask) + 1)) - 1);
8808
8809   switch (code)
8810     {
8811     case CLOBBER:
8812       /* If X is a (clobber (const_int)), return it since we know we are
8813          generating something that won't match.  */
8814       return x;
8815
8816     case SIGN_EXTEND:
8817     case ZERO_EXTEND:
8818     case ZERO_EXTRACT:
8819     case SIGN_EXTRACT:
8820       x = expand_compound_operation (x);
8821       if (GET_CODE (x) != code)
8822         return force_to_mode (x, mode, mask, next_select);
8823       break;
8824
8825     case TRUNCATE:
8826       /* Similarly for a truncate.  */
8827       return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8828
8829     case AND:
8830       /* If this is an AND with a constant, convert it into an AND
8831          whose constant is the AND of that constant with MASK.  If it
8832          remains an AND of MASK, delete it since it is redundant.  */
8833
8834       if (CONST_INT_P (XEXP (x, 1)))
8835         {
8836           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8837                                       mask & INTVAL (XEXP (x, 1)));
8838           xmode = op_mode;
8839
8840           /* If X is still an AND, see if it is an AND with a mask that
8841              is just some low-order bits.  If so, and it is MASK, we don't
8842              need it.  */
8843
8844           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8845               && (INTVAL (XEXP (x, 1)) & GET_MODE_MASK (xmode)) == mask)
8846             x = XEXP (x, 0);
8847
8848           /* If it remains an AND, try making another AND with the bits
8849              in the mode mask that aren't in MASK turned on.  If the
8850              constant in the AND is wide enough, this might make a
8851              cheaper constant.  */
8852
8853           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8854               && GET_MODE_MASK (xmode) != mask
8855               && HWI_COMPUTABLE_MODE_P (xmode))
8856             {
8857               unsigned HOST_WIDE_INT cval
8858                 = UINTVAL (XEXP (x, 1)) | (GET_MODE_MASK (xmode) & ~mask);
8859               rtx y;
8860
8861               y = simplify_gen_binary (AND, xmode, XEXP (x, 0),
8862                                        gen_int_mode (cval, xmode));
8863               if (set_src_cost (y, xmode, optimize_this_for_speed_p)
8864                   < set_src_cost (x, xmode, optimize_this_for_speed_p))
8865                 x = y;
8866             }
8867
8868           break;
8869         }
8870
8871       goto binop;
8872
8873     case PLUS:
8874       /* In (and (plus FOO C1) M), if M is a mask that just turns off
8875          low-order bits (as in an alignment operation) and FOO is already
8876          aligned to that boundary, mask C1 to that boundary as well.
8877          This may eliminate that PLUS and, later, the AND.  */
8878
8879       {
8880         unsigned int width = GET_MODE_PRECISION (mode);
8881         unsigned HOST_WIDE_INT smask = mask;
8882
8883         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8884            number, sign extend it.  */
8885
8886         if (width < HOST_BITS_PER_WIDE_INT
8887             && (smask & (HOST_WIDE_INT_1U << (width - 1))) != 0)
8888           smask |= HOST_WIDE_INT_M1U << width;
8889
8890         if (CONST_INT_P (XEXP (x, 1))
8891             && pow2p_hwi (- smask)
8892             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8893             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8894           return force_to_mode (plus_constant (xmode, XEXP (x, 0),
8895                                                (INTVAL (XEXP (x, 1)) & smask)),
8896                                 mode, smask, next_select);
8897       }
8898
8899       /* fall through */
8900
8901     case MULT:
8902       /* Substituting into the operands of a widening MULT is not likely to
8903          create RTL matching a machine insn.  */
8904       if (code == MULT
8905           && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
8906               || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
8907           && (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND
8908               || GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
8909           && REG_P (XEXP (XEXP (x, 0), 0))
8910           && REG_P (XEXP (XEXP (x, 1), 0)))
8911         return gen_lowpart_or_truncate (mode, x);
8912
8913       /* For PLUS, MINUS and MULT, we need any bits less significant than the
8914          most significant bit in MASK since carries from those bits will
8915          affect the bits we are interested in.  */
8916       mask = fuller_mask;
8917       goto binop;
8918
8919     case MINUS:
8920       /* If X is (minus C Y) where C's least set bit is larger than any bit
8921          in the mask, then we may replace with (neg Y).  */
8922       if (poly_int_rtx_p (XEXP (x, 0), &const_op0)
8923           && known_alignment (poly_uint64 (const_op0)) > mask)
8924         {
8925           x = simplify_gen_unary (NEG, xmode, XEXP (x, 1), xmode);
8926           return force_to_mode (x, mode, mask, next_select);
8927         }
8928
8929       /* Similarly, if C contains every bit in the fuller_mask, then we may
8930          replace with (not Y).  */
8931       if (CONST_INT_P (XEXP (x, 0))
8932           && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8933         {
8934           x = simplify_gen_unary (NOT, xmode, XEXP (x, 1), xmode);
8935           return force_to_mode (x, mode, mask, next_select);
8936         }
8937
8938       mask = fuller_mask;
8939       goto binop;
8940
8941     case IOR:
8942     case XOR:
8943       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8944          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8945          operation which may be a bitfield extraction.  Ensure that the
8946          constant we form is not wider than the mode of X.  */
8947
8948       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8949           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8950           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8951           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8952           && CONST_INT_P (XEXP (x, 1))
8953           && ((INTVAL (XEXP (XEXP (x, 0), 1))
8954                + floor_log2 (INTVAL (XEXP (x, 1))))
8955               < GET_MODE_PRECISION (xmode))
8956           && (UINTVAL (XEXP (x, 1))
8957               & ~nonzero_bits (XEXP (x, 0), xmode)) == 0)
8958         {
8959           temp = gen_int_mode ((INTVAL (XEXP (x, 1)) & mask)
8960                                << INTVAL (XEXP (XEXP (x, 0), 1)),
8961                                xmode);
8962           temp = simplify_gen_binary (GET_CODE (x), xmode,
8963                                       XEXP (XEXP (x, 0), 0), temp);
8964           x = simplify_gen_binary (LSHIFTRT, xmode, temp,
8965                                    XEXP (XEXP (x, 0), 1));
8966           return force_to_mode (x, mode, mask, next_select);
8967         }
8968
8969     binop:
8970       /* For most binary operations, just propagate into the operation and
8971          change the mode if we have an operation of that mode.  */
8972
8973       op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8974       op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8975
8976       /* If we ended up truncating both operands, truncate the result of the
8977          operation instead.  */
8978       if (GET_CODE (op0) == TRUNCATE
8979           && GET_CODE (op1) == TRUNCATE)
8980         {
8981           op0 = XEXP (op0, 0);
8982           op1 = XEXP (op1, 0);
8983         }
8984
8985       op0 = gen_lowpart_or_truncate (op_mode, op0);
8986       op1 = gen_lowpart_or_truncate (op_mode, op1);
8987
8988       if (op_mode != xmode || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8989         {
8990           x = simplify_gen_binary (code, op_mode, op0, op1);
8991           xmode = op_mode;
8992         }
8993       break;
8994
8995     case ASHIFT:
8996       /* For left shifts, do the same, but just for the first operand.
8997          However, we cannot do anything with shifts where we cannot
8998          guarantee that the counts are smaller than the size of the mode
8999          because such a count will have a different meaning in a
9000          wider mode.  */
9001
9002       if (! (CONST_INT_P (XEXP (x, 1))
9003              && INTVAL (XEXP (x, 1)) >= 0
9004              && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
9005           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
9006                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
9007                     < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
9008         break;
9009
9010       /* If the shift count is a constant and we can do arithmetic in
9011          the mode of the shift, refine which bits we need.  Otherwise, use the
9012          conservative form of the mask.  */
9013       if (CONST_INT_P (XEXP (x, 1))
9014           && INTVAL (XEXP (x, 1)) >= 0
9015           && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
9016           && HWI_COMPUTABLE_MODE_P (op_mode))
9017         mask >>= INTVAL (XEXP (x, 1));
9018       else
9019         mask = fuller_mask;
9020
9021       op0 = gen_lowpart_or_truncate (op_mode,
9022                                      force_to_mode (XEXP (x, 0), mode,
9023                                                     mask, next_select));
9024
9025       if (op_mode != xmode || op0 != XEXP (x, 0))
9026         {
9027           x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
9028           xmode = op_mode;
9029         }
9030       break;
9031
9032     case LSHIFTRT:
9033       /* Here we can only do something if the shift count is a constant,
9034          this shift constant is valid for the host, and we can do arithmetic
9035          in OP_MODE.  */
9036
9037       if (CONST_INT_P (XEXP (x, 1))
9038           && INTVAL (XEXP (x, 1)) >= 0
9039           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
9040           && HWI_COMPUTABLE_MODE_P (op_mode))
9041         {
9042           rtx inner = XEXP (x, 0);
9043           unsigned HOST_WIDE_INT inner_mask;
9044
9045           /* Select the mask of the bits we need for the shift operand.  */
9046           inner_mask = mask << INTVAL (XEXP (x, 1));
9047
9048           /* We can only change the mode of the shift if we can do arithmetic
9049              in the mode of the shift and INNER_MASK is no wider than the
9050              width of X's mode.  */
9051           if ((inner_mask & ~GET_MODE_MASK (xmode)) != 0)
9052             op_mode = xmode;
9053
9054           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
9055
9056           if (xmode != op_mode || inner != XEXP (x, 0))
9057             {
9058               x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
9059               xmode = op_mode;
9060             }
9061         }
9062
9063       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
9064          shift and AND produces only copies of the sign bit (C2 is one less
9065          than a power of two), we can do this with just a shift.  */
9066
9067       if (GET_CODE (x) == LSHIFTRT
9068           && CONST_INT_P (XEXP (x, 1))
9069           /* The shift puts one of the sign bit copies in the least significant
9070              bit.  */
9071           && ((INTVAL (XEXP (x, 1))
9072                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
9073               >= GET_MODE_PRECISION (xmode))
9074           && pow2p_hwi (mask + 1)
9075           /* Number of bits left after the shift must be more than the mask
9076              needs.  */
9077           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
9078               <= GET_MODE_PRECISION (xmode))
9079           /* Must be more sign bit copies than the mask needs.  */
9080           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
9081               >= exact_log2 (mask + 1)))
9082         {
9083           int nbits = GET_MODE_PRECISION (xmode) - exact_log2 (mask + 1);
9084           x = simplify_gen_binary (LSHIFTRT, xmode, XEXP (x, 0),
9085                                    gen_int_shift_amount (xmode, nbits));
9086         }
9087       goto shiftrt;
9088
9089     case ASHIFTRT:
9090       /* If we are just looking for the sign bit, we don't need this shift at
9091          all, even if it has a variable count.  */
9092       if (val_signbit_p (xmode, mask))
9093         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
9094
9095       /* If this is a shift by a constant, get a mask that contains those bits
9096          that are not copies of the sign bit.  We then have two cases:  If
9097          MASK only includes those bits, this can be a logical shift, which may
9098          allow simplifications.  If MASK is a single-bit field not within
9099          those bits, we are requesting a copy of the sign bit and hence can
9100          shift the sign bit to the appropriate location.  */
9101
9102       if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
9103           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
9104         {
9105           unsigned HOST_WIDE_INT nonzero;
9106           int i;
9107
9108           /* If the considered data is wider than HOST_WIDE_INT, we can't
9109              represent a mask for all its bits in a single scalar.
9110              But we only care about the lower bits, so calculate these.  */
9111
9112           if (GET_MODE_PRECISION (xmode) > HOST_BITS_PER_WIDE_INT)
9113             {
9114               nonzero = HOST_WIDE_INT_M1U;
9115
9116               /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
9117                  is the number of bits a full-width mask would have set.
9118                  We need only shift if these are fewer than nonzero can
9119                  hold.  If not, we must keep all bits set in nonzero.  */
9120
9121               if (GET_MODE_PRECISION (xmode) - INTVAL (XEXP (x, 1))
9122                   < HOST_BITS_PER_WIDE_INT)
9123                 nonzero >>= INTVAL (XEXP (x, 1))
9124                             + HOST_BITS_PER_WIDE_INT
9125                             - GET_MODE_PRECISION (xmode);
9126             }
9127           else
9128             {
9129               nonzero = GET_MODE_MASK (xmode);
9130               nonzero >>= INTVAL (XEXP (x, 1));
9131             }
9132
9133           if ((mask & ~nonzero) == 0)
9134             {
9135               x = simplify_shift_const (NULL_RTX, LSHIFTRT, xmode,
9136                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
9137               if (GET_CODE (x) != ASHIFTRT)
9138                 return force_to_mode (x, mode, mask, next_select);
9139             }
9140
9141           else if ((i = exact_log2 (mask)) >= 0)
9142             {
9143               x = simplify_shift_const
9144                   (NULL_RTX, LSHIFTRT, xmode, XEXP (x, 0),
9145                    GET_MODE_PRECISION (xmode) - 1 - i);
9146
9147               if (GET_CODE (x) != ASHIFTRT)
9148                 return force_to_mode (x, mode, mask, next_select);
9149             }
9150         }
9151
9152       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
9153          even if the shift count isn't a constant.  */
9154       if (mask == 1)
9155         x = simplify_gen_binary (LSHIFTRT, xmode, XEXP (x, 0), XEXP (x, 1));
9156
9157     shiftrt:
9158
9159       /* If this is a zero- or sign-extension operation that just affects bits
9160          we don't care about, remove it.  Be sure the call above returned
9161          something that is still a shift.  */
9162
9163       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
9164           && CONST_INT_P (XEXP (x, 1))
9165           && INTVAL (XEXP (x, 1)) >= 0
9166           && (INTVAL (XEXP (x, 1))
9167               <= GET_MODE_PRECISION (xmode) - (floor_log2 (mask) + 1))
9168           && GET_CODE (XEXP (x, 0)) == ASHIFT
9169           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
9170         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask, next_select);
9171
9172       break;
9173
9174     case ROTATE:
9175     case ROTATERT:
9176       /* If the shift count is constant and we can do computations
9177          in the mode of X, compute where the bits we care about are.
9178          Otherwise, we can't do anything.  Don't change the mode of
9179          the shift or propagate MODE into the shift, though.  */
9180       if (CONST_INT_P (XEXP (x, 1))
9181           && INTVAL (XEXP (x, 1)) >= 0)
9182         {
9183           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
9184                                             xmode, gen_int_mode (mask, xmode),
9185                                             XEXP (x, 1));
9186           if (temp && CONST_INT_P (temp))
9187             x = simplify_gen_binary (code, xmode,
9188                                      force_to_mode (XEXP (x, 0), xmode,
9189                                                     INTVAL (temp), next_select),
9190                                      XEXP (x, 1));
9191         }
9192       break;
9193
9194     case NEG:
9195       /* If we just want the low-order bit, the NEG isn't needed since it
9196          won't change the low-order bit.  */
9197       if (mask == 1)
9198         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
9199
9200       /* We need any bits less significant than the most significant bit in
9201          MASK since carries from those bits will affect the bits we are
9202          interested in.  */
9203       mask = fuller_mask;
9204       goto unop;
9205
9206     case NOT:
9207       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9208          same as the XOR case above.  Ensure that the constant we form is not
9209          wider than the mode of X.  */
9210
9211       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
9212           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
9213           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
9214           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
9215               < GET_MODE_PRECISION (xmode))
9216           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
9217         {
9218           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)), xmode);
9219           temp = simplify_gen_binary (XOR, xmode, XEXP (XEXP (x, 0), 0), temp);
9220           x = simplify_gen_binary (LSHIFTRT, xmode,
9221                                    temp, XEXP (XEXP (x, 0), 1));
9222
9223           return force_to_mode (x, mode, mask, next_select);
9224         }
9225
9226       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9227          use the full mask inside the NOT.  */
9228       mask = fuller_mask;
9229
9230     unop:
9231       op0 = gen_lowpart_or_truncate (op_mode,
9232                                      force_to_mode (XEXP (x, 0), mode, mask,
9233                                                     next_select));
9234       if (op_mode != xmode || op0 != XEXP (x, 0))
9235         {
9236           x = simplify_gen_unary (code, op_mode, op0, op_mode);
9237           xmode = op_mode;
9238         }
9239       break;
9240
9241     case NE:
9242       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9243          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9244          which is equal to STORE_FLAG_VALUE.  */
9245       if ((mask & ~STORE_FLAG_VALUE) == 0
9246           && XEXP (x, 1) == const0_rtx
9247           && GET_MODE (XEXP (x, 0)) == mode
9248           && pow2p_hwi (nonzero_bits (XEXP (x, 0), mode))
9249           && (nonzero_bits (XEXP (x, 0), mode)
9250               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
9251         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
9252
9253       break;
9254
9255     case IF_THEN_ELSE:
9256       /* We have no way of knowing if the IF_THEN_ELSE can itself be
9257          written in a narrower mode.  We play it safe and do not do so.  */
9258
9259       op0 = gen_lowpart_or_truncate (xmode,
9260                                      force_to_mode (XEXP (x, 1), mode,
9261                                                     mask, next_select));
9262       op1 = gen_lowpart_or_truncate (xmode,
9263                                      force_to_mode (XEXP (x, 2), mode,
9264                                                     mask, next_select));
9265       if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2))
9266         x = simplify_gen_ternary (IF_THEN_ELSE, xmode,
9267                                   GET_MODE (XEXP (x, 0)), XEXP (x, 0),
9268                                   op0, op1);
9269       break;
9270
9271     default:
9272       break;
9273     }
9274
9275   /* Ensure we return a value of the proper mode.  */
9276   return gen_lowpart_or_truncate (mode, x);
9277 }
9278 \f
9279 /* Return nonzero if X is an expression that has one of two values depending on
9280    whether some other value is zero or nonzero.  In that case, we return the
9281    value that is being tested, *PTRUE is set to the value if the rtx being
9282    returned has a nonzero value, and *PFALSE is set to the other alternative.
9283
9284    If we return zero, we set *PTRUE and *PFALSE to X.  */
9285
9286 static rtx
9287 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
9288 {
9289   machine_mode mode = GET_MODE (x);
9290   enum rtx_code code = GET_CODE (x);
9291   rtx cond0, cond1, true0, true1, false0, false1;
9292   unsigned HOST_WIDE_INT nz;
9293   scalar_int_mode int_mode;
9294
9295   /* If we are comparing a value against zero, we are done.  */
9296   if ((code == NE || code == EQ)
9297       && XEXP (x, 1) == const0_rtx)
9298     {
9299       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
9300       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
9301       return XEXP (x, 0);
9302     }
9303
9304   /* If this is a unary operation whose operand has one of two values, apply
9305      our opcode to compute those values.  */
9306   else if (UNARY_P (x)
9307            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
9308     {
9309       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
9310       *pfalse = simplify_gen_unary (code, mode, false0,
9311                                     GET_MODE (XEXP (x, 0)));
9312       return cond0;
9313     }
9314
9315   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9316      make can't possibly match and would suppress other optimizations.  */
9317   else if (code == COMPARE)
9318     ;
9319
9320   /* If this is a binary operation, see if either side has only one of two
9321      values.  If either one does or if both do and they are conditional on
9322      the same value, compute the new true and false values.  */
9323   else if (BINARY_P (x))
9324     {
9325       rtx op0 = XEXP (x, 0);
9326       rtx op1 = XEXP (x, 1);
9327       cond0 = if_then_else_cond (op0, &true0, &false0);
9328       cond1 = if_then_else_cond (op1, &true1, &false1);
9329
9330       if ((cond0 != 0 && cond1 != 0 && !rtx_equal_p (cond0, cond1))
9331           && (REG_P (op0) || REG_P (op1)))
9332         {
9333           /* Try to enable a simplification by undoing work done by
9334              if_then_else_cond if it converted a REG into something more
9335              complex.  */
9336           if (REG_P (op0))
9337             {
9338               cond0 = 0;
9339               true0 = false0 = op0;
9340             }
9341           else
9342             {
9343               cond1 = 0;
9344               true1 = false1 = op1;
9345             }
9346         }
9347
9348       if ((cond0 != 0 || cond1 != 0)
9349           && ! (cond0 != 0 && cond1 != 0 && !rtx_equal_p (cond0, cond1)))
9350         {
9351           /* If if_then_else_cond returned zero, then true/false are the
9352              same rtl.  We must copy one of them to prevent invalid rtl
9353              sharing.  */
9354           if (cond0 == 0)
9355             true0 = copy_rtx (true0);
9356           else if (cond1 == 0)
9357             true1 = copy_rtx (true1);
9358
9359           if (COMPARISON_P (x))
9360             {
9361               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
9362                                                 true0, true1);
9363               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
9364                                                  false0, false1);
9365              }
9366           else
9367             {
9368               *ptrue = simplify_gen_binary (code, mode, true0, true1);
9369               *pfalse = simplify_gen_binary (code, mode, false0, false1);
9370             }
9371
9372           return cond0 ? cond0 : cond1;
9373         }
9374
9375       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9376          operands is zero when the other is nonzero, and vice-versa,
9377          and STORE_FLAG_VALUE is 1 or -1.  */
9378
9379       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9380           && (code == PLUS || code == IOR || code == XOR || code == MINUS
9381               || code == UMAX)
9382           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
9383         {
9384           rtx op0 = XEXP (XEXP (x, 0), 1);
9385           rtx op1 = XEXP (XEXP (x, 1), 1);
9386
9387           cond0 = XEXP (XEXP (x, 0), 0);
9388           cond1 = XEXP (XEXP (x, 1), 0);
9389
9390           if (COMPARISON_P (cond0)
9391               && COMPARISON_P (cond1)
9392               && SCALAR_INT_MODE_P (mode)
9393               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
9394                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
9395                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
9396                   || ((swap_condition (GET_CODE (cond0))
9397                        == reversed_comparison_code (cond1, NULL))
9398                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
9399                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
9400               && ! side_effects_p (x))
9401             {
9402               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
9403               *pfalse = simplify_gen_binary (MULT, mode,
9404                                              (code == MINUS
9405                                               ? simplify_gen_unary (NEG, mode,
9406                                                                     op1, mode)
9407                                               : op1),
9408                                               const_true_rtx);
9409               return cond0;
9410             }
9411         }
9412
9413       /* Similarly for MULT, AND and UMIN, except that for these the result
9414          is always zero.  */
9415       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9416           && (code == MULT || code == AND || code == UMIN)
9417           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
9418         {
9419           cond0 = XEXP (XEXP (x, 0), 0);
9420           cond1 = XEXP (XEXP (x, 1), 0);
9421
9422           if (COMPARISON_P (cond0)
9423               && COMPARISON_P (cond1)
9424               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
9425                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
9426                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
9427                   || ((swap_condition (GET_CODE (cond0))
9428                        == reversed_comparison_code (cond1, NULL))
9429                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
9430                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
9431               && ! side_effects_p (x))
9432             {
9433               *ptrue = *pfalse = const0_rtx;
9434               return cond0;
9435             }
9436         }
9437     }
9438
9439   else if (code == IF_THEN_ELSE)
9440     {
9441       /* If we have IF_THEN_ELSE already, extract the condition and
9442          canonicalize it if it is NE or EQ.  */
9443       cond0 = XEXP (x, 0);
9444       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
9445       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
9446         return XEXP (cond0, 0);
9447       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
9448         {
9449           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
9450           return XEXP (cond0, 0);
9451         }
9452       else
9453         return cond0;
9454     }
9455
9456   /* If X is a SUBREG, we can narrow both the true and false values
9457      if the inner expression, if there is a condition.  */
9458   else if (code == SUBREG
9459            && (cond0 = if_then_else_cond (SUBREG_REG (x), &true0,
9460                                           &false0)) != 0)
9461     {
9462       true0 = simplify_gen_subreg (mode, true0,
9463                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
9464       false0 = simplify_gen_subreg (mode, false0,
9465                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
9466       if (true0 && false0)
9467         {
9468           *ptrue = true0;
9469           *pfalse = false0;
9470           return cond0;
9471         }
9472     }
9473
9474   /* If X is a constant, this isn't special and will cause confusions
9475      if we treat it as such.  Likewise if it is equivalent to a constant.  */
9476   else if (CONSTANT_P (x)
9477            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
9478     ;
9479
9480   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9481      will be least confusing to the rest of the compiler.  */
9482   else if (mode == BImode)
9483     {
9484       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
9485       return x;
9486     }
9487
9488   /* If X is known to be either 0 or -1, those are the true and
9489      false values when testing X.  */
9490   else if (x == constm1_rtx || x == const0_rtx
9491            || (is_a <scalar_int_mode> (mode, &int_mode)
9492                && (num_sign_bit_copies (x, int_mode)
9493                    == GET_MODE_PRECISION (int_mode))))
9494     {
9495       *ptrue = constm1_rtx, *pfalse = const0_rtx;
9496       return x;
9497     }
9498
9499   /* Likewise for 0 or a single bit.  */
9500   else if (HWI_COMPUTABLE_MODE_P (mode)
9501            && pow2p_hwi (nz = nonzero_bits (x, mode)))
9502     {
9503       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
9504       return x;
9505     }
9506
9507   /* Otherwise fail; show no condition with true and false values the same.  */
9508   *ptrue = *pfalse = x;
9509   return 0;
9510 }
9511 \f
9512 /* Return the value of expression X given the fact that condition COND
9513    is known to be true when applied to REG as its first operand and VAL
9514    as its second.  X is known to not be shared and so can be modified in
9515    place.
9516
9517    We only handle the simplest cases, and specifically those cases that
9518    arise with IF_THEN_ELSE expressions.  */
9519
9520 static rtx
9521 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
9522 {
9523   enum rtx_code code = GET_CODE (x);
9524   const char *fmt;
9525   int i, j;
9526
9527   if (side_effects_p (x))
9528     return x;
9529
9530   /* If either operand of the condition is a floating point value,
9531      then we have to avoid collapsing an EQ comparison.  */
9532   if (cond == EQ
9533       && rtx_equal_p (x, reg)
9534       && ! FLOAT_MODE_P (GET_MODE (x))
9535       && ! FLOAT_MODE_P (GET_MODE (val)))
9536     return val;
9537
9538   if (cond == UNEQ && rtx_equal_p (x, reg))
9539     return val;
9540
9541   /* If X is (abs REG) and we know something about REG's relationship
9542      with zero, we may be able to simplify this.  */
9543
9544   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
9545     switch (cond)
9546       {
9547       case GE:  case GT:  case EQ:
9548         return XEXP (x, 0);
9549       case LT:  case LE:
9550         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
9551                                    XEXP (x, 0),
9552                                    GET_MODE (XEXP (x, 0)));
9553       default:
9554         break;
9555       }
9556
9557   /* The only other cases we handle are MIN, MAX, and comparisons if the
9558      operands are the same as REG and VAL.  */
9559
9560   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
9561     {
9562       if (rtx_equal_p (XEXP (x, 0), val))
9563         {
9564           std::swap (val, reg);
9565           cond = swap_condition (cond);
9566         }
9567
9568       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
9569         {
9570           if (COMPARISON_P (x))
9571             {
9572               if (comparison_dominates_p (cond, code))
9573                 return VECTOR_MODE_P (GET_MODE (x)) ? x : const_true_rtx;
9574
9575               code = reversed_comparison_code (x, NULL);
9576               if (code != UNKNOWN
9577                   && comparison_dominates_p (cond, code))
9578                 return CONST0_RTX (GET_MODE (x));
9579               else
9580                 return x;
9581             }
9582           else if (code == SMAX || code == SMIN
9583                    || code == UMIN || code == UMAX)
9584             {
9585               int unsignedp = (code == UMIN || code == UMAX);
9586
9587               /* Do not reverse the condition when it is NE or EQ.
9588                  This is because we cannot conclude anything about
9589                  the value of 'SMAX (x, y)' when x is not equal to y,
9590                  but we can when x equals y.  */
9591               if ((code == SMAX || code == UMAX)
9592                   && ! (cond == EQ || cond == NE))
9593                 cond = reverse_condition (cond);
9594
9595               switch (cond)
9596                 {
9597                 case GE:   case GT:
9598                   return unsignedp ? x : XEXP (x, 1);
9599                 case LE:   case LT:
9600                   return unsignedp ? x : XEXP (x, 0);
9601                 case GEU:  case GTU:
9602                   return unsignedp ? XEXP (x, 1) : x;
9603                 case LEU:  case LTU:
9604                   return unsignedp ? XEXP (x, 0) : x;
9605                 default:
9606                   break;
9607                 }
9608             }
9609         }
9610     }
9611   else if (code == SUBREG)
9612     {
9613       machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
9614       rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
9615
9616       if (SUBREG_REG (x) != r)
9617         {
9618           /* We must simplify subreg here, before we lose track of the
9619              original inner_mode.  */
9620           new_rtx = simplify_subreg (GET_MODE (x), r,
9621                                      inner_mode, SUBREG_BYTE (x));
9622           if (new_rtx)
9623             return new_rtx;
9624           else
9625             SUBST (SUBREG_REG (x), r);
9626         }
9627
9628       return x;
9629     }
9630   /* We don't have to handle SIGN_EXTEND here, because even in the
9631      case of replacing something with a modeless CONST_INT, a
9632      CONST_INT is already (supposed to be) a valid sign extension for
9633      its narrower mode, which implies it's already properly
9634      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
9635      story is different.  */
9636   else if (code == ZERO_EXTEND)
9637     {
9638       machine_mode inner_mode = GET_MODE (XEXP (x, 0));
9639       rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
9640
9641       if (XEXP (x, 0) != r)
9642         {
9643           /* We must simplify the zero_extend here, before we lose
9644              track of the original inner_mode.  */
9645           new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
9646                                               r, inner_mode);
9647           if (new_rtx)
9648             return new_rtx;
9649           else
9650             SUBST (XEXP (x, 0), r);
9651         }
9652
9653       return x;
9654     }
9655
9656   fmt = GET_RTX_FORMAT (code);
9657   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9658     {
9659       if (fmt[i] == 'e')
9660         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
9661       else if (fmt[i] == 'E')
9662         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9663           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
9664                                                 cond, reg, val));
9665     }
9666
9667   return x;
9668 }
9669 \f
9670 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9671    assignment as a field assignment.  */
9672
9673 static bool
9674 rtx_equal_for_field_assignment_p (rtx x, rtx y, bool widen_x)
9675 {
9676   if (widen_x && GET_MODE (x) != GET_MODE (y))
9677     {
9678       if (paradoxical_subreg_p (GET_MODE (x), GET_MODE (y)))
9679         return false;
9680       if (BYTES_BIG_ENDIAN != WORDS_BIG_ENDIAN)
9681         return false;
9682       x = adjust_address_nv (x, GET_MODE (y),
9683                              byte_lowpart_offset (GET_MODE (y),
9684                                                   GET_MODE (x)));
9685     }
9686
9687   if (x == y || rtx_equal_p (x, y))
9688     return true;
9689
9690   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
9691     return false;
9692
9693   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9694      Note that all SUBREGs of MEM are paradoxical; otherwise they
9695      would have been rewritten.  */
9696   if (MEM_P (x) && GET_CODE (y) == SUBREG
9697       && MEM_P (SUBREG_REG (y))
9698       && rtx_equal_p (SUBREG_REG (y),
9699                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
9700     return true;
9701
9702   if (MEM_P (y) && GET_CODE (x) == SUBREG
9703       && MEM_P (SUBREG_REG (x))
9704       && rtx_equal_p (SUBREG_REG (x),
9705                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
9706     return true;
9707
9708   /* We used to see if get_last_value of X and Y were the same but that's
9709      not correct.  In one direction, we'll cause the assignment to have
9710      the wrong destination and in the case, we'll import a register into this
9711      insn that might have already have been dead.   So fail if none of the
9712      above cases are true.  */
9713   return false;
9714 }
9715 \f
9716 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9717    Return that assignment if so.
9718
9719    We only handle the most common cases.  */
9720
9721 static rtx
9722 make_field_assignment (rtx x)
9723 {
9724   rtx dest = SET_DEST (x);
9725   rtx src = SET_SRC (x);
9726   rtx assign;
9727   rtx rhs, lhs;
9728   HOST_WIDE_INT c1;
9729   HOST_WIDE_INT pos;
9730   unsigned HOST_WIDE_INT len;
9731   rtx other;
9732
9733   /* All the rules in this function are specific to scalar integers.  */
9734   scalar_int_mode mode;
9735   if (!is_a <scalar_int_mode> (GET_MODE (dest), &mode))
9736     return x;
9737
9738   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9739      a clear of a one-bit field.  We will have changed it to
9740      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
9741      for a SUBREG.  */
9742
9743   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
9744       && CONST_INT_P (XEXP (XEXP (src, 0), 0))
9745       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
9746       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9747     {
9748       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9749                                 1, true, true, false);
9750       if (assign != 0)
9751         return gen_rtx_SET (assign, const0_rtx);
9752       return x;
9753     }
9754
9755   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
9756       && subreg_lowpart_p (XEXP (src, 0))
9757       && partial_subreg_p (XEXP (src, 0))
9758       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
9759       && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
9760       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
9761       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9762     {
9763       assign = make_extraction (VOIDmode, dest, 0,
9764                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9765                                 1, true, true, false);
9766       if (assign != 0)
9767         return gen_rtx_SET (assign, const0_rtx);
9768       return x;
9769     }
9770
9771   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9772      one-bit field.  */
9773   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9774       && XEXP (XEXP (src, 0), 0) == const1_rtx
9775       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9776     {
9777       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9778                                 1, true, true, false);
9779       if (assign != 0)
9780         return gen_rtx_SET (assign, const1_rtx);
9781       return x;
9782     }
9783
9784   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9785      SRC is an AND with all bits of that field set, then we can discard
9786      the AND.  */
9787   if (GET_CODE (dest) == ZERO_EXTRACT
9788       && CONST_INT_P (XEXP (dest, 1))
9789       && GET_CODE (src) == AND
9790       && CONST_INT_P (XEXP (src, 1)))
9791     {
9792       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9793       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9794       unsigned HOST_WIDE_INT ze_mask;
9795
9796       if (width >= HOST_BITS_PER_WIDE_INT)
9797         ze_mask = -1;
9798       else
9799         ze_mask = (HOST_WIDE_INT_1U << width) - 1;
9800
9801       /* Complete overlap.  We can remove the source AND.  */
9802       if ((and_mask & ze_mask) == ze_mask)
9803         return gen_rtx_SET (dest, XEXP (src, 0));
9804
9805       /* Partial overlap.  We can reduce the source AND.  */
9806       if ((and_mask & ze_mask) != and_mask)
9807         {
9808           src = gen_rtx_AND (mode, XEXP (src, 0),
9809                              gen_int_mode (and_mask & ze_mask, mode));
9810           return gen_rtx_SET (dest, src);
9811         }
9812     }
9813
9814   /* The other case we handle is assignments into a constant-position
9815      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
9816      a mask that has all one bits except for a group of zero bits and
9817      OTHER is known to have zeros where C1 has ones, this is such an
9818      assignment.  Compute the position and length from C1.  Shift OTHER
9819      to the appropriate position, force it to the required mode, and
9820      make the extraction.  Check for the AND in both operands.  */
9821
9822   /* One or more SUBREGs might obscure the constant-position field
9823      assignment.  The first one we are likely to encounter is an outer
9824      narrowing SUBREG, which we can just strip for the purposes of
9825      identifying the constant-field assignment.  */
9826   scalar_int_mode src_mode = mode;
9827   if (GET_CODE (src) == SUBREG
9828       && subreg_lowpart_p (src)
9829       && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (src)), &src_mode))
9830     src = SUBREG_REG (src);
9831
9832   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9833     return x;
9834
9835   rhs = expand_compound_operation (XEXP (src, 0));
9836   lhs = expand_compound_operation (XEXP (src, 1));
9837
9838   if (GET_CODE (rhs) == AND
9839       && CONST_INT_P (XEXP (rhs, 1))
9840       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9841     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9842   /* The second SUBREG that might get in the way is a paradoxical
9843      SUBREG around the first operand of the AND.  We want to
9844      pretend the operand is as wide as the destination here.   We
9845      do this by adjusting the MEM to wider mode for the sole
9846      purpose of the call to rtx_equal_for_field_assignment_p.   Also
9847      note this trick only works for MEMs.  */
9848   else if (GET_CODE (rhs) == AND
9849            && paradoxical_subreg_p (XEXP (rhs, 0))
9850            && MEM_P (SUBREG_REG (XEXP (rhs, 0)))
9851            && CONST_INT_P (XEXP (rhs, 1))
9852            && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs, 0)),
9853                                                 dest, true))
9854     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9855   else if (GET_CODE (lhs) == AND
9856            && CONST_INT_P (XEXP (lhs, 1))
9857            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9858     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9859   /* The second SUBREG that might get in the way is a paradoxical
9860      SUBREG around the first operand of the AND.  We want to
9861      pretend the operand is as wide as the destination here.   We
9862      do this by adjusting the MEM to wider mode for the sole
9863      purpose of the call to rtx_equal_for_field_assignment_p.   Also
9864      note this trick only works for MEMs.  */
9865   else if (GET_CODE (lhs) == AND
9866            && paradoxical_subreg_p (XEXP (lhs, 0))
9867            && MEM_P (SUBREG_REG (XEXP (lhs, 0)))
9868            && CONST_INT_P (XEXP (lhs, 1))
9869            && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs, 0)),
9870                                                 dest, true))
9871     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9872   else
9873     return x;
9874
9875   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (mode), &len);
9876   if (pos < 0
9877       || pos + len > GET_MODE_PRECISION (mode)
9878       || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
9879       || (c1 & nonzero_bits (other, mode)) != 0)
9880     return x;
9881
9882   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len,
9883                             true, true, false);
9884   if (assign == 0)
9885     return x;
9886
9887   /* The mode to use for the source is the mode of the assignment, or of
9888      what is inside a possible STRICT_LOW_PART.  */
9889   machine_mode new_mode = (GET_CODE (assign) == STRICT_LOW_PART
9890                            ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9891
9892   /* Shift OTHER right POS places and make it the source, restricting it
9893      to the proper length and mode.  */
9894
9895   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9896                                                      src_mode, other, pos),
9897                                dest);
9898   src = force_to_mode (src, new_mode,
9899                        len >= HOST_BITS_PER_WIDE_INT
9900                        ? HOST_WIDE_INT_M1U
9901                        : (HOST_WIDE_INT_1U << len) - 1, false);
9902
9903   /* If SRC is masked by an AND that does not make a difference in
9904      the value being stored, strip it.  */
9905   if (GET_CODE (assign) == ZERO_EXTRACT
9906       && CONST_INT_P (XEXP (assign, 1))
9907       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9908       && GET_CODE (src) == AND
9909       && CONST_INT_P (XEXP (src, 1))
9910       && UINTVAL (XEXP (src, 1))
9911          == (HOST_WIDE_INT_1U << INTVAL (XEXP (assign, 1))) - 1)
9912     src = XEXP (src, 0);
9913
9914   return gen_rtx_SET (assign, src);
9915 }
9916 \f
9917 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9918    if so.  */
9919
9920 static rtx
9921 apply_distributive_law (rtx x)
9922 {
9923   enum rtx_code code = GET_CODE (x);
9924   enum rtx_code inner_code;
9925   rtx lhs, rhs, other;
9926   rtx tem;
9927
9928   /* Distributivity is not true for floating point as it can change the
9929      value.  So we don't do it unless -funsafe-math-optimizations.  */
9930   if (FLOAT_MODE_P (GET_MODE (x))
9931       && ! flag_unsafe_math_optimizations)
9932     return x;
9933
9934   /* The outer operation can only be one of the following:  */
9935   if (code != IOR && code != AND && code != XOR
9936       && code != PLUS && code != MINUS)
9937     return x;
9938
9939   lhs = XEXP (x, 0);
9940   rhs = XEXP (x, 1);
9941
9942   /* If either operand is a primitive we can't do anything, so get out
9943      fast.  */
9944   if (OBJECT_P (lhs) || OBJECT_P (rhs))
9945     return x;
9946
9947   lhs = expand_compound_operation (lhs);
9948   rhs = expand_compound_operation (rhs);
9949   inner_code = GET_CODE (lhs);
9950   if (inner_code != GET_CODE (rhs))
9951     return x;
9952
9953   /* See if the inner and outer operations distribute.  */
9954   switch (inner_code)
9955     {
9956     case LSHIFTRT:
9957     case ASHIFTRT:
9958     case AND:
9959     case IOR:
9960       /* These all distribute except over PLUS.  */
9961       if (code == PLUS || code == MINUS)
9962         return x;
9963       break;
9964
9965     case MULT:
9966       if (code != PLUS && code != MINUS)
9967         return x;
9968       break;
9969
9970     case ASHIFT:
9971       /* This is also a multiply, so it distributes over everything.  */
9972       break;
9973
9974     /* This used to handle SUBREG, but this turned out to be counter-
9975        productive, since (subreg (op ...)) usually is not handled by
9976        insn patterns, and this "optimization" therefore transformed
9977        recognizable patterns into unrecognizable ones.  Therefore the
9978        SUBREG case was removed from here.
9979
9980        It is possible that distributing SUBREG over arithmetic operations
9981        leads to an intermediate result than can then be optimized further,
9982        e.g. by moving the outer SUBREG to the other side of a SET as done
9983        in simplify_set.  This seems to have been the original intent of
9984        handling SUBREGs here.
9985
9986        However, with current GCC this does not appear to actually happen,
9987        at least on major platforms.  If some case is found where removing
9988        the SUBREG case here prevents follow-on optimizations, distributing
9989        SUBREGs ought to be re-added at that place, e.g. in simplify_set.  */
9990
9991     default:
9992       return x;
9993     }
9994
9995   /* Set LHS and RHS to the inner operands (A and B in the example
9996      above) and set OTHER to the common operand (C in the example).
9997      There is only one way to do this unless the inner operation is
9998      commutative.  */
9999   if (COMMUTATIVE_ARITH_P (lhs)
10000       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
10001     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
10002   else if (COMMUTATIVE_ARITH_P (lhs)
10003            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
10004     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
10005   else if (COMMUTATIVE_ARITH_P (lhs)
10006            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
10007     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
10008   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
10009     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
10010   else
10011     return x;
10012
10013   /* Form the new inner operation, seeing if it simplifies first.  */
10014   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
10015
10016   /* There is one exception to the general way of distributing:
10017      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
10018   if (code == XOR && inner_code == IOR)
10019     {
10020       inner_code = AND;
10021       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
10022     }
10023
10024   /* We may be able to continuing distributing the result, so call
10025      ourselves recursively on the inner operation before forming the
10026      outer operation, which we return.  */
10027   return simplify_gen_binary (inner_code, GET_MODE (x),
10028                               apply_distributive_law (tem), other);
10029 }
10030
10031 /* See if X is of the form (* (+ A B) C), and if so convert to
10032    (+ (* A C) (* B C)) and try to simplify.
10033
10034    Most of the time, this results in no change.  However, if some of
10035    the operands are the same or inverses of each other, simplifications
10036    will result.
10037
10038    For example, (and (ior A B) (not B)) can occur as the result of
10039    expanding a bit field assignment.  When we apply the distributive
10040    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
10041    which then simplifies to (and (A (not B))).
10042
10043    Note that no checks happen on the validity of applying the inverse
10044    distributive law.  This is pointless since we can do it in the
10045    few places where this routine is called.
10046
10047    N is the index of the term that is decomposed (the arithmetic operation,
10048    i.e. (+ A B) in the first example above).  !N is the index of the term that
10049    is distributed, i.e. of C in the first example above.  */
10050 static rtx
10051 distribute_and_simplify_rtx (rtx x, int n)
10052 {
10053   machine_mode mode;
10054   enum rtx_code outer_code, inner_code;
10055   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
10056
10057   /* Distributivity is not true for floating point as it can change the
10058      value.  So we don't do it unless -funsafe-math-optimizations.  */
10059   if (FLOAT_MODE_P (GET_MODE (x))
10060       && ! flag_unsafe_math_optimizations)
10061     return NULL_RTX;
10062
10063   decomposed = XEXP (x, n);
10064   if (!ARITHMETIC_P (decomposed))
10065     return NULL_RTX;
10066
10067   mode = GET_MODE (x);
10068   outer_code = GET_CODE (x);
10069   distributed = XEXP (x, !n);
10070
10071   inner_code = GET_CODE (decomposed);
10072   inner_op0 = XEXP (decomposed, 0);
10073   inner_op1 = XEXP (decomposed, 1);
10074
10075   /* Special case (and (xor B C) (not A)), which is equivalent to
10076      (xor (ior A B) (ior A C))  */
10077   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
10078     {
10079       distributed = XEXP (distributed, 0);
10080       outer_code = IOR;
10081     }
10082
10083   if (n == 0)
10084     {
10085       /* Distribute the second term.  */
10086       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
10087       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
10088     }
10089   else
10090     {
10091       /* Distribute the first term.  */
10092       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
10093       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
10094     }
10095
10096   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
10097                                                      new_op0, new_op1));
10098   if (GET_CODE (tmp) != outer_code
10099       && (set_src_cost (tmp, mode, optimize_this_for_speed_p)
10100           < set_src_cost (x, mode, optimize_this_for_speed_p)))
10101     return tmp;
10102
10103   return NULL_RTX;
10104 }
10105 \f
10106 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
10107    in MODE.  Return an equivalent form, if different from (and VAROP
10108    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
10109
10110 static rtx
10111 simplify_and_const_int_1 (scalar_int_mode mode, rtx varop,
10112                           unsigned HOST_WIDE_INT constop)
10113 {
10114   unsigned HOST_WIDE_INT nonzero;
10115   unsigned HOST_WIDE_INT orig_constop;
10116   rtx orig_varop;
10117   int i;
10118
10119   orig_varop = varop;
10120   orig_constop = constop;
10121   if (GET_CODE (varop) == CLOBBER)
10122     return NULL_RTX;
10123
10124   /* Simplify VAROP knowing that we will be only looking at some of the
10125      bits in it.
10126
10127      Note by passing in CONSTOP, we guarantee that the bits not set in
10128      CONSTOP are not significant and will never be examined.  We must
10129      ensure that is the case by explicitly masking out those bits
10130      before returning.  */
10131   varop = force_to_mode (varop, mode, constop, false);
10132
10133   /* If VAROP is a CLOBBER, we will fail so return it.  */
10134   if (GET_CODE (varop) == CLOBBER)
10135     return varop;
10136
10137   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10138      to VAROP and return the new constant.  */
10139   if (CONST_INT_P (varop))
10140     return gen_int_mode (INTVAL (varop) & constop, mode);
10141
10142   /* See what bits may be nonzero in VAROP.  Unlike the general case of
10143      a call to nonzero_bits, here we don't care about bits outside
10144      MODE unless WORD_REGISTER_OPERATIONS is true.  */
10145
10146   scalar_int_mode tmode = mode;
10147   if (WORD_REGISTER_OPERATIONS && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
10148     tmode = word_mode;
10149   nonzero = nonzero_bits (varop, tmode) & GET_MODE_MASK (tmode);
10150
10151   /* Turn off all bits in the constant that are known to already be zero.
10152      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10153      which is tested below.  */
10154
10155   constop &= nonzero;
10156
10157   /* If we don't have any bits left, return zero.  */
10158   if (constop == 0 && !side_effects_p (varop))
10159     return const0_rtx;
10160
10161   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10162      a power of two, we can replace this with an ASHIFT.  */
10163   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), tmode) == 1
10164       && (i = exact_log2 (constop)) >= 0)
10165     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
10166
10167   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10168      or XOR, then try to apply the distributive law.  This may eliminate
10169      operations if either branch can be simplified because of the AND.
10170      It may also make some cases more complex, but those cases probably
10171      won't match a pattern either with or without this.  */
10172
10173   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
10174     {
10175       scalar_int_mode varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10176       return
10177         gen_lowpart
10178           (mode,
10179            apply_distributive_law
10180            (simplify_gen_binary (GET_CODE (varop), varop_mode,
10181                                  simplify_and_const_int (NULL_RTX, varop_mode,
10182                                                          XEXP (varop, 0),
10183                                                          constop),
10184                                  simplify_and_const_int (NULL_RTX, varop_mode,
10185                                                          XEXP (varop, 1),
10186                                                          constop))));
10187     }
10188
10189   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10190      the AND and see if one of the operands simplifies to zero.  If so, we
10191      may eliminate it.  */
10192
10193   if (GET_CODE (varop) == PLUS
10194       && pow2p_hwi (constop + 1))
10195     {
10196       rtx o0, o1;
10197
10198       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
10199       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
10200       if (o0 == const0_rtx)
10201         return o1;
10202       if (o1 == const0_rtx)
10203         return o0;
10204     }
10205
10206   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
10207   varop = gen_lowpart (mode, varop);
10208   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10209     return NULL_RTX;
10210
10211   /* If we are only masking insignificant bits, return VAROP.  */
10212   if (constop == nonzero)
10213     return varop;
10214
10215   if (varop == orig_varop && constop == orig_constop)
10216     return NULL_RTX;
10217
10218   /* Otherwise, return an AND.  */
10219   return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
10220 }
10221
10222
10223 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10224    in MODE.
10225
10226    Return an equivalent form, if different from X.  Otherwise, return X.  If
10227    X is zero, we are to always construct the equivalent form.  */
10228
10229 static rtx
10230 simplify_and_const_int (rtx x, scalar_int_mode mode, rtx varop,
10231                         unsigned HOST_WIDE_INT constop)
10232 {
10233   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
10234   if (tem)
10235     return tem;
10236
10237   if (!x)
10238     x = simplify_gen_binary (AND, GET_MODE (varop), varop,
10239                              gen_int_mode (constop, mode));
10240   if (GET_MODE (x) != mode)
10241     x = gen_lowpart (mode, x);
10242   return x;
10243 }
10244 \f
10245 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10246    We don't care about bits outside of those defined in MODE.
10247    We DO care about all the bits in MODE, even if XMODE is smaller than MODE.
10248
10249    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10250    a shift, AND, or zero_extract, we can do better.  */
10251
10252 static rtx
10253 reg_nonzero_bits_for_combine (const_rtx x, scalar_int_mode xmode,
10254                               scalar_int_mode mode,
10255                               unsigned HOST_WIDE_INT *nonzero)
10256 {
10257   rtx tem;
10258   reg_stat_type *rsp;
10259
10260   /* If X is a register whose nonzero bits value is current, use it.
10261      Otherwise, if X is a register whose value we can find, use that
10262      value.  Otherwise, use the previously-computed global nonzero bits
10263      for this register.  */
10264
10265   rsp = &reg_stat[REGNO (x)];
10266   if (rsp->last_set_value != 0
10267       && (rsp->last_set_mode == mode
10268           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
10269               && GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
10270               && GET_MODE_CLASS (mode) == MODE_INT))
10271       && ((rsp->last_set_label >= label_tick_ebb_start
10272            && rsp->last_set_label < label_tick)
10273           || (rsp->last_set_label == label_tick
10274               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
10275           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
10276               && REGNO (x) < reg_n_sets_max
10277               && REG_N_SETS (REGNO (x)) == 1
10278               && !REGNO_REG_SET_P
10279                   (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
10280                    REGNO (x)))))
10281     {
10282       /* Note that, even if the precision of last_set_mode is lower than that
10283          of mode, record_value_for_reg invoked nonzero_bits on the register
10284          with nonzero_bits_mode (because last_set_mode is necessarily integral
10285          and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10286          are all valid, hence in mode too since nonzero_bits_mode is defined
10287          to the largest HWI_COMPUTABLE_MODE_P mode.  */
10288       *nonzero &= rsp->last_set_nonzero_bits;
10289       return NULL;
10290     }
10291
10292   tem = get_last_value (x);
10293   if (tem)
10294     {
10295       if (SHORT_IMMEDIATES_SIGN_EXTEND)
10296         tem = sign_extend_short_imm (tem, xmode, GET_MODE_PRECISION (mode));
10297
10298       return tem;
10299     }
10300
10301   if (nonzero_sign_valid && rsp->nonzero_bits)
10302     {
10303       unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
10304
10305       if (GET_MODE_PRECISION (xmode) < GET_MODE_PRECISION (mode))
10306         /* We don't know anything about the upper bits.  */
10307         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (xmode);
10308
10309       *nonzero &= mask;
10310     }
10311
10312   return NULL;
10313 }
10314
10315 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10316    end of X that are known to be equal to the sign bit.  X will be used
10317    in mode MODE; the returned value will always be between 1 and the
10318    number of bits in MODE.  */
10319
10320 static rtx
10321 reg_num_sign_bit_copies_for_combine (const_rtx x, scalar_int_mode xmode,
10322                                      scalar_int_mode mode,
10323                                      unsigned int *result)
10324 {
10325   rtx tem;
10326   reg_stat_type *rsp;
10327
10328   rsp = &reg_stat[REGNO (x)];
10329   if (rsp->last_set_value != 0
10330       && rsp->last_set_mode == mode
10331       && ((rsp->last_set_label >= label_tick_ebb_start
10332            && rsp->last_set_label < label_tick)
10333           || (rsp->last_set_label == label_tick
10334               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
10335           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
10336               && REGNO (x) < reg_n_sets_max
10337               && REG_N_SETS (REGNO (x)) == 1
10338               && !REGNO_REG_SET_P
10339                   (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
10340                    REGNO (x)))))
10341     {
10342       *result = rsp->last_set_sign_bit_copies;
10343       return NULL;
10344     }
10345
10346   tem = get_last_value (x);
10347   if (tem != 0)
10348     return tem;
10349
10350   if (nonzero_sign_valid && rsp->sign_bit_copies != 0
10351       && GET_MODE_PRECISION (xmode) == GET_MODE_PRECISION (mode))
10352     *result = rsp->sign_bit_copies;
10353
10354   return NULL;
10355 }
10356 \f
10357 /* Return the number of "extended" bits there are in X, when interpreted
10358    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
10359    unsigned quantities, this is the number of high-order zero bits.
10360    For signed quantities, this is the number of copies of the sign bit
10361    minus 1.  In both case, this function returns the number of "spare"
10362    bits.  For example, if two quantities for which this function returns
10363    at least 1 are added, the addition is known not to overflow.
10364
10365    This function will always return 0 unless called during combine, which
10366    implies that it must be called from a define_split.  */
10367
10368 unsigned int
10369 extended_count (const_rtx x, machine_mode mode, bool unsignedp)
10370 {
10371   if (nonzero_sign_valid == 0)
10372     return 0;
10373
10374   scalar_int_mode int_mode;
10375   return (unsignedp
10376           ? (is_a <scalar_int_mode> (mode, &int_mode)
10377              && HWI_COMPUTABLE_MODE_P (int_mode)
10378              ? (unsigned int) (GET_MODE_PRECISION (int_mode) - 1
10379                                - floor_log2 (nonzero_bits (x, int_mode)))
10380              : 0)
10381           : num_sign_bit_copies (x, mode) - 1);
10382 }
10383
10384 /* This function is called from `simplify_shift_const' to merge two
10385    outer operations.  Specifically, we have already found that we need
10386    to perform operation *POP0 with constant *PCONST0 at the outermost
10387    position.  We would now like to also perform OP1 with constant CONST1
10388    (with *POP0 being done last).
10389
10390    Return true if we can do the operation and update *POP0 and *PCONST0 with
10391    the resulting operation.  *PCOMP_P is set to true if we would need to
10392    complement the innermost operand, otherwise it is unchanged.
10393
10394    MODE is the mode in which the operation will be done.  No bits outside
10395    the width of this mode matter.  It is assumed that the width of this mode
10396    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10397
10398    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
10399    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
10400    result is simply *PCONST0.
10401
10402    If the resulting operation cannot be expressed as one operation, we
10403    return false and do not change *POP0, *PCONST0, and *PCOMP_P.  */
10404
10405 static bool
10406 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0,
10407                  enum rtx_code op1, HOST_WIDE_INT const1,
10408                  machine_mode mode, bool *pcomp_p)
10409 {
10410   enum rtx_code op0 = *pop0;
10411   HOST_WIDE_INT const0 = *pconst0;
10412
10413   const0 &= GET_MODE_MASK (mode);
10414   const1 &= GET_MODE_MASK (mode);
10415
10416   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
10417   if (op0 == AND)
10418     const1 &= const0;
10419
10420   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
10421      if OP0 is SET.  */
10422
10423   if (op1 == UNKNOWN || op0 == SET)
10424     return true;
10425
10426   else if (op0 == UNKNOWN)
10427     op0 = op1, const0 = const1;
10428
10429   else if (op0 == op1)
10430     {
10431       switch (op0)
10432         {
10433         case AND:
10434           const0 &= const1;
10435           break;
10436         case IOR:
10437           const0 |= const1;
10438           break;
10439         case XOR:
10440           const0 ^= const1;
10441           break;
10442         case PLUS:
10443           const0 += const1;
10444           break;
10445         case NEG:
10446           op0 = UNKNOWN;
10447           break;
10448         default:
10449           break;
10450         }
10451     }
10452
10453   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
10454   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
10455     return false;
10456
10457   /* If the two constants aren't the same, we can't do anything.  The
10458      remaining six cases can all be done.  */
10459   else if (const0 != const1)
10460     return false;
10461
10462   else
10463     switch (op0)
10464       {
10465       case IOR:
10466         if (op1 == AND)
10467           /* (a & b) | b == b */
10468           op0 = SET;
10469         else /* op1 == XOR */
10470           /* (a ^ b) | b == a | b */
10471           {;}
10472         break;
10473
10474       case XOR:
10475         if (op1 == AND)
10476           /* (a & b) ^ b == (~a) & b */
10477           op0 = AND, *pcomp_p = true;
10478         else /* op1 == IOR */
10479           /* (a | b) ^ b == a & ~b */
10480           op0 = AND, const0 = ~const0;
10481         break;
10482
10483       case AND:
10484         if (op1 == IOR)
10485           /* (a | b) & b == b */
10486         op0 = SET;
10487         else /* op1 == XOR */
10488           /* (a ^ b) & b) == (~a) & b */
10489           *pcomp_p = true;
10490         break;
10491       default:
10492         break;
10493       }
10494
10495   /* Check for NO-OP cases.  */
10496   const0 &= GET_MODE_MASK (mode);
10497   if (const0 == 0
10498       && (op0 == IOR || op0 == XOR || op0 == PLUS))
10499     op0 = UNKNOWN;
10500   else if (const0 == 0 && op0 == AND)
10501     op0 = SET;
10502   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
10503            && op0 == AND)
10504     op0 = UNKNOWN;
10505
10506   *pop0 = op0;
10507
10508   /* ??? Slightly redundant with the above mask, but not entirely.
10509      Moving this above means we'd have to sign-extend the mode mask
10510      for the final test.  */
10511   if (op0 != UNKNOWN && op0 != NEG)
10512     *pconst0 = trunc_int_for_mode (const0, mode);
10513
10514   return true;
10515 }
10516 \f
10517 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10518    the shift in.  The original shift operation CODE is performed on OP in
10519    ORIG_MODE.  Return the wider mode MODE if we can perform the operation
10520    in that mode.  Return ORIG_MODE otherwise.  We can also assume that the
10521    result of the shift is subject to operation OUTER_CODE with operand
10522    OUTER_CONST.  */
10523
10524 static scalar_int_mode
10525 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
10526                       scalar_int_mode orig_mode, scalar_int_mode mode,
10527                       enum rtx_code outer_code, HOST_WIDE_INT outer_const)
10528 {
10529   gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
10530
10531   /* In general we can't perform in wider mode for right shift and rotate.  */
10532   switch (code)
10533     {
10534     case ASHIFTRT:
10535       /* We can still widen if the bits brought in from the left are identical
10536          to the sign bit of ORIG_MODE.  */
10537       if (num_sign_bit_copies (op, mode)
10538           > (unsigned) (GET_MODE_PRECISION (mode)
10539                         - GET_MODE_PRECISION (orig_mode)))
10540         return mode;
10541       return orig_mode;
10542
10543     case LSHIFTRT:
10544       /* Similarly here but with zero bits.  */
10545       if (HWI_COMPUTABLE_MODE_P (mode)
10546           && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
10547         return mode;
10548
10549       /* We can also widen if the bits brought in will be masked off.  This
10550          operation is performed in ORIG_MODE.  */
10551       if (outer_code == AND)
10552         {
10553           int care_bits = low_bitmask_len (orig_mode, outer_const);
10554
10555           if (care_bits >= 0
10556               && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
10557             return mode;
10558         }
10559       /* fall through */
10560
10561     case ROTATE:
10562       return orig_mode;
10563
10564     case ROTATERT:
10565       gcc_unreachable ();
10566
10567     default:
10568       return mode;
10569     }
10570 }
10571
10572 /* Simplify a shift of VAROP by ORIG_COUNT bits.  CODE says what kind
10573    of shift.  The result of the shift is RESULT_MODE.  Return NULL_RTX
10574    if we cannot simplify it.  Otherwise, return a simplified value.
10575
10576    The shift is normally computed in the widest mode we find in VAROP, as
10577    long as it isn't a different number of words than RESULT_MODE.  Exceptions
10578    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
10579
10580 static rtx
10581 simplify_shift_const_1 (enum rtx_code code, machine_mode result_mode,
10582                         rtx varop, int orig_count)
10583 {
10584   enum rtx_code orig_code = code;
10585   rtx orig_varop = varop;
10586   int count, log2;
10587   machine_mode mode = result_mode;
10588   machine_mode shift_mode;
10589   scalar_int_mode tmode, inner_mode, int_mode, int_varop_mode, int_result_mode;
10590   /* We form (outer_op (code varop count) (outer_const)).  */
10591   enum rtx_code outer_op = UNKNOWN;
10592   HOST_WIDE_INT outer_const = 0;
10593   bool complement_p = false;
10594   rtx new_rtx, x;
10595
10596   /* Make sure and truncate the "natural" shift on the way in.  We don't
10597      want to do this inside the loop as it makes it more difficult to
10598      combine shifts.  */
10599   if (SHIFT_COUNT_TRUNCATED)
10600     orig_count &= GET_MODE_UNIT_BITSIZE (mode) - 1;
10601
10602   /* If we were given an invalid count, don't do anything except exactly
10603      what was requested.  */
10604
10605   if (orig_count < 0 || orig_count >= (int) GET_MODE_UNIT_PRECISION (mode))
10606     return NULL_RTX;
10607
10608   count = orig_count;
10609
10610   /* Unless one of the branches of the `if' in this loop does a `continue',
10611      we will `break' the loop after the `if'.  */
10612
10613   while (count != 0)
10614     {
10615       /* If we have an operand of (clobber (const_int 0)), fail.  */
10616       if (GET_CODE (varop) == CLOBBER)
10617         return NULL_RTX;
10618
10619       /* Convert ROTATERT to ROTATE.  */
10620       if (code == ROTATERT)
10621         {
10622           unsigned int bitsize = GET_MODE_UNIT_PRECISION (result_mode);
10623           code = ROTATE;
10624           count = bitsize - count;
10625         }
10626
10627       shift_mode = result_mode;
10628       if (shift_mode != mode)
10629         {
10630           /* We only change the modes of scalar shifts.  */
10631           int_mode = as_a <scalar_int_mode> (mode);
10632           int_result_mode = as_a <scalar_int_mode> (result_mode);
10633           shift_mode = try_widen_shift_mode (code, varop, count,
10634                                              int_result_mode, int_mode,
10635                                              outer_op, outer_const);
10636         }
10637
10638       scalar_int_mode shift_unit_mode
10639         = as_a <scalar_int_mode> (GET_MODE_INNER (shift_mode));
10640
10641       /* Handle cases where the count is greater than the size of the mode
10642          minus 1.  For ASHIFT, use the size minus one as the count (this can
10643          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
10644          take the count modulo the size.  For other shifts, the result is
10645          zero.
10646
10647          Since these shifts are being produced by the compiler by combining
10648          multiple operations, each of which are defined, we know what the
10649          result is supposed to be.  */
10650
10651       if (count > (GET_MODE_PRECISION (shift_unit_mode) - 1))
10652         {
10653           if (code == ASHIFTRT)
10654             count = GET_MODE_PRECISION (shift_unit_mode) - 1;
10655           else if (code == ROTATE || code == ROTATERT)
10656             count %= GET_MODE_PRECISION (shift_unit_mode);
10657           else
10658             {
10659               /* We can't simply return zero because there may be an
10660                  outer op.  */
10661               varop = const0_rtx;
10662               count = 0;
10663               break;
10664             }
10665         }
10666
10667       /* If we discovered we had to complement VAROP, leave.  Making a NOT
10668          here would cause an infinite loop.  */
10669       if (complement_p)
10670         break;
10671
10672       if (shift_mode == shift_unit_mode)
10673         {
10674           /* An arithmetic right shift of a quantity known to be -1 or 0
10675              is a no-op.  */
10676           if (code == ASHIFTRT
10677               && (num_sign_bit_copies (varop, shift_unit_mode)
10678                   == GET_MODE_PRECISION (shift_unit_mode)))
10679             {
10680               count = 0;
10681               break;
10682             }
10683
10684           /* If we are doing an arithmetic right shift and discarding all but
10685              the sign bit copies, this is equivalent to doing a shift by the
10686              bitsize minus one.  Convert it into that shift because it will
10687              often allow other simplifications.  */
10688
10689           if (code == ASHIFTRT
10690               && (count + num_sign_bit_copies (varop, shift_unit_mode)
10691                   >= GET_MODE_PRECISION (shift_unit_mode)))
10692             count = GET_MODE_PRECISION (shift_unit_mode) - 1;
10693
10694           /* We simplify the tests below and elsewhere by converting
10695              ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10696              `make_compound_operation' will convert it to an ASHIFTRT for
10697              those machines (such as VAX) that don't have an LSHIFTRT.  */
10698           if (code == ASHIFTRT
10699               && HWI_COMPUTABLE_MODE_P (shift_unit_mode)
10700               && val_signbit_known_clear_p (shift_unit_mode,
10701                                             nonzero_bits (varop,
10702                                                           shift_unit_mode)))
10703             code = LSHIFTRT;
10704
10705           if (((code == LSHIFTRT
10706                 && HWI_COMPUTABLE_MODE_P (shift_unit_mode)
10707                 && !(nonzero_bits (varop, shift_unit_mode) >> count))
10708                || (code == ASHIFT
10709                    && HWI_COMPUTABLE_MODE_P (shift_unit_mode)
10710                    && !((nonzero_bits (varop, shift_unit_mode) << count)
10711                         & GET_MODE_MASK (shift_unit_mode))))
10712               && !side_effects_p (varop))
10713             varop = const0_rtx;
10714         }
10715
10716       switch (GET_CODE (varop))
10717         {
10718         case SIGN_EXTEND:
10719         case ZERO_EXTEND:
10720         case SIGN_EXTRACT:
10721         case ZERO_EXTRACT:
10722           new_rtx = expand_compound_operation (varop);
10723           if (new_rtx != varop)
10724             {
10725               varop = new_rtx;
10726               continue;
10727             }
10728           break;
10729
10730         case MEM:
10731           /* The following rules apply only to scalars.  */
10732           if (shift_mode != shift_unit_mode)
10733             break;
10734           int_mode = as_a <scalar_int_mode> (mode);
10735
10736           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10737              minus the width of a smaller mode, we can do this with a
10738              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
10739           if ((code == ASHIFTRT || code == LSHIFTRT)
10740               && ! mode_dependent_address_p (XEXP (varop, 0),
10741                                              MEM_ADDR_SPACE (varop))
10742               && ! MEM_VOLATILE_P (varop)
10743               && (int_mode_for_size (GET_MODE_BITSIZE (int_mode) - count, 1)
10744                   .exists (&tmode)))
10745             {
10746               new_rtx = adjust_address_nv (varop, tmode,
10747                                            BYTES_BIG_ENDIAN ? 0
10748                                            : count / BITS_PER_UNIT);
10749
10750               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
10751                                      : ZERO_EXTEND, int_mode, new_rtx);
10752               count = 0;
10753               continue;
10754             }
10755           break;
10756
10757         case SUBREG:
10758           /* The following rules apply only to scalars.  */
10759           if (shift_mode != shift_unit_mode)
10760             break;
10761           int_mode = as_a <scalar_int_mode> (mode);
10762           int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10763
10764           /* If VAROP is a SUBREG, strip it as long as the inner operand has
10765              the same number of words as what we've seen so far.  Then store
10766              the widest mode in MODE.  */
10767           if (subreg_lowpart_p (varop)
10768               && is_int_mode (GET_MODE (SUBREG_REG (varop)), &inner_mode)
10769               && GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (int_varop_mode)
10770               && (CEIL (GET_MODE_SIZE (inner_mode), UNITS_PER_WORD)
10771                   == CEIL (GET_MODE_SIZE (int_mode), UNITS_PER_WORD))
10772               && GET_MODE_CLASS (int_varop_mode) == MODE_INT)
10773             {
10774               varop = SUBREG_REG (varop);
10775               if (GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (int_mode))
10776                 mode = inner_mode;
10777               continue;
10778             }
10779           break;
10780
10781         case MULT:
10782           /* Some machines use MULT instead of ASHIFT because MULT
10783              is cheaper.  But it is still better on those machines to
10784              merge two shifts into one.  */
10785           if (CONST_INT_P (XEXP (varop, 1))
10786               && (log2 = exact_log2 (UINTVAL (XEXP (varop, 1)))) >= 0)
10787             {
10788               rtx log2_rtx = gen_int_shift_amount (GET_MODE (varop), log2);
10789               varop = simplify_gen_binary (ASHIFT, GET_MODE (varop),
10790                                            XEXP (varop, 0), log2_rtx);
10791               continue;
10792             }
10793           break;
10794
10795         case UDIV:
10796           /* Similar, for when divides are cheaper.  */
10797           if (CONST_INT_P (XEXP (varop, 1))
10798               && (log2 = exact_log2 (UINTVAL (XEXP (varop, 1)))) >= 0)
10799             {
10800               rtx log2_rtx = gen_int_shift_amount (GET_MODE (varop), log2);
10801               varop = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
10802                                            XEXP (varop, 0), log2_rtx);
10803               continue;
10804             }
10805           break;
10806
10807         case ASHIFTRT:
10808           /* If we are extracting just the sign bit of an arithmetic
10809              right shift, that shift is not needed.  However, the sign
10810              bit of a wider mode may be different from what would be
10811              interpreted as the sign bit in a narrower mode, so, if
10812              the result is narrower, don't discard the shift.  */
10813           if (code == LSHIFTRT
10814               && count == (GET_MODE_UNIT_BITSIZE (result_mode) - 1)
10815               && (GET_MODE_UNIT_BITSIZE (result_mode)
10816                   >= GET_MODE_UNIT_BITSIZE (GET_MODE (varop))))
10817             {
10818               varop = XEXP (varop, 0);
10819               continue;
10820             }
10821
10822           /* fall through */
10823
10824         case LSHIFTRT:
10825         case ASHIFT:
10826         case ROTATE:
10827           /* The following rules apply only to scalars.  */
10828           if (shift_mode != shift_unit_mode)
10829             break;
10830           int_mode = as_a <scalar_int_mode> (mode);
10831           int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10832           int_result_mode = as_a <scalar_int_mode> (result_mode);
10833
10834           /* Here we have two nested shifts.  The result is usually the
10835              AND of a new shift with a mask.  We compute the result below.  */
10836           if (CONST_INT_P (XEXP (varop, 1))
10837               && INTVAL (XEXP (varop, 1)) >= 0
10838               && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (int_varop_mode)
10839               && HWI_COMPUTABLE_MODE_P (int_result_mode)
10840               && HWI_COMPUTABLE_MODE_P (int_mode))
10841             {
10842               enum rtx_code first_code = GET_CODE (varop);
10843               unsigned int first_count = INTVAL (XEXP (varop, 1));
10844               unsigned HOST_WIDE_INT mask;
10845               rtx mask_rtx;
10846
10847               /* We have one common special case.  We can't do any merging if
10848                  the inner code is an ASHIFTRT of a smaller mode.  However, if
10849                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10850                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10851                  we can convert it to
10852                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10853                  This simplifies certain SIGN_EXTEND operations.  */
10854               if (code == ASHIFT && first_code == ASHIFTRT
10855                   && count == (GET_MODE_PRECISION (int_result_mode)
10856                                - GET_MODE_PRECISION (int_varop_mode)))
10857                 {
10858                   /* C3 has the low-order C1 bits zero.  */
10859
10860                   mask = GET_MODE_MASK (int_mode)
10861                          & ~((HOST_WIDE_INT_1U << first_count) - 1);
10862
10863                   varop = simplify_and_const_int (NULL_RTX, int_result_mode,
10864                                                   XEXP (varop, 0), mask);
10865                   varop = simplify_shift_const (NULL_RTX, ASHIFT,
10866                                                 int_result_mode, varop, count);
10867                   count = first_count;
10868                   code = ASHIFTRT;
10869                   continue;
10870                 }
10871
10872               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10873                  than C1 high-order bits equal to the sign bit, we can convert
10874                  this to either an ASHIFT or an ASHIFTRT depending on the
10875                  two counts.
10876
10877                  We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE.  */
10878
10879               if (code == ASHIFTRT && first_code == ASHIFT
10880                   && int_varop_mode == shift_unit_mode
10881                   && (num_sign_bit_copies (XEXP (varop, 0), shift_unit_mode)
10882                       > first_count))
10883                 {
10884                   varop = XEXP (varop, 0);
10885                   count -= first_count;
10886                   if (count < 0)
10887                     {
10888                       count = -count;
10889                       code = ASHIFT;
10890                     }
10891
10892                   continue;
10893                 }
10894
10895               /* There are some cases we can't do.  If CODE is ASHIFTRT,
10896                  we can only do this if FIRST_CODE is also ASHIFTRT.
10897
10898                  We can't do the case when CODE is ROTATE and FIRST_CODE is
10899                  ASHIFTRT.
10900
10901                  If the mode of this shift is not the mode of the outer shift,
10902                  we can't do this if either shift is a right shift or ROTATE.
10903
10904                  Finally, we can't do any of these if the mode is too wide
10905                  unless the codes are the same.
10906
10907                  Handle the case where the shift codes are the same
10908                  first.  */
10909
10910               if (code == first_code)
10911                 {
10912                   if (int_varop_mode != int_result_mode
10913                       && (code == ASHIFTRT || code == LSHIFTRT
10914                           || code == ROTATE))
10915                     break;
10916
10917                   count += first_count;
10918                   varop = XEXP (varop, 0);
10919                   continue;
10920                 }
10921
10922               if (code == ASHIFTRT
10923                   || (code == ROTATE && first_code == ASHIFTRT)
10924                   || GET_MODE_PRECISION (int_mode) > HOST_BITS_PER_WIDE_INT
10925                   || (int_varop_mode != int_result_mode
10926                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
10927                           || first_code == ROTATE
10928                           || code == ROTATE)))
10929                 break;
10930
10931               /* To compute the mask to apply after the shift, shift the
10932                  nonzero bits of the inner shift the same way the
10933                  outer shift will.  */
10934
10935               mask_rtx = gen_int_mode (nonzero_bits (varop, int_varop_mode),
10936                                        int_result_mode);
10937               rtx count_rtx = gen_int_shift_amount (int_result_mode, count);
10938               mask_rtx
10939                 = simplify_const_binary_operation (code, int_result_mode,
10940                                                    mask_rtx, count_rtx);
10941
10942               /* Give up if we can't compute an outer operation to use.  */
10943               if (mask_rtx == 0
10944                   || !CONST_INT_P (mask_rtx)
10945                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
10946                                         INTVAL (mask_rtx),
10947                                         int_result_mode, &complement_p))
10948                 break;
10949
10950               /* If the shifts are in the same direction, we add the
10951                  counts.  Otherwise, we subtract them.  */
10952               if ((code == ASHIFTRT || code == LSHIFTRT)
10953                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10954                 count += first_count;
10955               else
10956                 count -= first_count;
10957
10958               /* If COUNT is positive, the new shift is usually CODE,
10959                  except for the two exceptions below, in which case it is
10960                  FIRST_CODE.  If the count is negative, FIRST_CODE should
10961                  always be used  */
10962               if (count > 0
10963                   && ((first_code == ROTATE && code == ASHIFT)
10964                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
10965                 code = first_code;
10966               else if (count < 0)
10967                 code = first_code, count = -count;
10968
10969               varop = XEXP (varop, 0);
10970               continue;
10971             }
10972
10973           /* If we have (A << B << C) for any shift, we can convert this to
10974              (A << C << B).  This wins if A is a constant.  Only try this if
10975              B is not a constant.  */
10976
10977           else if (GET_CODE (varop) == code
10978                    && CONST_INT_P (XEXP (varop, 0))
10979                    && !CONST_INT_P (XEXP (varop, 1)))
10980             {
10981               /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10982                  sure the result will be masked.  See PR70222.  */
10983               if (code == LSHIFTRT
10984                   && int_mode != int_result_mode
10985                   && !merge_outer_ops (&outer_op, &outer_const, AND,
10986                                        GET_MODE_MASK (int_result_mode)
10987                                        >> orig_count, int_result_mode,
10988                                        &complement_p))
10989                 break;
10990               /* For ((int) (cstLL >> count)) >> cst2 just give up.  Queuing
10991                  up outer sign extension (often left and right shift) is
10992                  hardly more efficient than the original.  See PR70429.
10993                  Similarly punt for rotates with different modes.
10994                  See PR97386.  */
10995               if ((code == ASHIFTRT || code == ROTATE)
10996                   && int_mode != int_result_mode)
10997                 break;
10998
10999               rtx count_rtx = gen_int_shift_amount (int_result_mode, count);
11000               rtx new_rtx = simplify_const_binary_operation (code, int_mode,
11001                                                              XEXP (varop, 0),
11002                                                              count_rtx);
11003               varop = gen_rtx_fmt_ee (code, int_mode, new_rtx, XEXP (varop, 1));
11004               count = 0;
11005               continue;
11006             }
11007           break;
11008
11009         case NOT:
11010           /* The following rules apply only to scalars.  */
11011           if (shift_mode != shift_unit_mode)
11012             break;
11013
11014           /* Make this fit the case below.  */
11015           varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
11016           continue;
11017
11018         case IOR:
11019         case AND:
11020         case XOR:
11021           /* The following rules apply only to scalars.  */
11022           if (shift_mode != shift_unit_mode)
11023             break;
11024           int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
11025           int_result_mode = as_a <scalar_int_mode> (result_mode);
11026
11027           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
11028              with C the size of VAROP - 1 and the shift is logical if
11029              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11030              we have an (le X 0) operation.   If we have an arithmetic shift
11031              and STORE_FLAG_VALUE is 1 or we have a logical shift with
11032              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
11033
11034           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
11035               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
11036               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
11037               && (code == LSHIFTRT || code == ASHIFTRT)
11038               && count == (GET_MODE_PRECISION (int_varop_mode) - 1)
11039               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
11040             {
11041               count = 0;
11042               varop = gen_rtx_LE (int_varop_mode, XEXP (varop, 1),
11043                                   const0_rtx);
11044
11045               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
11046                 varop = gen_rtx_NEG (int_varop_mode, varop);
11047
11048               continue;
11049             }
11050
11051           /* If we have (shift (logical)), move the logical to the outside
11052              to allow it to possibly combine with another logical and the
11053              shift to combine with another shift.  This also canonicalizes to
11054              what a ZERO_EXTRACT looks like.  Also, some machines have
11055              (and (shift)) insns.  */
11056
11057           if (CONST_INT_P (XEXP (varop, 1))
11058               /* We can't do this if we have (ashiftrt (xor))  and the
11059                  constant has its sign bit set in shift_unit_mode with
11060                  shift_unit_mode wider than result_mode.  */
11061               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
11062                    && int_result_mode != shift_unit_mode
11063                    && trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
11064                                           shift_unit_mode) < 0)
11065               && (new_rtx = simplify_const_binary_operation
11066                   (code, int_result_mode,
11067                    gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11068                    gen_int_shift_amount (int_result_mode, count))) != 0
11069               && CONST_INT_P (new_rtx)
11070               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
11071                                   INTVAL (new_rtx), int_result_mode,
11072                                   &complement_p))
11073             {
11074               varop = XEXP (varop, 0);
11075               continue;
11076             }
11077
11078           /* If we can't do that, try to simplify the shift in each arm of the
11079              logical expression, make a new logical expression, and apply
11080              the inverse distributive law.  This also can't be done for
11081              (ashiftrt (xor)) where we've widened the shift and the constant
11082              changes the sign bit.  */
11083           if (CONST_INT_P (XEXP (varop, 1))
11084               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
11085                    && int_result_mode != shift_unit_mode
11086                    && trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
11087                                           shift_unit_mode) < 0))
11088             {
11089               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_unit_mode,
11090                                               XEXP (varop, 0), count);
11091               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_unit_mode,
11092                                               XEXP (varop, 1), count);
11093
11094               varop = simplify_gen_binary (GET_CODE (varop), shift_unit_mode,
11095                                            lhs, rhs);
11096               varop = apply_distributive_law (varop);
11097
11098               count = 0;
11099               continue;
11100             }
11101           break;
11102
11103         case EQ:
11104           /* The following rules apply only to scalars.  */
11105           if (shift_mode != shift_unit_mode)
11106             break;
11107           int_result_mode = as_a <scalar_int_mode> (result_mode);
11108
11109           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
11110              says that the sign bit can be tested, FOO has mode MODE, C is
11111              GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
11112              that may be nonzero.  */
11113           if (code == LSHIFTRT
11114               && XEXP (varop, 1) == const0_rtx
11115               && GET_MODE (XEXP (varop, 0)) == int_result_mode
11116               && count == (GET_MODE_PRECISION (int_result_mode) - 1)
11117               && HWI_COMPUTABLE_MODE_P (int_result_mode)
11118               && STORE_FLAG_VALUE == -1
11119               && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1
11120               && merge_outer_ops (&outer_op, &outer_const, XOR, 1,
11121                                   int_result_mode, &complement_p))
11122             {
11123               varop = XEXP (varop, 0);
11124               count = 0;
11125               continue;
11126             }
11127           break;
11128
11129         case NEG:
11130           /* The following rules apply only to scalars.  */
11131           if (shift_mode != shift_unit_mode)
11132             break;
11133           int_result_mode = as_a <scalar_int_mode> (result_mode);
11134
11135           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11136              than the number of bits in the mode is equivalent to A.  */
11137           if (code == LSHIFTRT
11138               && count == (GET_MODE_PRECISION (int_result_mode) - 1)
11139               && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1)
11140             {
11141               varop = XEXP (varop, 0);
11142               count = 0;
11143               continue;
11144             }
11145
11146           /* NEG commutes with ASHIFT since it is multiplication.  Move the
11147              NEG outside to allow shifts to combine.  */
11148           if (code == ASHIFT
11149               && merge_outer_ops (&outer_op, &outer_const, NEG, 0,
11150                                   int_result_mode, &complement_p))
11151             {
11152               varop = XEXP (varop, 0);
11153               continue;
11154             }
11155           break;
11156
11157         case PLUS:
11158           /* The following rules apply only to scalars.  */
11159           if (shift_mode != shift_unit_mode)
11160             break;
11161           int_result_mode = as_a <scalar_int_mode> (result_mode);
11162
11163           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11164              is one less than the number of bits in the mode is
11165              equivalent to (xor A 1).  */
11166           if (code == LSHIFTRT
11167               && count == (GET_MODE_PRECISION (int_result_mode) - 1)
11168               && XEXP (varop, 1) == constm1_rtx
11169               && nonzero_bits (XEXP (varop, 0), int_result_mode) == 1
11170               && merge_outer_ops (&outer_op, &outer_const, XOR, 1,
11171                                   int_result_mode, &complement_p))
11172             {
11173               count = 0;
11174               varop = XEXP (varop, 0);
11175               continue;
11176             }
11177
11178           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11179              that might be nonzero in BAR are those being shifted out and those
11180              bits are known zero in FOO, we can replace the PLUS with FOO.
11181              Similarly in the other operand order.  This code occurs when
11182              we are computing the size of a variable-size array.  */
11183
11184           if ((code == ASHIFTRT || code == LSHIFTRT)
11185               && count < HOST_BITS_PER_WIDE_INT
11186               && nonzero_bits (XEXP (varop, 1), int_result_mode) >> count == 0
11187               && (nonzero_bits (XEXP (varop, 1), int_result_mode)
11188                   & nonzero_bits (XEXP (varop, 0), int_result_mode)) == 0)
11189             {
11190               varop = XEXP (varop, 0);
11191               continue;
11192             }
11193           else if ((code == ASHIFTRT || code == LSHIFTRT)
11194                    && count < HOST_BITS_PER_WIDE_INT
11195                    && HWI_COMPUTABLE_MODE_P (int_result_mode)
11196                    && (nonzero_bits (XEXP (varop, 0), int_result_mode)
11197                        >> count) == 0
11198                    && (nonzero_bits (XEXP (varop, 0), int_result_mode)
11199                        & nonzero_bits (XEXP (varop, 1), int_result_mode)) == 0)
11200             {
11201               varop = XEXP (varop, 1);
11202               continue;
11203             }
11204
11205           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
11206           if (code == ASHIFT
11207               && CONST_INT_P (XEXP (varop, 1))
11208               && (new_rtx = simplify_const_binary_operation
11209                   (ASHIFT, int_result_mode,
11210                    gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11211                    gen_int_shift_amount (int_result_mode, count))) != 0
11212               && CONST_INT_P (new_rtx)
11213               && merge_outer_ops (&outer_op, &outer_const, PLUS,
11214                                   INTVAL (new_rtx), int_result_mode,
11215                                   &complement_p))
11216             {
11217               varop = XEXP (varop, 0);
11218               continue;
11219             }
11220
11221           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11222              signbit', and attempt to change the PLUS to an XOR and move it to
11223              the outer operation as is done above in the AND/IOR/XOR case
11224              leg for shift(logical). See details in logical handling above
11225              for reasoning in doing so.  */
11226           if (code == LSHIFTRT
11227               && CONST_INT_P (XEXP (varop, 1))
11228               && mode_signbit_p (int_result_mode, XEXP (varop, 1))
11229               && (new_rtx = simplify_const_binary_operation
11230                   (code, int_result_mode,
11231                    gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11232                    gen_int_shift_amount (int_result_mode, count))) != 0
11233               && CONST_INT_P (new_rtx)
11234               && merge_outer_ops (&outer_op, &outer_const, XOR,
11235                                   INTVAL (new_rtx), int_result_mode,
11236                                   &complement_p))
11237             {
11238               varop = XEXP (varop, 0);
11239               continue;
11240             }
11241
11242           break;
11243
11244         case MINUS:
11245           /* The following rules apply only to scalars.  */
11246           if (shift_mode != shift_unit_mode)
11247             break;
11248           int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
11249
11250           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11251              with C the size of VAROP - 1 and the shift is logical if
11252              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11253              we have a (gt X 0) operation.  If the shift is arithmetic with
11254              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11255              we have a (neg (gt X 0)) operation.  */
11256
11257           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
11258               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
11259               && count == (GET_MODE_PRECISION (int_varop_mode) - 1)
11260               && (code == LSHIFTRT || code == ASHIFTRT)
11261               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
11262               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
11263               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
11264             {
11265               count = 0;
11266               varop = gen_rtx_GT (int_varop_mode, XEXP (varop, 1),
11267                                   const0_rtx);
11268
11269               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
11270                 varop = gen_rtx_NEG (int_varop_mode, varop);
11271
11272               continue;
11273             }
11274           break;
11275
11276         case TRUNCATE:
11277           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11278              if the truncate does not affect the value.  */
11279           if (code == LSHIFTRT
11280               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
11281               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
11282               && (INTVAL (XEXP (XEXP (varop, 0), 1))
11283                   >= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop, 0)))
11284                       - GET_MODE_UNIT_PRECISION (GET_MODE (varop)))))
11285             {
11286               rtx varop_inner = XEXP (varop, 0);
11287               int new_count = count + INTVAL (XEXP (varop_inner, 1));
11288               rtx new_count_rtx = gen_int_shift_amount (GET_MODE (varop_inner),
11289                                                         new_count);
11290               varop_inner = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
11291                                               XEXP (varop_inner, 0),
11292                                               new_count_rtx);
11293               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
11294               count = 0;
11295               continue;
11296             }
11297           break;
11298
11299         default:
11300           break;
11301         }
11302
11303       break;
11304     }
11305
11306   shift_mode = result_mode;
11307   if (shift_mode != mode)
11308     {
11309       /* We only change the modes of scalar shifts.  */
11310       int_mode = as_a <scalar_int_mode> (mode);
11311       int_result_mode = as_a <scalar_int_mode> (result_mode);
11312       shift_mode = try_widen_shift_mode (code, varop, count, int_result_mode,
11313                                          int_mode, outer_op, outer_const);
11314     }
11315
11316   /* We have now finished analyzing the shift.  The result should be
11317      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
11318      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11319      to the result of the shift.  OUTER_CONST is the relevant constant,
11320      but we must turn off all bits turned off in the shift.  */
11321
11322   if (outer_op == UNKNOWN
11323       && orig_code == code && orig_count == count
11324       && varop == orig_varop
11325       && shift_mode == GET_MODE (varop))
11326     return NULL_RTX;
11327
11328   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
11329   varop = gen_lowpart (shift_mode, varop);
11330   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
11331     return NULL_RTX;
11332
11333   /* If we have an outer operation and we just made a shift, it is
11334      possible that we could have simplified the shift were it not
11335      for the outer operation.  So try to do the simplification
11336      recursively.  */
11337
11338   if (outer_op != UNKNOWN)
11339     x = simplify_shift_const_1 (code, shift_mode, varop, count);
11340   else
11341     x = NULL_RTX;
11342
11343   if (x == NULL_RTX)
11344     x = simplify_gen_binary (code, shift_mode, varop,
11345                              gen_int_shift_amount (shift_mode, count));
11346
11347   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11348      turn off all the bits that the shift would have turned off.  */
11349   if (orig_code == LSHIFTRT && result_mode != shift_mode)
11350     /* We only change the modes of scalar shifts.  */
11351     x = simplify_and_const_int (NULL_RTX, as_a <scalar_int_mode> (shift_mode),
11352                                 x, GET_MODE_MASK (result_mode) >> orig_count);
11353
11354   /* Do the remainder of the processing in RESULT_MODE.  */
11355   x = gen_lowpart_or_truncate (result_mode, x);
11356
11357   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11358      operation.  */
11359   if (complement_p)
11360     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
11361
11362   if (outer_op != UNKNOWN)
11363     {
11364       int_result_mode = as_a <scalar_int_mode> (result_mode);
11365
11366       if (GET_RTX_CLASS (outer_op) != RTX_UNARY
11367           && GET_MODE_PRECISION (int_result_mode) < HOST_BITS_PER_WIDE_INT)
11368         outer_const = trunc_int_for_mode (outer_const, int_result_mode);
11369
11370       if (outer_op == AND)
11371         x = simplify_and_const_int (NULL_RTX, int_result_mode, x, outer_const);
11372       else if (outer_op == SET)
11373         {
11374           /* This means that we have determined that the result is
11375              equivalent to a constant.  This should be rare.  */
11376           if (!side_effects_p (x))
11377             x = GEN_INT (outer_const);
11378         }
11379       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
11380         x = simplify_gen_unary (outer_op, int_result_mode, x, int_result_mode);
11381       else
11382         x = simplify_gen_binary (outer_op, int_result_mode, x,
11383                                  GEN_INT (outer_const));
11384     }
11385
11386   return x;
11387 }
11388
11389 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
11390    The result of the shift is RESULT_MODE.  If we cannot simplify it,
11391    return X or, if it is NULL, synthesize the expression with
11392    simplify_gen_binary.  Otherwise, return a simplified value.
11393
11394    The shift is normally computed in the widest mode we find in VAROP, as
11395    long as it isn't a different number of words than RESULT_MODE.  Exceptions
11396    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
11397
11398 static rtx
11399 simplify_shift_const (rtx x, enum rtx_code code, machine_mode result_mode,
11400                       rtx varop, int count)
11401 {
11402   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
11403   if (tem)
11404     return tem;
11405
11406   if (!x)
11407     x = simplify_gen_binary (code, GET_MODE (varop), varop,
11408                              gen_int_shift_amount (GET_MODE (varop), count));
11409   if (GET_MODE (x) != result_mode)
11410     x = gen_lowpart (result_mode, x);
11411   return x;
11412 }
11413
11414 \f
11415 /* A subroutine of recog_for_combine.  See there for arguments and
11416    return value.  */
11417
11418 static int
11419 recog_for_combine_1 (rtx *pnewpat, rtx_insn *insn, rtx *pnotes)
11420 {
11421   rtx pat = *pnewpat;
11422   rtx pat_without_clobbers;
11423   int insn_code_number;
11424   int num_clobbers_to_add = 0;
11425   int i;
11426   rtx notes = NULL_RTX;
11427   rtx old_notes, old_pat;
11428   int old_icode;
11429
11430   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11431      we use to indicate that something didn't match.  If we find such a
11432      thing, force rejection.  */
11433   if (GET_CODE (pat) == PARALLEL)
11434     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
11435       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
11436           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
11437         return -1;
11438
11439   old_pat = PATTERN (insn);
11440   old_notes = REG_NOTES (insn);
11441   PATTERN (insn) = pat;
11442   REG_NOTES (insn) = NULL_RTX;
11443
11444   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
11445   if (dump_file && (dump_flags & TDF_DETAILS))
11446     {
11447       if (insn_code_number < 0)
11448         fputs ("Failed to match this instruction:\n", dump_file);
11449       else
11450         fputs ("Successfully matched this instruction:\n", dump_file);
11451       print_rtl_single (dump_file, pat);
11452     }
11453
11454   /* If it isn't, there is the possibility that we previously had an insn
11455      that clobbered some register as a side effect, but the combined
11456      insn doesn't need to do that.  So try once more without the clobbers
11457      unless this represents an ASM insn.  */
11458
11459   if (insn_code_number < 0 && ! check_asm_operands (pat)
11460       && GET_CODE (pat) == PARALLEL)
11461     {
11462       int pos;
11463
11464       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
11465         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
11466           {
11467             if (i != pos)
11468               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
11469             pos++;
11470           }
11471
11472       SUBST_INT (XVECLEN (pat, 0), pos);
11473
11474       if (pos == 1)
11475         pat = XVECEXP (pat, 0, 0);
11476
11477       PATTERN (insn) = pat;
11478       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
11479       if (dump_file && (dump_flags & TDF_DETAILS))
11480         {
11481           if (insn_code_number < 0)
11482             fputs ("Failed to match this instruction:\n", dump_file);
11483           else
11484             fputs ("Successfully matched this instruction:\n", dump_file);
11485           print_rtl_single (dump_file, pat);
11486         }
11487     }
11488
11489   pat_without_clobbers = pat;
11490
11491   PATTERN (insn) = old_pat;
11492   REG_NOTES (insn) = old_notes;
11493
11494   /* Recognize all noop sets, these will be killed by followup pass.  */
11495   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
11496     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
11497
11498   /* If we had any clobbers to add, make a new pattern than contains
11499      them.  Then check to make sure that all of them are dead.  */
11500   if (num_clobbers_to_add)
11501     {
11502       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
11503                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
11504                                                   ? (XVECLEN (pat, 0)
11505                                                      + num_clobbers_to_add)
11506                                                   : num_clobbers_to_add + 1));
11507
11508       if (GET_CODE (pat) == PARALLEL)
11509         for (i = 0; i < XVECLEN (pat, 0); i++)
11510           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
11511       else
11512         XVECEXP (newpat, 0, 0) = pat;
11513
11514       add_clobbers (newpat, insn_code_number);
11515
11516       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
11517            i < XVECLEN (newpat, 0); i++)
11518         {
11519           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
11520               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
11521             return -1;
11522           if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
11523             {
11524               gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
11525               notes = alloc_reg_note (REG_UNUSED,
11526                                       XEXP (XVECEXP (newpat, 0, i), 0), notes);
11527             }
11528         }
11529       pat = newpat;
11530     }
11531
11532   if (insn_code_number >= 0
11533       && insn_code_number != NOOP_MOVE_INSN_CODE)
11534     {
11535       old_pat = PATTERN (insn);
11536       old_notes = REG_NOTES (insn);
11537       old_icode = INSN_CODE (insn);
11538       PATTERN (insn) = pat;
11539       REG_NOTES (insn) = notes;
11540       INSN_CODE (insn) = insn_code_number;
11541
11542       /* Allow targets to reject combined insn.  */
11543       if (!targetm.legitimate_combined_insn (insn))
11544         {
11545           if (dump_file && (dump_flags & TDF_DETAILS))
11546             fputs ("Instruction not appropriate for target.",
11547                    dump_file);
11548
11549           /* Callers expect recog_for_combine to strip
11550              clobbers from the pattern on failure.  */
11551           pat = pat_without_clobbers;
11552           notes = NULL_RTX;
11553
11554           insn_code_number = -1;
11555         }
11556
11557       PATTERN (insn) = old_pat;
11558       REG_NOTES (insn) = old_notes;
11559       INSN_CODE (insn) = old_icode;
11560     }
11561
11562   *pnewpat = pat;
11563   *pnotes = notes;
11564
11565   return insn_code_number;
11566 }
11567
11568 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11569    expressed as an AND and maybe an LSHIFTRT, to that formulation.
11570    Return whether anything was so changed.  */
11571
11572 static bool
11573 change_zero_ext (rtx pat)
11574 {
11575   bool changed = false;
11576   rtx *src = &SET_SRC (pat);
11577
11578   subrtx_ptr_iterator::array_type array;
11579   FOR_EACH_SUBRTX_PTR (iter, array, src, NONCONST)
11580     {
11581       rtx x = **iter;
11582       scalar_int_mode mode, inner_mode;
11583       if (!is_a <scalar_int_mode> (GET_MODE (x), &mode))
11584         continue;
11585       int size;
11586
11587       if (GET_CODE (x) == ZERO_EXTRACT
11588           && CONST_INT_P (XEXP (x, 1))
11589           && CONST_INT_P (XEXP (x, 2))
11590           && is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &inner_mode)
11591           && GET_MODE_PRECISION (inner_mode) <= GET_MODE_PRECISION (mode))
11592         {
11593           size = INTVAL (XEXP (x, 1));
11594
11595           int start = INTVAL (XEXP (x, 2));
11596           if (BITS_BIG_ENDIAN)
11597             start = GET_MODE_PRECISION (inner_mode) - size - start;
11598
11599           if (start != 0)
11600             x = gen_rtx_LSHIFTRT (inner_mode, XEXP (x, 0),
11601                                   gen_int_shift_amount (inner_mode, start));
11602           else
11603             x = XEXP (x, 0);
11604
11605           if (mode != inner_mode)
11606             {
11607               if (REG_P (x) && HARD_REGISTER_P (x)
11608                   && !can_change_dest_mode (x, 0, mode))
11609                 continue;
11610
11611               x = gen_lowpart_SUBREG (mode, x);
11612             }
11613         }
11614       else if (GET_CODE (x) == ZERO_EXTEND
11615                && GET_CODE (XEXP (x, 0)) == SUBREG
11616                && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x, 0))))
11617                && !paradoxical_subreg_p (XEXP (x, 0))
11618                && subreg_lowpart_p (XEXP (x, 0)))
11619         {
11620           inner_mode = as_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)));
11621           size = GET_MODE_PRECISION (inner_mode);
11622           x = SUBREG_REG (XEXP (x, 0));
11623           if (GET_MODE (x) != mode)
11624             {
11625               if (REG_P (x) && HARD_REGISTER_P (x)
11626                   && !can_change_dest_mode (x, 0, mode))
11627                 continue;
11628
11629               x = gen_lowpart_SUBREG (mode, x);
11630             }
11631         }
11632       else if (GET_CODE (x) == ZERO_EXTEND
11633                && REG_P (XEXP (x, 0))
11634                && HARD_REGISTER_P (XEXP (x, 0))
11635                && can_change_dest_mode (XEXP (x, 0), 0, mode))
11636         {
11637           inner_mode = as_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)));
11638           size = GET_MODE_PRECISION (inner_mode);
11639           x = gen_rtx_REG (mode, REGNO (XEXP (x, 0)));
11640         }
11641       else
11642         continue;
11643
11644       if (!(GET_CODE (x) == LSHIFTRT
11645             && CONST_INT_P (XEXP (x, 1))
11646             && size + INTVAL (XEXP (x, 1)) == GET_MODE_PRECISION (mode)))
11647         {
11648           wide_int mask = wi::mask (size, false, GET_MODE_PRECISION (mode));
11649           x = gen_rtx_AND (mode, x, immed_wide_int_const (mask, mode));
11650         }
11651
11652       SUBST (**iter, x);
11653       changed = true;
11654     }
11655
11656   if (changed)
11657     FOR_EACH_SUBRTX_PTR (iter, array, src, NONCONST)
11658       maybe_swap_commutative_operands (**iter);
11659
11660   rtx *dst = &SET_DEST (pat);
11661   scalar_int_mode mode;
11662   if (GET_CODE (*dst) == ZERO_EXTRACT
11663       && REG_P (XEXP (*dst, 0))
11664       && is_a <scalar_int_mode> (GET_MODE (XEXP (*dst, 0)), &mode)
11665       && CONST_INT_P (XEXP (*dst, 1))
11666       && CONST_INT_P (XEXP (*dst, 2)))
11667     {
11668       rtx reg = XEXP (*dst, 0);
11669       int width = INTVAL (XEXP (*dst, 1));
11670       int offset = INTVAL (XEXP (*dst, 2));
11671       int reg_width = GET_MODE_PRECISION (mode);
11672       if (BITS_BIG_ENDIAN)
11673         offset = reg_width - width - offset;
11674
11675       rtx x, y, z, w;
11676       wide_int mask = wi::shifted_mask (offset, width, true, reg_width);
11677       wide_int mask2 = wi::shifted_mask (offset, width, false, reg_width);
11678       x = gen_rtx_AND (mode, reg, immed_wide_int_const (mask, mode));
11679       if (offset)
11680         y = gen_rtx_ASHIFT (mode, SET_SRC (pat), GEN_INT (offset));
11681       else
11682         y = SET_SRC (pat);
11683       z = gen_rtx_AND (mode, y, immed_wide_int_const (mask2, mode));
11684       w = gen_rtx_IOR (mode, x, z);
11685       SUBST (SET_DEST (pat), reg);
11686       SUBST (SET_SRC (pat), w);
11687
11688       changed = true;
11689     }
11690
11691   return changed;
11692 }
11693
11694 /* Like recog, but we receive the address of a pointer to a new pattern.
11695    We try to match the rtx that the pointer points to.
11696    If that fails, we may try to modify or replace the pattern,
11697    storing the replacement into the same pointer object.
11698
11699    Modifications include deletion or addition of CLOBBERs.  If the
11700    instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11701    to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11702    (and undo if that fails).
11703
11704    PNOTES is a pointer to a location where any REG_UNUSED notes added for
11705    the CLOBBERs are placed.
11706
11707    The value is the final insn code from the pattern ultimately matched,
11708    or -1.  */
11709
11710 static int
11711 recog_for_combine (rtx *pnewpat, rtx_insn *insn, rtx *pnotes)
11712 {
11713   rtx pat = *pnewpat;
11714   int insn_code_number = recog_for_combine_1 (pnewpat, insn, pnotes);
11715   if (insn_code_number >= 0 || check_asm_operands (pat))
11716     return insn_code_number;
11717
11718   void *marker = get_undo_marker ();
11719   bool changed = false;
11720
11721   if (GET_CODE (pat) == SET)
11722     {
11723       /* For an unrecognized single set of a constant, try placing it in
11724          the constant pool, if this function already uses one.  */
11725       rtx src = SET_SRC (pat);
11726       if (CONSTANT_P (src)
11727           && !CONST_INT_P (src)
11728           && crtl->uses_const_pool)
11729         {
11730           machine_mode mode = GET_MODE (src);
11731           if (mode == VOIDmode)
11732             mode = GET_MODE (SET_DEST (pat));
11733           src = force_const_mem (mode, src);
11734           if (src)
11735             {
11736               SUBST (SET_SRC (pat), src);
11737               changed = true;
11738             }
11739         }
11740       else
11741         changed = change_zero_ext (pat);
11742     }
11743   else if (GET_CODE (pat) == PARALLEL)
11744     {
11745       int i;
11746       for (i = 0; i < XVECLEN (pat, 0); i++)
11747         {
11748           rtx set = XVECEXP (pat, 0, i);
11749           if (GET_CODE (set) == SET)
11750             changed |= change_zero_ext (set);
11751         }
11752     }
11753
11754   if (changed)
11755     {
11756       insn_code_number = recog_for_combine_1 (pnewpat, insn, pnotes);
11757
11758       if (insn_code_number < 0)
11759         undo_to_marker (marker);
11760     }
11761
11762   return insn_code_number;
11763 }
11764 \f
11765 /* Like gen_lowpart_general but for use by combine.  In combine it
11766    is not possible to create any new pseudoregs.  However, it is
11767    safe to create invalid memory addresses, because combine will
11768    try to recognize them and all they will do is make the combine
11769    attempt fail.
11770
11771    If for some reason this cannot do its job, an rtx
11772    (clobber (const_int 0)) is returned.
11773    An insn containing that will not be recognized.  */
11774
11775 static rtx
11776 gen_lowpart_for_combine (machine_mode omode, rtx x)
11777 {
11778   machine_mode imode = GET_MODE (x);
11779   rtx result;
11780
11781   if (omode == imode)
11782     return x;
11783
11784   /* We can only support MODE being wider than a word if X is a
11785      constant integer or has a mode the same size.  */
11786   if (maybe_gt (GET_MODE_SIZE (omode), UNITS_PER_WORD)
11787       && ! (CONST_SCALAR_INT_P (x)
11788             || known_eq (GET_MODE_SIZE (imode), GET_MODE_SIZE (omode))))
11789     goto fail;
11790
11791   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
11792      won't know what to do.  So we will strip off the SUBREG here and
11793      process normally.  */
11794   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
11795     {
11796       x = SUBREG_REG (x);
11797
11798       /* For use in case we fall down into the address adjustments
11799          further below, we need to adjust the known mode and size of
11800          x; imode and isize, since we just adjusted x.  */
11801       imode = GET_MODE (x);
11802
11803       if (imode == omode)
11804         return x;
11805     }
11806
11807   result = gen_lowpart_common (omode, x);
11808
11809   if (result)
11810     return result;
11811
11812   if (MEM_P (x))
11813     {
11814       /* Refuse to work on a volatile memory ref or one with a mode-dependent
11815          address.  */
11816       if (MEM_VOLATILE_P (x)
11817           || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x)))
11818         goto fail;
11819
11820       /* If we want to refer to something bigger than the original memref,
11821          generate a paradoxical subreg instead.  That will force a reload
11822          of the original memref X.  */
11823       if (paradoxical_subreg_p (omode, imode))
11824         return gen_rtx_SUBREG (omode, x, 0);
11825
11826       poly_int64 offset = byte_lowpart_offset (omode, imode);
11827       return adjust_address_nv (x, omode, offset);
11828     }
11829
11830   /* If X is a comparison operator, rewrite it in a new mode.  This
11831      probably won't match, but may allow further simplifications.  */
11832   else if (COMPARISON_P (x)
11833            && SCALAR_INT_MODE_P (imode)
11834            && SCALAR_INT_MODE_P (omode))
11835     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
11836
11837   /* If we couldn't simplify X any other way, just enclose it in a
11838      SUBREG.  Normally, this SUBREG won't match, but some patterns may
11839      include an explicit SUBREG or we may simplify it further in combine.  */
11840   else
11841     {
11842       rtx res;
11843
11844       if (imode == VOIDmode)
11845         {
11846           imode = int_mode_for_mode (omode).require ();
11847           x = gen_lowpart_common (imode, x);
11848           if (x == NULL)
11849             goto fail;
11850         }
11851       res = lowpart_subreg (omode, x, imode);
11852       if (res)
11853         return res;
11854     }
11855
11856  fail:
11857   return gen_rtx_CLOBBER (omode, const0_rtx);
11858 }
11859 \f
11860 /* Try to simplify a comparison between OP0 and a constant OP1,
11861    where CODE is the comparison code that will be tested, into a
11862    (CODE OP0 const0_rtx) form.
11863
11864    The result is a possibly different comparison code to use.
11865    *POP0 and *POP1 may be updated.  */
11866
11867 static enum rtx_code
11868 simplify_compare_const (enum rtx_code code, machine_mode mode,
11869                         rtx *pop0, rtx *pop1)
11870 {
11871   scalar_int_mode int_mode;
11872   rtx op0 = *pop0;
11873   HOST_WIDE_INT const_op = INTVAL (*pop1);
11874
11875   /* Get the constant we are comparing against and turn off all bits
11876      not on in our mode.  */
11877   if (mode != VOIDmode)
11878     const_op = trunc_int_for_mode (const_op, mode);
11879
11880   /* If we are comparing against a constant power of two and the value
11881      being compared can only have that single bit nonzero (e.g., it was
11882      `and'ed with that bit), we can replace this with a comparison
11883      with zero.  */
11884   if (const_op
11885       && (code == EQ || code == NE || code == GEU || code == LTU
11886           /* This optimization is incorrect for signed >= INT_MIN or
11887              < INT_MIN, those are always true or always false.  */
11888           || ((code == GE || code == LT) && const_op > 0))
11889       && is_a <scalar_int_mode> (mode, &int_mode)
11890       && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11891       && pow2p_hwi (const_op & GET_MODE_MASK (int_mode))
11892       && (nonzero_bits (op0, int_mode)
11893           == (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (int_mode))))
11894     {
11895       code = (code == EQ || code == GE || code == GEU ? NE : EQ);
11896       const_op = 0;
11897     }
11898
11899   /* Similarly, if we are comparing a value known to be either -1 or
11900      0 with -1, change it to the opposite comparison against zero.  */
11901   if (const_op == -1
11902       && (code == EQ || code == NE || code == GT || code == LE
11903           || code == GEU || code == LTU)
11904       && is_a <scalar_int_mode> (mode, &int_mode)
11905       && num_sign_bit_copies (op0, int_mode) == GET_MODE_PRECISION (int_mode))
11906     {
11907       code = (code == EQ || code == LE || code == GEU ? NE : EQ);
11908       const_op = 0;
11909     }
11910
11911   /* Do some canonicalizations based on the comparison code.  We prefer
11912      comparisons against zero and then prefer equality comparisons.
11913      If we can reduce the size of a constant, we will do that too.  */
11914   switch (code)
11915     {
11916     case LT:
11917       /* < C is equivalent to <= (C - 1) */
11918       if (const_op > 0)
11919         {
11920           const_op -= 1;
11921           code = LE;
11922           /* ... fall through to LE case below.  */
11923           gcc_fallthrough ();
11924         }
11925       else
11926         break;
11927
11928     case LE:
11929       /* <= C is equivalent to < (C + 1); we do this for C < 0  */
11930       if (const_op < 0)
11931         {
11932           const_op += 1;
11933           code = LT;
11934         }
11935
11936       /* If we are doing a <= 0 comparison on a value known to have
11937          a zero sign bit, we can replace this with == 0.  */
11938       else if (const_op == 0
11939                && is_a <scalar_int_mode> (mode, &int_mode)
11940                && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11941                && (nonzero_bits (op0, int_mode)
11942                    & (HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
11943                == 0)
11944         code = EQ;
11945       break;
11946
11947     case GE:
11948       /* >= C is equivalent to > (C - 1).  */
11949       if (const_op > 0)
11950         {
11951           const_op -= 1;
11952           code = GT;
11953           /* ... fall through to GT below.  */
11954           gcc_fallthrough ();
11955         }
11956       else
11957         break;
11958
11959     case GT:
11960       /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
11961       if (const_op < 0)
11962         {
11963           const_op += 1;
11964           code = GE;
11965         }
11966
11967       /* If we are doing a > 0 comparison on a value known to have
11968          a zero sign bit, we can replace this with != 0.  */
11969       else if (const_op == 0
11970                && is_a <scalar_int_mode> (mode, &int_mode)
11971                && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11972                && (nonzero_bits (op0, int_mode)
11973                    & (HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
11974                == 0)
11975         code = NE;
11976       break;
11977
11978     case LTU:
11979       /* < C is equivalent to <= (C - 1).  */
11980       if (const_op > 0)
11981         {
11982           const_op -= 1;
11983           code = LEU;
11984           /* ... fall through ...  */
11985           gcc_fallthrough ();
11986         }
11987       /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
11988       else if (is_a <scalar_int_mode> (mode, &int_mode)
11989                && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11990                && (((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode))
11991                    == HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
11992         {
11993           const_op = 0;
11994           code = GE;
11995           break;
11996         }
11997       else
11998         break;
11999
12000     case LEU:
12001       /* unsigned <= 0 is equivalent to == 0 */
12002       if (const_op == 0)
12003         code = EQ;
12004       /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
12005       else if (is_a <scalar_int_mode> (mode, &int_mode)
12006                && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12007                && ((unsigned HOST_WIDE_INT) const_op
12008                    == ((HOST_WIDE_INT_1U
12009                         << (GET_MODE_PRECISION (int_mode) - 1)) - 1)))
12010         {
12011           const_op = 0;
12012           code = GE;
12013         }
12014       break;
12015
12016     case GEU:
12017       /* >= C is equivalent to > (C - 1).  */
12018       if (const_op > 1)
12019         {
12020           const_op -= 1;
12021           code = GTU;
12022           /* ... fall through ...  */
12023           gcc_fallthrough ();
12024         }
12025
12026       /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
12027       else if (is_a <scalar_int_mode> (mode, &int_mode)
12028                && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12029                && (((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode))
12030                    == HOST_WIDE_INT_1U << (GET_MODE_PRECISION (int_mode) - 1)))
12031         {
12032           const_op = 0;
12033           code = LT;
12034           break;
12035         }
12036       else
12037         break;
12038
12039     case GTU:
12040       /* unsigned > 0 is equivalent to != 0 */
12041       if (const_op == 0)
12042         code = NE;
12043       /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
12044       else if (is_a <scalar_int_mode> (mode, &int_mode)
12045                && GET_MODE_PRECISION (int_mode) - 1 < HOST_BITS_PER_WIDE_INT
12046                && ((unsigned HOST_WIDE_INT) const_op
12047                    == (HOST_WIDE_INT_1U
12048                        << (GET_MODE_PRECISION (int_mode) - 1)) - 1))
12049         {
12050           const_op = 0;
12051           code = LT;
12052         }
12053       break;
12054
12055     default:
12056       break;
12057     }
12058
12059   /* Narrow non-symmetric comparison of memory and constant as e.g.
12060      x0...x7 <= 0x3fffffffffffffff into x0 <= 0x3f where x0 is the most
12061      significant byte.  Likewise, transform x0...x7 >= 0x4000000000000000 into
12062      x0 >= 0x40.  */
12063   if ((code == LEU || code == LTU || code == GEU || code == GTU)
12064       && is_a <scalar_int_mode> (GET_MODE (op0), &int_mode)
12065       && HWI_COMPUTABLE_MODE_P (int_mode)
12066       && MEM_P (op0)
12067       && !MEM_VOLATILE_P (op0)
12068       /* The optimization makes only sense for constants which are big enough
12069          so that we have a chance to chop off something at all.  */
12070       && ((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode)) > 0xff
12071       /* Ensure that we do not overflow during normalization.  */
12072       && (code != GTU
12073           || ((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode))
12074              < HOST_WIDE_INT_M1U)
12075       && trunc_int_for_mode (const_op, int_mode) == const_op)
12076     {
12077       unsigned HOST_WIDE_INT n
12078         = (unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode);
12079       enum rtx_code adjusted_code;
12080
12081       /* Normalize code to either LEU or GEU.  */
12082       if (code == LTU)
12083         {
12084           --n;
12085           adjusted_code = LEU;
12086         }
12087       else if (code == GTU)
12088         {
12089           ++n;
12090           adjusted_code = GEU;
12091         }
12092       else
12093         adjusted_code = code;
12094
12095       scalar_int_mode narrow_mode_iter;
12096       FOR_EACH_MODE_UNTIL (narrow_mode_iter, int_mode)
12097         {
12098           unsigned nbits = GET_MODE_PRECISION (int_mode)
12099                            - GET_MODE_PRECISION (narrow_mode_iter);
12100           unsigned HOST_WIDE_INT mask = (HOST_WIDE_INT_1U << nbits) - 1;
12101           unsigned HOST_WIDE_INT lower_bits = n & mask;
12102           if ((adjusted_code == LEU && lower_bits == mask)
12103               || (adjusted_code == GEU && lower_bits == 0))
12104             {
12105               n >>= nbits;
12106               break;
12107             }
12108         }
12109
12110       if (narrow_mode_iter < int_mode)
12111         {
12112           if (dump_file && (dump_flags & TDF_DETAILS))
12113             {
12114               fprintf (
12115                 dump_file, "narrow comparison from mode %s to %s: (MEM %s "
12116                 HOST_WIDE_INT_PRINT_HEX ") to (MEM %s "
12117                 HOST_WIDE_INT_PRINT_HEX ").\n", GET_MODE_NAME (int_mode),
12118                 GET_MODE_NAME (narrow_mode_iter), GET_RTX_NAME (code),
12119                 (unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode),
12120                 GET_RTX_NAME (adjusted_code), n);
12121             }
12122           poly_int64 offset = (BYTES_BIG_ENDIAN
12123                                ? 0
12124                                : (GET_MODE_SIZE (int_mode)
12125                                   - GET_MODE_SIZE (narrow_mode_iter)));
12126           *pop0 = adjust_address_nv (op0, narrow_mode_iter, offset);
12127           *pop1 = gen_int_mode (n, narrow_mode_iter);
12128           return adjusted_code;
12129         }
12130     }
12131
12132   *pop1 = GEN_INT (const_op);
12133   return code;
12134 }
12135 \f
12136 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
12137    comparison code that will be tested.
12138
12139    The result is a possibly different comparison code to use.  *POP0 and
12140    *POP1 may be updated.
12141
12142    It is possible that we might detect that a comparison is either always
12143    true or always false.  However, we do not perform general constant
12144    folding in combine, so this knowledge isn't useful.  Such tautologies
12145    should have been detected earlier.  Hence we ignore all such cases.  */
12146
12147 static enum rtx_code
12148 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
12149 {
12150   rtx op0 = *pop0;
12151   rtx op1 = *pop1;
12152   rtx tem, tem1;
12153   int i;
12154   scalar_int_mode mode, inner_mode, tmode;
12155   opt_scalar_int_mode tmode_iter;
12156
12157   /* Try a few ways of applying the same transformation to both operands.  */
12158   while (1)
12159     {
12160       /* The test below this one won't handle SIGN_EXTENDs on these machines,
12161          so check specially.  */
12162       if (!WORD_REGISTER_OPERATIONS
12163           && code != GTU && code != GEU && code != LTU && code != LEU
12164           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
12165           && GET_CODE (XEXP (op0, 0)) == ASHIFT
12166           && GET_CODE (XEXP (op1, 0)) == ASHIFT
12167           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
12168           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
12169           && is_a <scalar_int_mode> (GET_MODE (op0), &mode)
12170           && (is_a <scalar_int_mode>
12171               (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))), &inner_mode))
12172           && inner_mode == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0)))
12173           && CONST_INT_P (XEXP (op0, 1))
12174           && XEXP (op0, 1) == XEXP (op1, 1)
12175           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
12176           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
12177           && (INTVAL (XEXP (op0, 1))
12178               == (GET_MODE_PRECISION (mode)
12179                   - GET_MODE_PRECISION (inner_mode))))
12180         {
12181           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
12182           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
12183         }
12184
12185       /* If both operands are the same constant shift, see if we can ignore the
12186          shift.  We can if the shift is a rotate or if the bits shifted out of
12187          this shift are known to be zero for both inputs and if the type of
12188          comparison is compatible with the shift.  */
12189       if (GET_CODE (op0) == GET_CODE (op1)
12190           && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
12191           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
12192               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
12193                   && (code != GT && code != LT && code != GE && code != LE))
12194               || (GET_CODE (op0) == ASHIFTRT
12195                   && (code != GTU && code != LTU
12196                       && code != GEU && code != LEU)))
12197           && CONST_INT_P (XEXP (op0, 1))
12198           && INTVAL (XEXP (op0, 1)) >= 0
12199           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
12200           && XEXP (op0, 1) == XEXP (op1, 1))
12201         {
12202           machine_mode mode = GET_MODE (op0);
12203           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
12204           int shift_count = INTVAL (XEXP (op0, 1));
12205
12206           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
12207             mask &= (mask >> shift_count) << shift_count;
12208           else if (GET_CODE (op0) == ASHIFT)
12209             mask = (mask & (mask << shift_count)) >> shift_count;
12210
12211           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
12212               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
12213             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
12214           else
12215             break;
12216         }
12217
12218       /* If both operands are AND's of a paradoxical SUBREG by constant, the
12219          SUBREGs are of the same mode, and, in both cases, the AND would
12220          be redundant if the comparison was done in the narrower mode,
12221          do the comparison in the narrower mode (e.g., we are AND'ing with 1
12222          and the operand's possibly nonzero bits are 0xffffff01; in that case
12223          if we only care about QImode, we don't need the AND).  This case
12224          occurs if the output mode of an scc insn is not SImode and
12225          STORE_FLAG_VALUE == 1 (e.g., the 386).
12226
12227          Similarly, check for a case where the AND's are ZERO_EXTEND
12228          operations from some narrower mode even though a SUBREG is not
12229          present.  */
12230
12231       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
12232                && CONST_INT_P (XEXP (op0, 1))
12233                && CONST_INT_P (XEXP (op1, 1)))
12234         {
12235           rtx inner_op0 = XEXP (op0, 0);
12236           rtx inner_op1 = XEXP (op1, 0);
12237           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
12238           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
12239           bool changed = false;
12240
12241           if (paradoxical_subreg_p (inner_op0)
12242               && GET_CODE (inner_op1) == SUBREG
12243               && HWI_COMPUTABLE_MODE_P (GET_MODE (SUBREG_REG (inner_op0)))
12244               && (GET_MODE (SUBREG_REG (inner_op0))
12245                   == GET_MODE (SUBREG_REG (inner_op1)))
12246               && ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
12247                                         GET_MODE (SUBREG_REG (inner_op0)))) == 0
12248               && ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
12249                                         GET_MODE (SUBREG_REG (inner_op1)))) == 0)
12250             {
12251               op0 = SUBREG_REG (inner_op0);
12252               op1 = SUBREG_REG (inner_op1);
12253
12254               /* The resulting comparison is always unsigned since we masked
12255                  off the original sign bit.  */
12256               code = unsigned_condition (code);
12257
12258               changed = true;
12259             }
12260
12261           else if (c0 == c1)
12262             FOR_EACH_MODE_UNTIL (tmode,
12263                                  as_a <scalar_int_mode> (GET_MODE (op0)))
12264               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
12265                 {
12266                   op0 = gen_lowpart_or_truncate (tmode, inner_op0);
12267                   op1 = gen_lowpart_or_truncate (tmode, inner_op1);
12268                   code = unsigned_condition (code);
12269                   changed = true;
12270                   break;
12271                 }
12272
12273           if (! changed)
12274             break;
12275         }
12276
12277       /* If both operands are NOT, we can strip off the outer operation
12278          and adjust the comparison code for swapped operands; similarly for
12279          NEG, except that this must be an equality comparison.  */
12280       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
12281                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
12282                    && (code == EQ || code == NE)))
12283         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
12284
12285       else
12286         break;
12287     }
12288
12289   /* If the first operand is a constant, swap the operands and adjust the
12290      comparison code appropriately, but don't do this if the second operand
12291      is already a constant integer.  */
12292   if (swap_commutative_operands_p (op0, op1))
12293     {
12294       std::swap (op0, op1);
12295       code = swap_condition (code);
12296     }
12297
12298   /* We now enter a loop during which we will try to simplify the comparison.
12299      For the most part, we only are concerned with comparisons with zero,
12300      but some things may really be comparisons with zero but not start
12301      out looking that way.  */
12302
12303   while (CONST_INT_P (op1))
12304     {
12305       machine_mode raw_mode = GET_MODE (op0);
12306       scalar_int_mode int_mode;
12307       int equality_comparison_p;
12308       int sign_bit_comparison_p;
12309       int unsigned_comparison_p;
12310       HOST_WIDE_INT const_op;
12311
12312       /* We only want to handle integral modes.  This catches VOIDmode,
12313          CCmode, and the floating-point modes.  An exception is that we
12314          can handle VOIDmode if OP0 is a COMPARE or a comparison
12315          operation.  */
12316
12317       if (GET_MODE_CLASS (raw_mode) != MODE_INT
12318           && ! (raw_mode == VOIDmode
12319                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
12320         break;
12321
12322       /* Try to simplify the compare to constant, possibly changing the
12323          comparison op, and/or changing op1 to zero.  */
12324       code = simplify_compare_const (code, raw_mode, &op0, &op1);
12325       const_op = INTVAL (op1);
12326
12327       /* Compute some predicates to simplify code below.  */
12328
12329       equality_comparison_p = (code == EQ || code == NE);
12330       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
12331       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
12332                                || code == GEU);
12333
12334       /* If this is a sign bit comparison and we can do arithmetic in
12335          MODE, say that we will only be needing the sign bit of OP0.  */
12336       if (sign_bit_comparison_p
12337           && is_a <scalar_int_mode> (raw_mode, &int_mode)
12338           && HWI_COMPUTABLE_MODE_P (int_mode))
12339         op0 = force_to_mode (op0, int_mode,
12340                              HOST_WIDE_INT_1U
12341                              << (GET_MODE_PRECISION (int_mode) - 1), false);
12342
12343       if (COMPARISON_P (op0))
12344         {
12345           /* We can't do anything if OP0 is a condition code value, rather
12346              than an actual data value.  */
12347           if (const_op != 0
12348               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
12349             break;
12350
12351           /* Get the two operands being compared.  */
12352           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
12353             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
12354           else
12355             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
12356
12357           /* Check for the cases where we simply want the result of the
12358              earlier test or the opposite of that result.  */
12359           if (code == NE || code == EQ
12360               || (val_signbit_known_set_p (raw_mode, STORE_FLAG_VALUE)
12361                   && (code == LT || code == GE)))
12362             {
12363               enum rtx_code new_code;
12364               if (code == LT || code == NE)
12365                 new_code = GET_CODE (op0);
12366               else
12367                 new_code = reversed_comparison_code (op0, NULL);
12368
12369               if (new_code != UNKNOWN)
12370                 {
12371                   code = new_code;
12372                   op0 = tem;
12373                   op1 = tem1;
12374                   continue;
12375                 }
12376             }
12377           break;
12378         }
12379
12380       if (raw_mode == VOIDmode)
12381         break;
12382       scalar_int_mode mode = as_a <scalar_int_mode> (raw_mode);
12383
12384       /* Now try cases based on the opcode of OP0.  If none of the cases
12385          does a "continue", we exit this loop immediately after the
12386          switch.  */
12387
12388       unsigned int mode_width = GET_MODE_PRECISION (mode);
12389       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
12390       switch (GET_CODE (op0))
12391         {
12392         case ZERO_EXTRACT:
12393           /* If we are extracting a single bit from a variable position in
12394              a constant that has only a single bit set and are comparing it
12395              with zero, we can convert this into an equality comparison
12396              between the position and the location of the single bit.  */
12397           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12398              have already reduced the shift count modulo the word size.  */
12399           if (!SHIFT_COUNT_TRUNCATED
12400               && CONST_INT_P (XEXP (op0, 0))
12401               && XEXP (op0, 1) == const1_rtx
12402               && equality_comparison_p && const_op == 0
12403               && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
12404             {
12405               if (BITS_BIG_ENDIAN)
12406                 i = BITS_PER_WORD - 1 - i;
12407
12408               op0 = XEXP (op0, 2);
12409               op1 = GEN_INT (i);
12410               const_op = i;
12411
12412               /* Result is nonzero iff shift count is equal to I.  */
12413               code = reverse_condition (code);
12414               continue;
12415             }
12416
12417           /* fall through */
12418
12419         case SIGN_EXTRACT:
12420           tem = expand_compound_operation (op0);
12421           if (tem != op0)
12422             {
12423               op0 = tem;
12424               continue;
12425             }
12426           break;
12427
12428         case NOT:
12429           /* If testing for equality, we can take the NOT of the constant.  */
12430           if (equality_comparison_p
12431               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
12432             {
12433               op0 = XEXP (op0, 0);
12434               op1 = tem;
12435               continue;
12436             }
12437
12438           /* If just looking at the sign bit, reverse the sense of the
12439              comparison.  */
12440           if (sign_bit_comparison_p)
12441             {
12442               op0 = XEXP (op0, 0);
12443               code = (code == GE ? LT : GE);
12444               continue;
12445             }
12446           break;
12447
12448         case NEG:
12449           /* If testing for equality, we can take the NEG of the constant.  */
12450           if (equality_comparison_p
12451               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
12452             {
12453               op0 = XEXP (op0, 0);
12454               op1 = tem;
12455               continue;
12456             }
12457
12458           /* The remaining cases only apply to comparisons with zero.  */
12459           if (const_op != 0)
12460             break;
12461
12462           /* When X is ABS or is known positive,
12463              (neg X) is < 0 if and only if X != 0.  */
12464
12465           if (sign_bit_comparison_p
12466               && (GET_CODE (XEXP (op0, 0)) == ABS
12467                   || (mode_width <= HOST_BITS_PER_WIDE_INT
12468                       && (nonzero_bits (XEXP (op0, 0), mode)
12469                           & (HOST_WIDE_INT_1U << (mode_width - 1)))
12470                          == 0)))
12471             {
12472               op0 = XEXP (op0, 0);
12473               code = (code == LT ? NE : EQ);
12474               continue;
12475             }
12476
12477           /* If we have NEG of something whose two high-order bits are the
12478              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
12479           if (num_sign_bit_copies (op0, mode) >= 2)
12480             {
12481               op0 = XEXP (op0, 0);
12482               code = swap_condition (code);
12483               continue;
12484             }
12485           break;
12486
12487         case ROTATE:
12488           /* If we are testing equality and our count is a constant, we
12489              can perform the inverse operation on our RHS.  */
12490           if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
12491               && (tem = simplify_binary_operation (ROTATERT, mode,
12492                                                    op1, XEXP (op0, 1))) != 0)
12493             {
12494               op0 = XEXP (op0, 0);
12495               op1 = tem;
12496               continue;
12497             }
12498
12499           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12500              a particular bit.  Convert it to an AND of a constant of that
12501              bit.  This will be converted into a ZERO_EXTRACT.  */
12502           if (const_op == 0 && sign_bit_comparison_p
12503               && CONST_INT_P (XEXP (op0, 1))
12504               && mode_width <= HOST_BITS_PER_WIDE_INT
12505               && UINTVAL (XEXP (op0, 1)) < mode_width)
12506             {
12507               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
12508                                             (HOST_WIDE_INT_1U
12509                                              << (mode_width - 1
12510                                                  - INTVAL (XEXP (op0, 1)))));
12511               code = (code == LT ? NE : EQ);
12512               continue;
12513             }
12514
12515           /* Fall through.  */
12516
12517         case ABS:
12518           /* ABS is ignorable inside an equality comparison with zero.  */
12519           if (const_op == 0 && equality_comparison_p)
12520             {
12521               op0 = XEXP (op0, 0);
12522               continue;
12523             }
12524           break;
12525
12526         case SIGN_EXTEND:
12527           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12528              (compare FOO CONST) if CONST fits in FOO's mode and we
12529              are either testing inequality or have an unsigned
12530              comparison with ZERO_EXTEND or a signed comparison with
12531              SIGN_EXTEND.  But don't do it if we don't have a compare
12532              insn of the given mode, since we'd have to revert it
12533              later on, and then we wouldn't know whether to sign- or
12534              zero-extend.  */
12535           if (is_int_mode (GET_MODE (XEXP (op0, 0)), &mode)
12536               && ! unsigned_comparison_p
12537               && HWI_COMPUTABLE_MODE_P (mode)
12538               && trunc_int_for_mode (const_op, mode) == const_op
12539               && have_insn_for (COMPARE, mode))
12540             {
12541               op0 = XEXP (op0, 0);
12542               continue;
12543             }
12544           break;
12545
12546         case SUBREG:
12547           /* Check for the case where we are comparing A - C1 with C2, that is
12548
12549                (subreg:MODE (plus (A) (-C1))) op (C2)
12550
12551              with C1 a constant, and try to lift the SUBREG, i.e. to do the
12552              comparison in the wider mode.  One of the following two conditions
12553              must be true in order for this to be valid:
12554
12555                1. The mode extension results in the same bit pattern being added
12556                   on both sides and the comparison is equality or unsigned.  As
12557                   C2 has been truncated to fit in MODE, the pattern can only be
12558                   all 0s or all 1s.
12559
12560                2. The mode extension results in the sign bit being copied on
12561                   each side.
12562
12563              The difficulty here is that we have predicates for A but not for
12564              (A - C1) so we need to check that C1 is within proper bounds so
12565              as to perturbate A as little as possible.  */
12566
12567           if (mode_width <= HOST_BITS_PER_WIDE_INT
12568               && subreg_lowpart_p (op0)
12569               && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (op0)),
12570                                          &inner_mode)
12571               && GET_MODE_PRECISION (inner_mode) > mode_width
12572               && GET_CODE (SUBREG_REG (op0)) == PLUS
12573               && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
12574             {
12575               rtx a = XEXP (SUBREG_REG (op0), 0);
12576               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
12577
12578               if ((c1 > 0
12579                    && (unsigned HOST_WIDE_INT) c1
12580                        < HOST_WIDE_INT_1U << (mode_width - 1)
12581                    && (equality_comparison_p || unsigned_comparison_p)
12582                    /* (A - C1) zero-extends if it is positive and sign-extends
12583                       if it is negative, C2 both zero- and sign-extends.  */
12584                    && (((nonzero_bits (a, inner_mode)
12585                          & ~GET_MODE_MASK (mode)) == 0
12586                         && const_op >= 0)
12587                        /* (A - C1) sign-extends if it is positive and 1-extends
12588                           if it is negative, C2 both sign- and 1-extends.  */
12589                        || (num_sign_bit_copies (a, inner_mode)
12590                            > (unsigned int) (GET_MODE_PRECISION (inner_mode)
12591                                              - mode_width)
12592                            && const_op < 0)))
12593                   || ((unsigned HOST_WIDE_INT) c1
12594                        < HOST_WIDE_INT_1U << (mode_width - 2)
12595                       /* (A - C1) always sign-extends, like C2.  */
12596                       && num_sign_bit_copies (a, inner_mode)
12597                          > (unsigned int) (GET_MODE_PRECISION (inner_mode)
12598                                            - (mode_width - 1))))
12599                 {
12600                   op0 = SUBREG_REG (op0);
12601                   continue;
12602                 }
12603             }
12604
12605           /* If the inner mode is narrower and we are extracting the low part,
12606              we can treat the SUBREG as if it were a ZERO_EXTEND ...  */
12607           if (paradoxical_subreg_p (op0))
12608             {
12609               if (WORD_REGISTER_OPERATIONS
12610                   && is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (op0)),
12611                                              &inner_mode)
12612                   && GET_MODE_PRECISION (inner_mode) < BITS_PER_WORD
12613                   /* On WORD_REGISTER_OPERATIONS targets the bits
12614                      beyond sub_mode aren't considered undefined,
12615                      so optimize only if it is a MEM load when MEM loads
12616                      zero extend, because then the upper bits are all zero.  */
12617                   && !(MEM_P (SUBREG_REG (op0))
12618                        && load_extend_op (inner_mode) == ZERO_EXTEND))
12619                 break;
12620               /* FALLTHROUGH to case ZERO_EXTEND */
12621             }
12622           else if (subreg_lowpart_p (op0)
12623                    && GET_MODE_CLASS (mode) == MODE_INT
12624                    && is_int_mode (GET_MODE (SUBREG_REG (op0)), &inner_mode)
12625                    && (code == NE || code == EQ)
12626                    && GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
12627                    && !paradoxical_subreg_p (op0)
12628                    && (nonzero_bits (SUBREG_REG (op0), inner_mode)
12629                        & ~GET_MODE_MASK (mode)) == 0)
12630             {
12631               /* Remove outer subregs that don't do anything.  */
12632               tem = gen_lowpart (inner_mode, op1);
12633
12634               if ((nonzero_bits (tem, inner_mode)
12635                    & ~GET_MODE_MASK (mode)) == 0)
12636                 {
12637                   op0 = SUBREG_REG (op0);
12638                   op1 = tem;
12639                   continue;
12640                 }
12641               break;
12642             }
12643           else
12644             break;
12645
12646           /* FALLTHROUGH */
12647
12648         case ZERO_EXTEND:
12649           if (is_int_mode (GET_MODE (XEXP (op0, 0)), &mode)
12650               && (unsigned_comparison_p || equality_comparison_p)
12651               && HWI_COMPUTABLE_MODE_P (mode)
12652               && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
12653               && const_op >= 0
12654               && have_insn_for (COMPARE, mode))
12655             {
12656               op0 = XEXP (op0, 0);
12657               continue;
12658             }
12659           break;
12660
12661         case PLUS:
12662           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
12663              this for equality comparisons due to pathological cases involving
12664              overflows.  */
12665           if (equality_comparison_p
12666               && (tem = simplify_binary_operation (MINUS, mode,
12667                                                    op1, XEXP (op0, 1))) != 0)
12668             {
12669               op0 = XEXP (op0, 0);
12670               op1 = tem;
12671               continue;
12672             }
12673
12674           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
12675           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
12676               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
12677             {
12678               op0 = XEXP (XEXP (op0, 0), 0);
12679               code = (code == LT ? EQ : NE);
12680               continue;
12681             }
12682           break;
12683
12684         case MINUS:
12685           /* We used to optimize signed comparisons against zero, but that
12686              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
12687              arrive here as equality comparisons, or (GEU, LTU) are
12688              optimized away.  No need to special-case them.  */
12689
12690           /* (eq (minus A B) C) -> (eq A (plus B C)) or
12691              (eq B (minus A C)), whichever simplifies.  We can only do
12692              this for equality comparisons due to pathological cases involving
12693              overflows.  */
12694           if (equality_comparison_p
12695               && (tem = simplify_binary_operation (PLUS, mode,
12696                                                    XEXP (op0, 1), op1)) != 0)
12697             {
12698               op0 = XEXP (op0, 0);
12699               op1 = tem;
12700               continue;
12701             }
12702
12703           if (equality_comparison_p
12704               && (tem = simplify_binary_operation (MINUS, mode,
12705                                                    XEXP (op0, 0), op1)) != 0)
12706             {
12707               op0 = XEXP (op0, 1);
12708               op1 = tem;
12709               continue;
12710             }
12711
12712           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12713              of bits in X minus 1, is one iff X > 0.  */
12714           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
12715               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
12716               && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
12717               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
12718             {
12719               op0 = XEXP (op0, 1);
12720               code = (code == GE ? LE : GT);
12721               continue;
12722             }
12723           break;
12724
12725         case XOR:
12726           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
12727              if C is zero or B is a constant.  */
12728           if (equality_comparison_p
12729               && (tem = simplify_binary_operation (XOR, mode,
12730                                                    XEXP (op0, 1), op1)) != 0)
12731             {
12732               op0 = XEXP (op0, 0);
12733               op1 = tem;
12734               continue;
12735             }
12736           break;
12737
12738
12739         case IOR:
12740           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12741              iff X <= 0.  */
12742           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
12743               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
12744               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
12745             {
12746               op0 = XEXP (op0, 1);
12747               code = (code == GE ? GT : LE);
12748               continue;
12749             }
12750           break;
12751
12752         case AND:
12753           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
12754              will be converted to a ZERO_EXTRACT later.  */
12755           if (const_op == 0 && equality_comparison_p
12756               && GET_CODE (XEXP (op0, 0)) == ASHIFT
12757               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
12758             {
12759               op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
12760                                       XEXP (XEXP (op0, 0), 1));
12761               op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
12762               continue;
12763             }
12764
12765           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12766              zero and X is a comparison and C1 and C2 describe only bits set
12767              in STORE_FLAG_VALUE, we can compare with X.  */
12768           if (const_op == 0 && equality_comparison_p
12769               && mode_width <= HOST_BITS_PER_WIDE_INT
12770               && CONST_INT_P (XEXP (op0, 1))
12771               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
12772               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
12773               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
12774               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
12775             {
12776               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
12777                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
12778               if ((~STORE_FLAG_VALUE & mask) == 0
12779                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
12780                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
12781                           && COMPARISON_P (tem))))
12782                 {
12783                   op0 = XEXP (XEXP (op0, 0), 0);
12784                   continue;
12785                 }
12786             }
12787
12788           /* If we are doing an equality comparison of an AND of a bit equal
12789              to the sign bit, replace this with a LT or GE comparison of
12790              the underlying value.  */
12791           if (equality_comparison_p
12792               && const_op == 0
12793               && CONST_INT_P (XEXP (op0, 1))
12794               && mode_width <= HOST_BITS_PER_WIDE_INT
12795               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
12796                   == HOST_WIDE_INT_1U << (mode_width - 1)))
12797             {
12798               op0 = XEXP (op0, 0);
12799               code = (code == EQ ? GE : LT);
12800               continue;
12801             }
12802
12803           /* If this AND operation is really a ZERO_EXTEND from a narrower
12804              mode, the constant fits within that mode, and this is either an
12805              equality or unsigned comparison, try to do this comparison in
12806              the narrower mode.
12807
12808              Note that in:
12809
12810              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12811              -> (ne:DI (reg:SI 4) (const_int 0))
12812
12813              unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12814              known to hold a value of the required mode the
12815              transformation is invalid.  */
12816           if ((equality_comparison_p || unsigned_comparison_p)
12817               && CONST_INT_P (XEXP (op0, 1))
12818               && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
12819                                    & GET_MODE_MASK (mode))
12820                                   + 1)) >= 0
12821               && const_op >> i == 0
12822               && int_mode_for_size (i, 1).exists (&tmode))
12823             {
12824               op0 = gen_lowpart_or_truncate (tmode, XEXP (op0, 0));
12825               continue;
12826             }
12827
12828           /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12829              fits in both M1 and M2 and the SUBREG is either paradoxical
12830              or represents the low part, permute the SUBREG and the AND
12831              and try again.  */
12832           if (GET_CODE (XEXP (op0, 0)) == SUBREG
12833               && CONST_INT_P (XEXP (op0, 1)))
12834             {
12835               unsigned HOST_WIDE_INT c1 = INTVAL (XEXP (op0, 1));
12836               /* Require an integral mode, to avoid creating something like
12837                  (AND:SF ...).  */
12838               if ((is_a <scalar_int_mode>
12839                    (GET_MODE (SUBREG_REG (XEXP (op0, 0))), &tmode))
12840                   /* It is unsafe to commute the AND into the SUBREG if the
12841                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12842                      not defined.  As originally written the upper bits
12843                      have a defined value due to the AND operation.
12844                      However, if we commute the AND inside the SUBREG then
12845                      they no longer have defined values and the meaning of
12846                      the code has been changed.
12847                      Also C1 should not change value in the smaller mode,
12848                      see PR67028 (a positive C1 can become negative in the
12849                      smaller mode, so that the AND does no longer mask the
12850                      upper bits).  */
12851                   && ((WORD_REGISTER_OPERATIONS
12852                        && mode_width > GET_MODE_PRECISION (tmode)
12853                        && mode_width <= BITS_PER_WORD
12854                        && trunc_int_for_mode (c1, tmode) == (HOST_WIDE_INT) c1)
12855                       || (mode_width <= GET_MODE_PRECISION (tmode)
12856                           && subreg_lowpart_p (XEXP (op0, 0))))
12857                   && mode_width <= HOST_BITS_PER_WIDE_INT
12858                   && HWI_COMPUTABLE_MODE_P (tmode)
12859                   && (c1 & ~mask) == 0
12860                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
12861                   && c1 != mask
12862                   && c1 != GET_MODE_MASK (tmode))
12863                 {
12864                   op0 = simplify_gen_binary (AND, tmode,
12865                                              SUBREG_REG (XEXP (op0, 0)),
12866                                              gen_int_mode (c1, tmode));
12867                   op0 = gen_lowpart (mode, op0);
12868                   continue;
12869                 }
12870             }
12871
12872           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
12873           if (const_op == 0 && equality_comparison_p
12874               && XEXP (op0, 1) == const1_rtx
12875               && GET_CODE (XEXP (op0, 0)) == NOT)
12876             {
12877               op0 = simplify_and_const_int (NULL_RTX, mode,
12878                                             XEXP (XEXP (op0, 0), 0), 1);
12879               code = (code == NE ? EQ : NE);
12880               continue;
12881             }
12882
12883           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12884              (eq (and (lshiftrt X) 1) 0).
12885              Also handle the case where (not X) is expressed using xor.  */
12886           if (const_op == 0 && equality_comparison_p
12887               && XEXP (op0, 1) == const1_rtx
12888               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
12889             {
12890               rtx shift_op = XEXP (XEXP (op0, 0), 0);
12891               rtx shift_count = XEXP (XEXP (op0, 0), 1);
12892
12893               if (GET_CODE (shift_op) == NOT
12894                   || (GET_CODE (shift_op) == XOR
12895                       && CONST_INT_P (XEXP (shift_op, 1))
12896                       && CONST_INT_P (shift_count)
12897                       && HWI_COMPUTABLE_MODE_P (mode)
12898                       && (UINTVAL (XEXP (shift_op, 1))
12899                           == HOST_WIDE_INT_1U
12900                                << INTVAL (shift_count))))
12901                 {
12902                   op0
12903                     = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
12904                   op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
12905                   code = (code == NE ? EQ : NE);
12906                   continue;
12907                 }
12908             }
12909           break;
12910
12911         case ASHIFT:
12912           /* If we have (compare (ashift FOO N) (const_int C)) and
12913              the high order N bits of FOO (N+1 if an inequality comparison)
12914              are known to be zero, we can do this by comparing FOO with C
12915              shifted right N bits so long as the low-order N bits of C are
12916              zero.  */
12917           if (CONST_INT_P (XEXP (op0, 1))
12918               && INTVAL (XEXP (op0, 1)) >= 0
12919               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
12920                   < HOST_BITS_PER_WIDE_INT)
12921               && (((unsigned HOST_WIDE_INT) const_op
12922                    & ((HOST_WIDE_INT_1U << INTVAL (XEXP (op0, 1)))
12923                       - 1)) == 0)
12924               && mode_width <= HOST_BITS_PER_WIDE_INT
12925               && (nonzero_bits (XEXP (op0, 0), mode)
12926                   & ~(mask >> (INTVAL (XEXP (op0, 1))
12927                                + ! equality_comparison_p))) == 0)
12928             {
12929               /* We must perform a logical shift, not an arithmetic one,
12930                  as we want the top N bits of C to be zero.  */
12931               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
12932
12933               temp >>= INTVAL (XEXP (op0, 1));
12934               op1 = gen_int_mode (temp, mode);
12935               op0 = XEXP (op0, 0);
12936               continue;
12937             }
12938
12939           /* If we are doing a sign bit comparison, it means we are testing
12940              a particular bit.  Convert it to the appropriate AND.  */
12941           if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
12942               && mode_width <= HOST_BITS_PER_WIDE_INT)
12943             {
12944               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
12945                                             (HOST_WIDE_INT_1U
12946                                              << (mode_width - 1
12947                                                  - INTVAL (XEXP (op0, 1)))));
12948               code = (code == LT ? NE : EQ);
12949               continue;
12950             }
12951
12952           /* If this an equality comparison with zero and we are shifting
12953              the low bit to the sign bit, we can convert this to an AND of the
12954              low-order bit.  */
12955           if (const_op == 0 && equality_comparison_p
12956               && CONST_INT_P (XEXP (op0, 1))
12957               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
12958             {
12959               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
12960               continue;
12961             }
12962           break;
12963
12964         case ASHIFTRT:
12965           /* If this is an equality comparison with zero, we can do this
12966              as a logical shift, which might be much simpler.  */
12967           if (equality_comparison_p && const_op == 0
12968               && CONST_INT_P (XEXP (op0, 1)))
12969             {
12970               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
12971                                           XEXP (op0, 0),
12972                                           INTVAL (XEXP (op0, 1)));
12973               continue;
12974             }
12975
12976           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12977              do the comparison in a narrower mode.  */
12978           if (! unsigned_comparison_p
12979               && CONST_INT_P (XEXP (op0, 1))
12980               && GET_CODE (XEXP (op0, 0)) == ASHIFT
12981               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
12982               && (int_mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 1)
12983                   .exists (&tmode))
12984               && (((unsigned HOST_WIDE_INT) const_op
12985                    + (GET_MODE_MASK (tmode) >> 1) + 1)
12986                   <= GET_MODE_MASK (tmode)))
12987             {
12988               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
12989               continue;
12990             }
12991
12992           /* Likewise if OP0 is a PLUS of a sign extension with a
12993              constant, which is usually represented with the PLUS
12994              between the shifts.  */
12995           if (! unsigned_comparison_p
12996               && CONST_INT_P (XEXP (op0, 1))
12997               && GET_CODE (XEXP (op0, 0)) == PLUS
12998               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
12999               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
13000               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
13001               && (int_mode_for_size (mode_width - INTVAL (XEXP (op0, 1)), 1)
13002                   .exists (&tmode))
13003               && (((unsigned HOST_WIDE_INT) const_op
13004                    + (GET_MODE_MASK (tmode) >> 1) + 1)
13005                   <= GET_MODE_MASK (tmode)))
13006             {
13007               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
13008               rtx add_const = XEXP (XEXP (op0, 0), 1);
13009               rtx new_const = simplify_gen_binary (ASHIFTRT, mode,
13010                                                    add_const, XEXP (op0, 1));
13011
13012               op0 = simplify_gen_binary (PLUS, tmode,
13013                                          gen_lowpart (tmode, inner),
13014                                          new_const);
13015               continue;
13016             }
13017
13018           /* FALLTHROUGH */
13019         case LSHIFTRT:
13020           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
13021              the low order N bits of FOO are known to be zero, we can do this
13022              by comparing FOO with C shifted left N bits so long as no
13023              overflow occurs.  Even if the low order N bits of FOO aren't known
13024              to be zero, if the comparison is >= or < we can use the same
13025              optimization and for > or <= by setting all the low
13026              order N bits in the comparison constant.  */
13027           if (CONST_INT_P (XEXP (op0, 1))
13028               && INTVAL (XEXP (op0, 1)) > 0
13029               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
13030               && mode_width <= HOST_BITS_PER_WIDE_INT
13031               && (((unsigned HOST_WIDE_INT) const_op
13032                    + (GET_CODE (op0) != LSHIFTRT
13033                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
13034                          + 1)
13035                       : 0))
13036                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
13037             {
13038               unsigned HOST_WIDE_INT low_bits
13039                 = (nonzero_bits (XEXP (op0, 0), mode)
13040                    & ((HOST_WIDE_INT_1U
13041                        << INTVAL (XEXP (op0, 1))) - 1));
13042               if (low_bits == 0 || !equality_comparison_p)
13043                 {
13044                   /* If the shift was logical, then we must make the condition
13045                      unsigned.  */
13046                   if (GET_CODE (op0) == LSHIFTRT)
13047                     code = unsigned_condition (code);
13048
13049                   const_op = (unsigned HOST_WIDE_INT) const_op
13050                               << INTVAL (XEXP (op0, 1));
13051                   if (low_bits != 0
13052                       && (code == GT || code == GTU
13053                           || code == LE || code == LEU))
13054                     const_op
13055                       |= ((HOST_WIDE_INT_1 << INTVAL (XEXP (op0, 1))) - 1);
13056                   op1 = GEN_INT (const_op);
13057                   op0 = XEXP (op0, 0);
13058                   continue;
13059                 }
13060             }
13061
13062           /* If we are using this shift to extract just the sign bit, we
13063              can replace this with an LT or GE comparison.  */
13064           if (const_op == 0
13065               && (equality_comparison_p || sign_bit_comparison_p)
13066               && CONST_INT_P (XEXP (op0, 1))
13067               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
13068             {
13069               op0 = XEXP (op0, 0);
13070               code = (code == NE || code == GT ? LT : GE);
13071               continue;
13072             }
13073           break;
13074
13075         default:
13076           break;
13077         }
13078
13079       break;
13080     }
13081
13082   /* Now make any compound operations involved in this comparison.  Then,
13083      check for an outmost SUBREG on OP0 that is not doing anything or is
13084      paradoxical.  The latter transformation must only be performed when
13085      it is known that the "extra" bits will be the same in op0 and op1 or
13086      that they don't matter.  There are three cases to consider:
13087
13088      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
13089      care bits and we can assume they have any convenient value.  So
13090      making the transformation is safe.
13091
13092      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
13093      In this case the upper bits of op0 are undefined.  We should not make
13094      the simplification in that case as we do not know the contents of
13095      those bits.
13096
13097      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
13098      In that case we know those bits are zeros or ones.  We must also be
13099      sure that they are the same as the upper bits of op1.
13100
13101      We can never remove a SUBREG for a non-equality comparison because
13102      the sign bit is in a different place in the underlying object.  */
13103
13104   rtx_code op0_mco_code = SET;
13105   if (op1 == const0_rtx)
13106     op0_mco_code = code == NE || code == EQ ? EQ : COMPARE;
13107
13108   op0 = make_compound_operation (op0, op0_mco_code);
13109   op1 = make_compound_operation (op1, SET);
13110
13111   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
13112       && is_int_mode (GET_MODE (op0), &mode)
13113       && is_int_mode (GET_MODE (SUBREG_REG (op0)), &inner_mode)
13114       && (code == NE || code == EQ))
13115     {
13116       if (paradoxical_subreg_p (op0))
13117         {
13118           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
13119              implemented.  */
13120           if (REG_P (SUBREG_REG (op0)))
13121             {
13122               op0 = SUBREG_REG (op0);
13123               op1 = gen_lowpart (inner_mode, op1);
13124             }
13125         }
13126       else if (GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT
13127                && (nonzero_bits (SUBREG_REG (op0), inner_mode)
13128                    & ~GET_MODE_MASK (mode)) == 0)
13129         {
13130           tem = gen_lowpart (inner_mode, op1);
13131
13132           if ((nonzero_bits (tem, inner_mode) & ~GET_MODE_MASK (mode)) == 0)
13133             op0 = SUBREG_REG (op0), op1 = tem;
13134         }
13135     }
13136
13137   /* We now do the opposite procedure: Some machines don't have compare
13138      insns in all modes.  If OP0's mode is an integer mode smaller than a
13139      word and we can't do a compare in that mode, see if there is a larger
13140      mode for which we can do the compare.  There are a number of cases in
13141      which we can use the wider mode.  */
13142
13143   if (is_int_mode (GET_MODE (op0), &mode)
13144       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
13145       && ! have_insn_for (COMPARE, mode))
13146     FOR_EACH_WIDER_MODE (tmode_iter, mode)
13147       {
13148         tmode = tmode_iter.require ();
13149         if (!HWI_COMPUTABLE_MODE_P (tmode))
13150           break;
13151         if (have_insn_for (COMPARE, tmode))
13152           {
13153             int zero_extended;
13154
13155             /* If this is a test for negative, we can make an explicit
13156                test of the sign bit.  Test this first so we can use
13157                a paradoxical subreg to extend OP0.  */
13158
13159             if (op1 == const0_rtx && (code == LT || code == GE)
13160                 && HWI_COMPUTABLE_MODE_P (mode))
13161               {
13162                 unsigned HOST_WIDE_INT sign
13163                   = HOST_WIDE_INT_1U << (GET_MODE_BITSIZE (mode) - 1);
13164                 op0 = simplify_gen_binary (AND, tmode,
13165                                            gen_lowpart (tmode, op0),
13166                                            gen_int_mode (sign, tmode));
13167                 code = (code == LT) ? NE : EQ;
13168                 break;
13169               }
13170
13171             /* If the only nonzero bits in OP0 and OP1 are those in the
13172                narrower mode and this is an equality or unsigned comparison,
13173                we can use the wider mode.  Similarly for sign-extended
13174                values, in which case it is true for all comparisons.  */
13175             zero_extended = ((code == EQ || code == NE
13176                               || code == GEU || code == GTU
13177                               || code == LEU || code == LTU)
13178                              && (nonzero_bits (op0, tmode)
13179                                  & ~GET_MODE_MASK (mode)) == 0
13180                              && ((CONST_INT_P (op1)
13181                                   || (nonzero_bits (op1, tmode)
13182                                       & ~GET_MODE_MASK (mode)) == 0)));
13183
13184             if (zero_extended
13185                 || ((num_sign_bit_copies (op0, tmode)
13186                      > (unsigned int) (GET_MODE_PRECISION (tmode)
13187                                        - GET_MODE_PRECISION (mode)))
13188                     && (num_sign_bit_copies (op1, tmode)
13189                         > (unsigned int) (GET_MODE_PRECISION (tmode)
13190                                           - GET_MODE_PRECISION (mode)))))
13191               {
13192                 /* If OP0 is an AND and we don't have an AND in MODE either,
13193                    make a new AND in the proper mode.  */
13194                 if (GET_CODE (op0) == AND
13195                     && !have_insn_for (AND, mode))
13196                   op0 = simplify_gen_binary (AND, tmode,
13197                                              gen_lowpart (tmode,
13198                                                           XEXP (op0, 0)),
13199                                              gen_lowpart (tmode,
13200                                                           XEXP (op0, 1)));
13201                 else
13202                   {
13203                     if (zero_extended)
13204                       {
13205                         op0 = simplify_gen_unary (ZERO_EXTEND, tmode,
13206                                                   op0, mode);
13207                         op1 = simplify_gen_unary (ZERO_EXTEND, tmode,
13208                                                   op1, mode);
13209                       }
13210                     else
13211                       {
13212                         op0 = simplify_gen_unary (SIGN_EXTEND, tmode,
13213                                                   op0, mode);
13214                         op1 = simplify_gen_unary (SIGN_EXTEND, tmode,
13215                                                   op1, mode);
13216                       }
13217                     break;
13218                   }
13219               }
13220           }
13221       }
13222
13223   /* We may have changed the comparison operands.  Re-canonicalize.  */
13224   if (swap_commutative_operands_p (op0, op1))
13225     {
13226       std::swap (op0, op1);
13227       code = swap_condition (code);
13228     }
13229
13230   /* If this machine only supports a subset of valid comparisons, see if we
13231      can convert an unsupported one into a supported one.  */
13232   target_canonicalize_comparison (&code, &op0, &op1, 0);
13233
13234   *pop0 = op0;
13235   *pop1 = op1;
13236
13237   return code;
13238 }
13239 \f
13240 /* Utility function for record_value_for_reg.  Count number of
13241    rtxs in X.  */
13242 static int
13243 count_rtxs (rtx x)
13244 {
13245   enum rtx_code code = GET_CODE (x);
13246   const char *fmt;
13247   int i, j, ret = 1;
13248
13249   if (GET_RTX_CLASS (code) == RTX_BIN_ARITH
13250       || GET_RTX_CLASS (code) == RTX_COMM_ARITH)
13251     {
13252       rtx x0 = XEXP (x, 0);
13253       rtx x1 = XEXP (x, 1);
13254
13255       if (x0 == x1)
13256         return 1 + 2 * count_rtxs (x0);
13257
13258       if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH
13259            || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH)
13260           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13261         return 2 + 2 * count_rtxs (x0)
13262                + count_rtxs (x == XEXP (x1, 0)
13263                              ? XEXP (x1, 1) : XEXP (x1, 0));
13264
13265       if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH
13266            || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH)
13267           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13268         return 2 + 2 * count_rtxs (x1)
13269                + count_rtxs (x == XEXP (x0, 0)
13270                              ? XEXP (x0, 1) : XEXP (x0, 0));
13271     }
13272
13273   fmt = GET_RTX_FORMAT (code);
13274   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13275     if (fmt[i] == 'e')
13276       ret += count_rtxs (XEXP (x, i));
13277     else if (fmt[i] == 'E')
13278       for (j = 0; j < XVECLEN (x, i); j++)
13279         ret += count_rtxs (XVECEXP (x, i, j));
13280
13281   return ret;
13282 }
13283 \f
13284 /* Utility function for following routine.  Called when X is part of a value
13285    being stored into last_set_value.  Sets last_set_table_tick
13286    for each register mentioned.  Similar to mention_regs in cse.cc  */
13287
13288 static void
13289 update_table_tick (rtx x)
13290 {
13291   enum rtx_code code = GET_CODE (x);
13292   const char *fmt = GET_RTX_FORMAT (code);
13293   int i, j;
13294
13295   if (code == REG)
13296     {
13297       unsigned int regno = REGNO (x);
13298       unsigned int endregno = END_REGNO (x);
13299       unsigned int r;
13300
13301       for (r = regno; r < endregno; r++)
13302         {
13303           reg_stat_type *rsp = &reg_stat[r];
13304           rsp->last_set_table_tick = label_tick;
13305         }
13306
13307       return;
13308     }
13309
13310   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13311     if (fmt[i] == 'e')
13312       {
13313         /* Check for identical subexpressions.  If x contains
13314            identical subexpression we only have to traverse one of
13315            them.  */
13316         if (i == 0 && ARITHMETIC_P (x))
13317           {
13318             /* Note that at this point x1 has already been
13319                processed.  */
13320             rtx x0 = XEXP (x, 0);
13321             rtx x1 = XEXP (x, 1);
13322
13323             /* If x0 and x1 are identical then there is no need to
13324                process x0.  */
13325             if (x0 == x1)
13326               break;
13327
13328             /* If x0 is identical to a subexpression of x1 then while
13329                processing x1, x0 has already been processed.  Thus we
13330                are done with x.  */
13331             if (ARITHMETIC_P (x1)
13332                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13333               break;
13334
13335             /* If x1 is identical to a subexpression of x0 then we
13336                still have to process the rest of x0.  */
13337             if (ARITHMETIC_P (x0)
13338                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13339               {
13340                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
13341                 break;
13342               }
13343           }
13344
13345         update_table_tick (XEXP (x, i));
13346       }
13347     else if (fmt[i] == 'E')
13348       for (j = 0; j < XVECLEN (x, i); j++)
13349         update_table_tick (XVECEXP (x, i, j));
13350 }
13351
13352 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
13353    are saying that the register is clobbered and we no longer know its
13354    value.  If INSN is zero, don't update reg_stat[].last_set; this is
13355    only permitted with VALUE also zero and is used to invalidate the
13356    register.  */
13357
13358 static void
13359 record_value_for_reg (rtx reg, rtx_insn *insn, rtx value)
13360 {
13361   unsigned int regno = REGNO (reg);
13362   unsigned int endregno = END_REGNO (reg);
13363   unsigned int i;
13364   reg_stat_type *rsp;
13365
13366   /* If VALUE contains REG and we have a previous value for REG, substitute
13367      the previous value.  */
13368   if (value && insn && reg_overlap_mentioned_p (reg, value))
13369     {
13370       rtx tem;
13371
13372       /* Set things up so get_last_value is allowed to see anything set up to
13373          our insn.  */
13374       subst_low_luid = DF_INSN_LUID (insn);
13375       tem = get_last_value (reg);
13376
13377       /* If TEM is simply a binary operation with two CLOBBERs as operands,
13378          it isn't going to be useful and will take a lot of time to process,
13379          so just use the CLOBBER.  */
13380
13381       if (tem)
13382         {
13383           if (ARITHMETIC_P (tem)
13384               && GET_CODE (XEXP (tem, 0)) == CLOBBER
13385               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
13386             tem = XEXP (tem, 0);
13387           else if (count_occurrences (value, reg, 1) >= 2)
13388             {
13389               /* If there are two or more occurrences of REG in VALUE,
13390                  prevent the value from growing too much.  */
13391               if (count_rtxs (tem) > param_max_last_value_rtl)
13392                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
13393             }
13394
13395           value = replace_rtx (copy_rtx (value), reg, tem);
13396         }
13397     }
13398
13399   /* For each register modified, show we don't know its value, that
13400      we don't know about its bitwise content, that its value has been
13401      updated, and that we don't know the location of the death of the
13402      register.  */
13403   for (i = regno; i < endregno; i++)
13404     {
13405       rsp = &reg_stat[i];
13406
13407       if (insn)
13408         rsp->last_set = insn;
13409
13410       rsp->last_set_value = 0;
13411       rsp->last_set_mode = VOIDmode;
13412       rsp->last_set_nonzero_bits = 0;
13413       rsp->last_set_sign_bit_copies = 0;
13414       rsp->last_death = 0;
13415       rsp->truncated_to_mode = VOIDmode;
13416     }
13417
13418   /* Mark registers that are being referenced in this value.  */
13419   if (value)
13420     update_table_tick (value);
13421
13422   /* Now update the status of each register being set.
13423      If someone is using this register in this block, set this register
13424      to invalid since we will get confused between the two lives in this
13425      basic block.  This makes using this register always invalid.  In cse, we
13426      scan the table to invalidate all entries using this register, but this
13427      is too much work for us.  */
13428
13429   for (i = regno; i < endregno; i++)
13430     {
13431       rsp = &reg_stat[i];
13432       rsp->last_set_label = label_tick;
13433       if (!insn
13434           || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
13435         rsp->last_set_invalid = true;
13436       else
13437         rsp->last_set_invalid = false;
13438     }
13439
13440   /* The value being assigned might refer to X (like in "x++;").  In that
13441      case, we must replace it with (clobber (const_int 0)) to prevent
13442      infinite loops.  */
13443   rsp = &reg_stat[regno];
13444   if (value && !get_last_value_validate (&value, insn, label_tick, false))
13445     {
13446       value = copy_rtx (value);
13447       if (!get_last_value_validate (&value, insn, label_tick, true))
13448         value = 0;
13449     }
13450
13451   /* For the main register being modified, update the value, the mode, the
13452      nonzero bits, and the number of sign bit copies.  */
13453
13454   rsp->last_set_value = value;
13455
13456   if (value)
13457     {
13458       machine_mode mode = GET_MODE (reg);
13459       subst_low_luid = DF_INSN_LUID (insn);
13460       rsp->last_set_mode = mode;
13461       if (GET_MODE_CLASS (mode) == MODE_INT
13462           && HWI_COMPUTABLE_MODE_P (mode))
13463         mode = nonzero_bits_mode;
13464       rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
13465       rsp->last_set_sign_bit_copies
13466         = num_sign_bit_copies (value, GET_MODE (reg));
13467     }
13468 }
13469
13470 /* Called via note_stores from record_dead_and_set_regs to handle one
13471    SET or CLOBBER in an insn.  DATA is the instruction in which the
13472    set is occurring.  */
13473
13474 static void
13475 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
13476 {
13477   rtx_insn *record_dead_insn = (rtx_insn *) data;
13478
13479   if (GET_CODE (dest) == SUBREG)
13480     dest = SUBREG_REG (dest);
13481
13482   if (!record_dead_insn)
13483     {
13484       if (REG_P (dest))
13485         record_value_for_reg (dest, NULL, NULL_RTX);
13486       return;
13487     }
13488
13489   if (REG_P (dest))
13490     {
13491       /* If we are setting the whole register, we know its value.  */
13492       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
13493         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
13494       /* We can handle a SUBREG if it's the low part, but we must be
13495          careful with paradoxical SUBREGs on RISC architectures because
13496          we cannot strip e.g. an extension around a load and record the
13497          naked load since the RTL middle-end considers that the upper bits
13498          are defined according to LOAD_EXTEND_OP.  */
13499       else if (GET_CODE (setter) == SET
13500                && GET_CODE (SET_DEST (setter)) == SUBREG
13501                && SUBREG_REG (SET_DEST (setter)) == dest
13502                && known_le (GET_MODE_PRECISION (GET_MODE (dest)),
13503                             BITS_PER_WORD)
13504                && subreg_lowpart_p (SET_DEST (setter)))
13505         {
13506           if (WORD_REGISTER_OPERATIONS
13507               && word_register_operation_p (SET_SRC (setter))
13508               && paradoxical_subreg_p (SET_DEST (setter)))
13509             record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
13510           else if (!partial_subreg_p (SET_DEST (setter)))
13511             record_value_for_reg (dest, record_dead_insn,
13512                                   gen_lowpart (GET_MODE (dest),
13513                                                SET_SRC (setter)));
13514           else
13515             {
13516               record_value_for_reg (dest, record_dead_insn,
13517                                     gen_lowpart (GET_MODE (dest),
13518                                                  SET_SRC (setter)));
13519
13520               unsigned HOST_WIDE_INT mask;
13521               reg_stat_type *rsp = &reg_stat[REGNO (dest)];
13522               mask = GET_MODE_MASK (GET_MODE (SET_DEST (setter)));
13523               rsp->last_set_nonzero_bits |= ~mask;
13524               rsp->last_set_sign_bit_copies = 1;
13525             }
13526         }
13527       /* Otherwise show that we don't know the value.  */
13528       else
13529         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
13530     }
13531   else if (MEM_P (dest)
13532            /* Ignore pushes, they clobber nothing.  */
13533            && ! push_operand (dest, GET_MODE (dest)))
13534     mem_last_set = DF_INSN_LUID (record_dead_insn);
13535 }
13536
13537 /* Update the records of when each REG was most recently set or killed
13538    for the things done by INSN.  This is the last thing done in processing
13539    INSN in the combiner loop.
13540
13541    We update reg_stat[], in particular fields last_set, last_set_value,
13542    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13543    last_death, and also the similar information mem_last_set (which insn
13544    most recently modified memory) and last_call_luid (which insn was the
13545    most recent subroutine call).  */
13546
13547 static void
13548 record_dead_and_set_regs (rtx_insn *insn)
13549 {
13550   rtx link;
13551   unsigned int i;
13552
13553   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
13554     {
13555       if (REG_NOTE_KIND (link) == REG_DEAD
13556           && REG_P (XEXP (link, 0)))
13557         {
13558           unsigned int regno = REGNO (XEXP (link, 0));
13559           unsigned int endregno = END_REGNO (XEXP (link, 0));
13560
13561           for (i = regno; i < endregno; i++)
13562             {
13563               reg_stat_type *rsp;
13564
13565               rsp = &reg_stat[i];
13566               rsp->last_death = insn;
13567             }
13568         }
13569       else if (REG_NOTE_KIND (link) == REG_INC)
13570         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
13571     }
13572
13573   if (CALL_P (insn))
13574     {
13575       HARD_REG_SET callee_clobbers
13576         = insn_callee_abi (insn).full_and_partial_reg_clobbers ();
13577       hard_reg_set_iterator hrsi;
13578       EXECUTE_IF_SET_IN_HARD_REG_SET (callee_clobbers, 0, i, hrsi)
13579         {
13580           reg_stat_type *rsp;
13581
13582           /* ??? We could try to preserve some information from the last
13583              set of register I if the call doesn't actually clobber
13584              (reg:last_set_mode I), which might be true for ABIs with
13585              partial clobbers.  However, it would be difficult to
13586              update last_set_nonzero_bits and last_sign_bit_copies
13587              to account for the part of I that actually was clobbered.
13588              It wouldn't help much anyway, since we rarely see this
13589              situation before RA.  */
13590           rsp = &reg_stat[i];
13591           rsp->last_set_invalid = true;
13592           rsp->last_set = insn;
13593           rsp->last_set_value = 0;
13594           rsp->last_set_mode = VOIDmode;
13595           rsp->last_set_nonzero_bits = 0;
13596           rsp->last_set_sign_bit_copies = 0;
13597           rsp->last_death = 0;
13598           rsp->truncated_to_mode = VOIDmode;
13599         }
13600
13601       last_call_luid = mem_last_set = DF_INSN_LUID (insn);
13602
13603       /* We can't combine into a call pattern.  Remember, though, that
13604          the return value register is set at this LUID.  We could
13605          still replace a register with the return value from the
13606          wrong subroutine call!  */
13607       note_stores (insn, record_dead_and_set_regs_1, NULL_RTX);
13608     }
13609   else
13610     note_stores (insn, record_dead_and_set_regs_1, insn);
13611 }
13612
13613 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13614    register present in the SUBREG, so for each such SUBREG go back and
13615    adjust nonzero and sign bit information of the registers that are
13616    known to have some zero/sign bits set.
13617
13618    This is needed because when combine blows the SUBREGs away, the
13619    information on zero/sign bits is lost and further combines can be
13620    missed because of that.  */
13621
13622 static void
13623 record_promoted_value (rtx_insn *insn, rtx subreg)
13624 {
13625   struct insn_link *links;
13626   rtx set;
13627   unsigned int regno = REGNO (SUBREG_REG (subreg));
13628   machine_mode mode = GET_MODE (subreg);
13629
13630   if (!HWI_COMPUTABLE_MODE_P (mode))
13631     return;
13632
13633   for (links = LOG_LINKS (insn); links;)
13634     {
13635       reg_stat_type *rsp;
13636
13637       insn = links->insn;
13638       set = single_set (insn);
13639
13640       if (! set || !REG_P (SET_DEST (set))
13641           || REGNO (SET_DEST (set)) != regno
13642           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
13643         {
13644           links = links->next;
13645           continue;
13646         }
13647
13648       rsp = &reg_stat[regno];
13649       if (rsp->last_set == insn)
13650         {
13651           if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
13652             rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
13653         }
13654
13655       if (REG_P (SET_SRC (set)))
13656         {
13657           regno = REGNO (SET_SRC (set));
13658           links = LOG_LINKS (insn);
13659         }
13660       else
13661         break;
13662     }
13663 }
13664
13665 /* Check if X, a register, is known to contain a value already
13666    truncated to MODE.  In this case we can use a subreg to refer to
13667    the truncated value even though in the generic case we would need
13668    an explicit truncation.  */
13669
13670 static bool
13671 reg_truncated_to_mode (machine_mode mode, const_rtx x)
13672 {
13673   reg_stat_type *rsp = &reg_stat[REGNO (x)];
13674   machine_mode truncated = rsp->truncated_to_mode;
13675
13676   if (truncated == 0
13677       || rsp->truncation_label < label_tick_ebb_start)
13678     return false;
13679   if (!partial_subreg_p (mode, truncated))
13680     return true;
13681   if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
13682     return true;
13683   return false;
13684 }
13685
13686 /* If X is a hard reg or a subreg record the mode that the register is
13687    accessed in.  For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13688    able to turn a truncate into a subreg using this information.  Return true
13689    if traversing X is complete.  */
13690
13691 static bool
13692 record_truncated_value (rtx x)
13693 {
13694   machine_mode truncated_mode;
13695   reg_stat_type *rsp;
13696
13697   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
13698     {
13699       machine_mode original_mode = GET_MODE (SUBREG_REG (x));
13700       truncated_mode = GET_MODE (x);
13701
13702       if (!partial_subreg_p (truncated_mode, original_mode))
13703         return true;
13704
13705       truncated_mode = GET_MODE (x);
13706       if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
13707         return true;
13708
13709       x = SUBREG_REG (x);
13710     }
13711   /* ??? For hard-regs we now record everything.  We might be able to
13712      optimize this using last_set_mode.  */
13713   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
13714     truncated_mode = GET_MODE (x);
13715   else
13716     return false;
13717
13718   rsp = &reg_stat[REGNO (x)];
13719   if (rsp->truncated_to_mode == 0
13720       || rsp->truncation_label < label_tick_ebb_start
13721       || partial_subreg_p (truncated_mode, rsp->truncated_to_mode))
13722     {
13723       rsp->truncated_to_mode = truncated_mode;
13724       rsp->truncation_label = label_tick;
13725     }
13726
13727   return true;
13728 }
13729
13730 /* Callback for note_uses.  Find hardregs and subregs of pseudos and
13731    the modes they are used in.  This can help truning TRUNCATEs into
13732    SUBREGs.  */
13733
13734 static void
13735 record_truncated_values (rtx *loc, void *data ATTRIBUTE_UNUSED)
13736 {
13737   subrtx_var_iterator::array_type array;
13738   FOR_EACH_SUBRTX_VAR (iter, array, *loc, NONCONST)
13739     if (record_truncated_value (*iter))
13740       iter.skip_subrtxes ();
13741 }
13742
13743 /* Scan X for promoted SUBREGs.  For each one found,
13744    note what it implies to the registers used in it.  */
13745
13746 static void
13747 check_promoted_subreg (rtx_insn *insn, rtx x)
13748 {
13749   if (GET_CODE (x) == SUBREG
13750       && SUBREG_PROMOTED_VAR_P (x)
13751       && REG_P (SUBREG_REG (x)))
13752     record_promoted_value (insn, x);
13753   else
13754     {
13755       const char *format = GET_RTX_FORMAT (GET_CODE (x));
13756       int i, j;
13757
13758       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
13759         switch (format[i])
13760           {
13761           case 'e':
13762             check_promoted_subreg (insn, XEXP (x, i));
13763             break;
13764           case 'V':
13765           case 'E':
13766             if (XVEC (x, i) != 0)
13767               for (j = 0; j < XVECLEN (x, i); j++)
13768                 check_promoted_subreg (insn, XVECEXP (x, i, j));
13769             break;
13770           }
13771     }
13772 }
13773 \f
13774 /* Verify that all the registers and memory references mentioned in *LOC are
13775    still valid.  *LOC was part of a value set in INSN when label_tick was
13776    equal to TICK.  Return false if some are not.  If REPLACE is true, replace
13777    the invalid references with (clobber (const_int 0)) and return true.  This
13778    replacement is useful because we often can get useful information about
13779    the form of a value (e.g., if it was produced by a shift that always
13780    produces -1 or 0) even though we don't know exactly what registers it
13781    was produced from.  */
13782
13783 static bool
13784 get_last_value_validate (rtx *loc, rtx_insn *insn, int tick, bool replace)
13785 {
13786   rtx x = *loc;
13787   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
13788   int len = GET_RTX_LENGTH (GET_CODE (x));
13789   int i, j;
13790
13791   if (REG_P (x))
13792     {
13793       unsigned int regno = REGNO (x);
13794       unsigned int endregno = END_REGNO (x);
13795       unsigned int j;
13796
13797       for (j = regno; j < endregno; j++)
13798         {
13799           reg_stat_type *rsp = &reg_stat[j];
13800           if (rsp->last_set_invalid
13801               /* If this is a pseudo-register that was only set once and not
13802                  live at the beginning of the function, it is always valid.  */
13803               || (! (regno >= FIRST_PSEUDO_REGISTER
13804                      && regno < reg_n_sets_max
13805                      && REG_N_SETS (regno) == 1
13806                      && (!REGNO_REG_SET_P
13807                          (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
13808                           regno)))
13809                   && rsp->last_set_label > tick))
13810           {
13811             if (replace)
13812               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
13813             return replace;
13814           }
13815         }
13816
13817       return true;
13818     }
13819   /* If this is a memory reference, make sure that there were no stores after
13820      it that might have clobbered the value.  We don't have alias info, so we
13821      assume any store invalidates it.  Moreover, we only have local UIDs, so
13822      we also assume that there were stores in the intervening basic blocks.  */
13823   else if (MEM_P (x) && !MEM_READONLY_P (x)
13824            && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
13825     {
13826       if (replace)
13827         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
13828       return replace;
13829     }
13830
13831   for (i = 0; i < len; i++)
13832     {
13833       if (fmt[i] == 'e')
13834         {
13835           /* Check for identical subexpressions.  If x contains
13836              identical subexpression we only have to traverse one of
13837              them.  */
13838           if (i == 1 && ARITHMETIC_P (x))
13839             {
13840               /* Note that at this point x0 has already been checked
13841                  and found valid.  */
13842               rtx x0 = XEXP (x, 0);
13843               rtx x1 = XEXP (x, 1);
13844
13845               /* If x0 and x1 are identical then x is also valid.  */
13846               if (x0 == x1)
13847                 return true;
13848
13849               /* If x1 is identical to a subexpression of x0 then
13850                  while checking x0, x1 has already been checked.  Thus
13851                  it is valid and so as x.  */
13852               if (ARITHMETIC_P (x0)
13853                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13854                 return true;
13855
13856               /* If x0 is identical to a subexpression of x1 then x is
13857                  valid iff the rest of x1 is valid.  */
13858               if (ARITHMETIC_P (x1)
13859                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13860                 return
13861                   get_last_value_validate (&XEXP (x1,
13862                                                   x0 == XEXP (x1, 0) ? 1 : 0),
13863                                            insn, tick, replace);
13864             }
13865
13866           if (!get_last_value_validate (&XEXP (x, i), insn, tick, replace))
13867             return false;
13868         }
13869       else if (fmt[i] == 'E')
13870         for (j = 0; j < XVECLEN (x, i); j++)
13871           if (!get_last_value_validate (&XVECEXP (x, i, j),
13872                                         insn, tick, replace))
13873             return false;
13874     }
13875
13876   /* If we haven't found a reason for it to be invalid, it is valid.  */
13877   return true;
13878 }
13879
13880 /* Get the last value assigned to X, if known.  Some registers
13881    in the value may be replaced with (clobber (const_int 0)) if their value
13882    is known longer known reliably.  */
13883
13884 static rtx
13885 get_last_value (const_rtx x)
13886 {
13887   unsigned int regno;
13888   rtx value;
13889   reg_stat_type *rsp;
13890
13891   /* If this is a non-paradoxical SUBREG, get the value of its operand and
13892      then convert it to the desired mode.  If this is a paradoxical SUBREG,
13893      we cannot predict what values the "extra" bits might have.  */
13894   if (GET_CODE (x) == SUBREG
13895       && subreg_lowpart_p (x)
13896       && !paradoxical_subreg_p (x)
13897       && (value = get_last_value (SUBREG_REG (x))) != 0)
13898     return gen_lowpart (GET_MODE (x), value);
13899
13900   if (!REG_P (x))
13901     return 0;
13902
13903   regno = REGNO (x);
13904   rsp = &reg_stat[regno];
13905   value = rsp->last_set_value;
13906
13907   /* If we don't have a value, or if it isn't for this basic block and
13908      it's either a hard register, set more than once, or it's a live
13909      at the beginning of the function, return 0.
13910
13911      Because if it's not live at the beginning of the function then the reg
13912      is always set before being used (is never used without being set).
13913      And, if it's set only once, and it's always set before use, then all
13914      uses must have the same last value, even if it's not from this basic
13915      block.  */
13916
13917   if (value == 0
13918       || (rsp->last_set_label < label_tick_ebb_start
13919           && (regno < FIRST_PSEUDO_REGISTER
13920               || regno >= reg_n_sets_max
13921               || REG_N_SETS (regno) != 1
13922               || REGNO_REG_SET_P
13923                  (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), regno))))
13924     return 0;
13925
13926   /* If the value was set in a later insn than the ones we are processing,
13927      we can't use it even if the register was only set once.  */
13928   if (rsp->last_set_label == label_tick
13929       && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
13930     return 0;
13931
13932   /* If fewer bits were set than what we are asked for now, we cannot use
13933      the value.  */
13934   if (maybe_lt (GET_MODE_PRECISION (rsp->last_set_mode),
13935                 GET_MODE_PRECISION (GET_MODE (x))))
13936     return 0;
13937
13938   /* If the value has all its registers valid, return it.  */
13939   if (get_last_value_validate (&value, rsp->last_set,
13940                                rsp->last_set_label, false))
13941     return value;
13942
13943   /* Otherwise, make a copy and replace any invalid register with
13944      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
13945
13946   value = copy_rtx (value);
13947   if (get_last_value_validate (&value, rsp->last_set,
13948                                rsp->last_set_label, true))
13949     return value;
13950
13951   return 0;
13952 }
13953 \f
13954 /* Define three variables used for communication between the following
13955    routines.  */
13956
13957 static unsigned int reg_dead_regno, reg_dead_endregno;
13958 static int reg_dead_flag;
13959 rtx reg_dead_reg;
13960
13961 /* Function called via note_stores from reg_dead_at_p.
13962
13963    If DEST is within [reg_dead_regno, reg_dead_endregno), set
13964    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
13965
13966 static void
13967 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
13968 {
13969   unsigned int regno, endregno;
13970
13971   if (!REG_P (dest))
13972     return;
13973
13974   regno = REGNO (dest);
13975   endregno = END_REGNO (dest);
13976   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
13977     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
13978 }
13979
13980 /* Return true if REG is known to be dead at INSN.
13981
13982    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
13983    referencing REG, it is dead.  If we hit a SET referencing REG, it is
13984    live.  Otherwise, see if it is live or dead at the start of the basic
13985    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
13986    must be assumed to be always live.  */
13987
13988 static bool
13989 reg_dead_at_p (rtx reg, rtx_insn *insn)
13990 {
13991   basic_block block;
13992   unsigned int i;
13993
13994   /* Set variables for reg_dead_at_p_1.  */
13995   reg_dead_regno = REGNO (reg);
13996   reg_dead_endregno = END_REGNO (reg);
13997   reg_dead_reg = reg;
13998
13999   reg_dead_flag = 0;
14000
14001   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
14002      we allow the machine description to decide whether use-and-clobber
14003      patterns are OK.  */
14004   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
14005     {
14006       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
14007         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
14008           return false;
14009     }
14010
14011   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
14012      beginning of basic block.  */
14013   block = BLOCK_FOR_INSN (insn);
14014   for (;;)
14015     {
14016       if (INSN_P (insn))
14017         {
14018           if (find_regno_note (insn, REG_UNUSED, reg_dead_regno))
14019             return true;
14020
14021           note_stores (insn, reg_dead_at_p_1, NULL);
14022           if (reg_dead_flag)
14023             return reg_dead_flag == 1 ? 1 : 0;
14024
14025           if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
14026             return true;
14027         }
14028
14029       if (insn == BB_HEAD (block))
14030         break;
14031
14032       insn = PREV_INSN (insn);
14033     }
14034
14035   /* Look at live-in sets for the basic block that we were in.  */
14036   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
14037     if (REGNO_REG_SET_P (df_get_live_in (block), i))
14038       return false;
14039
14040   return true;
14041 }
14042 \f
14043 /* Note hard registers in X that are used.  */
14044
14045 static void
14046 mark_used_regs_combine (rtx x)
14047 {
14048   RTX_CODE code = GET_CODE (x);
14049   unsigned int regno;
14050   int i;
14051
14052   switch (code)
14053     {
14054     case LABEL_REF:
14055     case SYMBOL_REF:
14056     case CONST:
14057     CASE_CONST_ANY:
14058     case PC:
14059     case ADDR_VEC:
14060     case ADDR_DIFF_VEC:
14061     case ASM_INPUT:
14062       return;
14063
14064     case CLOBBER:
14065       /* If we are clobbering a MEM, mark any hard registers inside the
14066          address as used.  */
14067       if (MEM_P (XEXP (x, 0)))
14068         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
14069       return;
14070
14071     case REG:
14072       regno = REGNO (x);
14073       /* A hard reg in a wide mode may really be multiple registers.
14074          If so, mark all of them just like the first.  */
14075       if (regno < FIRST_PSEUDO_REGISTER)
14076         {
14077           /* None of this applies to the stack, frame or arg pointers.  */
14078           if (regno == STACK_POINTER_REGNUM
14079               || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
14080                   && regno == HARD_FRAME_POINTER_REGNUM)
14081               || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
14082                   && regno == ARG_POINTER_REGNUM && fixed_regs[regno])
14083               || regno == FRAME_POINTER_REGNUM)
14084             return;
14085
14086           add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
14087         }
14088       return;
14089
14090     case SET:
14091       {
14092         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
14093            the address.  */
14094         rtx testreg = SET_DEST (x);
14095
14096         while (GET_CODE (testreg) == SUBREG
14097                || GET_CODE (testreg) == ZERO_EXTRACT
14098                || GET_CODE (testreg) == STRICT_LOW_PART)
14099           testreg = XEXP (testreg, 0);
14100
14101         if (MEM_P (testreg))
14102           mark_used_regs_combine (XEXP (testreg, 0));
14103
14104         mark_used_regs_combine (SET_SRC (x));
14105       }
14106       return;
14107
14108     default:
14109       break;
14110     }
14111
14112   /* Recursively scan the operands of this expression.  */
14113
14114   {
14115     const char *fmt = GET_RTX_FORMAT (code);
14116
14117     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
14118       {
14119         if (fmt[i] == 'e')
14120           mark_used_regs_combine (XEXP (x, i));
14121         else if (fmt[i] == 'E')
14122           {
14123             int j;
14124
14125             for (j = 0; j < XVECLEN (x, i); j++)
14126               mark_used_regs_combine (XVECEXP (x, i, j));
14127           }
14128       }
14129   }
14130 }
14131 \f
14132 /* Remove register number REGNO from the dead registers list of INSN.
14133
14134    Return the note used to record the death, if there was one.  */
14135
14136 rtx
14137 remove_death (unsigned int regno, rtx_insn *insn)
14138 {
14139   rtx note = find_regno_note (insn, REG_DEAD, regno);
14140
14141   if (note)
14142     remove_note (insn, note);
14143
14144   return note;
14145 }
14146
14147 /* For each register (hardware or pseudo) used within expression X, if its
14148    death is in an instruction with luid between FROM_LUID (inclusive) and
14149    TO_INSN (exclusive), put a REG_DEAD note for that register in the
14150    list headed by PNOTES.
14151
14152    That said, don't move registers killed by maybe_kill_insn.
14153
14154    This is done when X is being merged by combination into TO_INSN.  These
14155    notes will then be distributed as needed.  */
14156
14157 static void
14158 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn,
14159              rtx *pnotes)
14160 {
14161   const char *fmt;
14162   int len, i;
14163   enum rtx_code code = GET_CODE (x);
14164
14165   if (code == REG)
14166     {
14167       unsigned int regno = REGNO (x);
14168       rtx_insn *where_dead = reg_stat[regno].last_death;
14169
14170       /* If we do not know where the register died, it may still die between
14171          FROM_LUID and TO_INSN.  If so, find it.  This is PR83304.  */
14172       if (!where_dead || DF_INSN_LUID (where_dead) >= DF_INSN_LUID (to_insn))
14173         {
14174           rtx_insn *insn = prev_real_nondebug_insn (to_insn);
14175           while (insn
14176                  && BLOCK_FOR_INSN (insn) == BLOCK_FOR_INSN (to_insn)
14177                  && DF_INSN_LUID (insn) >= from_luid)
14178             {
14179               if (dead_or_set_regno_p (insn, regno))
14180                 {
14181                   if (find_regno_note (insn, REG_DEAD, regno))
14182                     where_dead = insn;
14183                   break;
14184                 }
14185
14186               insn = prev_real_nondebug_insn (insn);
14187             }
14188         }
14189
14190       /* Don't move the register if it gets killed in between from and to.  */
14191       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
14192           && ! reg_referenced_p (x, maybe_kill_insn))
14193         return;
14194
14195       if (where_dead
14196           && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
14197           && DF_INSN_LUID (where_dead) >= from_luid
14198           && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
14199         {
14200           rtx note = remove_death (regno, where_dead);
14201
14202           /* It is possible for the call above to return 0.  This can occur
14203              when last_death points to I2 or I1 that we combined with.
14204              In that case make a new note.
14205
14206              We must also check for the case where X is a hard register
14207              and NOTE is a death note for a range of hard registers
14208              including X.  In that case, we must put REG_DEAD notes for
14209              the remaining registers in place of NOTE.  */
14210
14211           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
14212               && partial_subreg_p (GET_MODE (x), GET_MODE (XEXP (note, 0))))
14213             {
14214               unsigned int deadregno = REGNO (XEXP (note, 0));
14215               unsigned int deadend = END_REGNO (XEXP (note, 0));
14216               unsigned int ourend = END_REGNO (x);
14217               unsigned int i;
14218
14219               for (i = deadregno; i < deadend; i++)
14220                 if (i < regno || i >= ourend)
14221                   add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
14222             }
14223
14224           /* If we didn't find any note, or if we found a REG_DEAD note that
14225              covers only part of the given reg, and we have a multi-reg hard
14226              register, then to be safe we must check for REG_DEAD notes
14227              for each register other than the first.  They could have
14228              their own REG_DEAD notes lying around.  */
14229           else if ((note == 0
14230                     || (note != 0
14231                         && partial_subreg_p (GET_MODE (XEXP (note, 0)),
14232                                              GET_MODE (x))))
14233                    && regno < FIRST_PSEUDO_REGISTER
14234                    && REG_NREGS (x) > 1)
14235             {
14236               unsigned int ourend = END_REGNO (x);
14237               unsigned int i, offset;
14238               rtx oldnotes = 0;
14239
14240               if (note)
14241                 offset = hard_regno_nregs (regno, GET_MODE (XEXP (note, 0)));
14242               else
14243                 offset = 1;
14244
14245               for (i = regno + offset; i < ourend; i++)
14246                 move_deaths (regno_reg_rtx[i],
14247                              maybe_kill_insn, from_luid, to_insn, &oldnotes);
14248             }
14249
14250           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
14251             {
14252               XEXP (note, 1) = *pnotes;
14253               *pnotes = note;
14254             }
14255           else
14256             *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
14257         }
14258
14259       return;
14260     }
14261
14262   else if (GET_CODE (x) == SET)
14263     {
14264       rtx dest = SET_DEST (x);
14265
14266       move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
14267
14268       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
14269          that accesses one word of a multi-word item, some
14270          piece of everything register in the expression is used by
14271          this insn, so remove any old death.  */
14272       /* ??? So why do we test for equality of the sizes?  */
14273
14274       if (GET_CODE (dest) == ZERO_EXTRACT
14275           || GET_CODE (dest) == STRICT_LOW_PART
14276           || (GET_CODE (dest) == SUBREG
14277               && !read_modify_subreg_p (dest)))
14278         {
14279           move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
14280           return;
14281         }
14282
14283       /* If this is some other SUBREG, we know it replaces the entire
14284          value, so use that as the destination.  */
14285       if (GET_CODE (dest) == SUBREG)
14286         dest = SUBREG_REG (dest);
14287
14288       /* If this is a MEM, adjust deaths of anything used in the address.
14289          For a REG (the only other possibility), the entire value is
14290          being replaced so the old value is not used in this insn.  */
14291
14292       if (MEM_P (dest))
14293         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
14294                      to_insn, pnotes);
14295       return;
14296     }
14297
14298   else if (GET_CODE (x) == CLOBBER)
14299     return;
14300
14301   len = GET_RTX_LENGTH (code);
14302   fmt = GET_RTX_FORMAT (code);
14303
14304   for (i = 0; i < len; i++)
14305     {
14306       if (fmt[i] == 'E')
14307         {
14308           int j;
14309           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
14310             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
14311                          to_insn, pnotes);
14312         }
14313       else if (fmt[i] == 'e')
14314         move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
14315     }
14316 }
14317 \f
14318 /* Return true if X is the target of a bit-field assignment in BODY, the
14319    pattern of an insn.  X must be a REG.  */
14320
14321 static bool
14322 reg_bitfield_target_p (rtx x, rtx body)
14323 {
14324   int i;
14325
14326   if (GET_CODE (body) == SET)
14327     {
14328       rtx dest = SET_DEST (body);
14329       rtx target;
14330       unsigned int regno, tregno, endregno, endtregno;
14331
14332       if (GET_CODE (dest) == ZERO_EXTRACT)
14333         target = XEXP (dest, 0);
14334       else if (GET_CODE (dest) == STRICT_LOW_PART)
14335         target = SUBREG_REG (XEXP (dest, 0));
14336       else
14337         return false;
14338
14339       if (GET_CODE (target) == SUBREG)
14340         target = SUBREG_REG (target);
14341
14342       if (!REG_P (target))
14343         return false;
14344
14345       tregno = REGNO (target), regno = REGNO (x);
14346       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
14347         return target == x;
14348
14349       endtregno = end_hard_regno (GET_MODE (target), tregno);
14350       endregno = end_hard_regno (GET_MODE (x), regno);
14351
14352       return endregno > tregno && regno < endtregno;
14353     }
14354
14355   else if (GET_CODE (body) == PARALLEL)
14356     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
14357       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
14358         return true;
14359
14360   return false;
14361 }
14362 \f
14363 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14364    as appropriate.  I3 and I2 are the insns resulting from the combination
14365    insns including FROM (I2 may be zero).
14366
14367    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14368    not need REG_DEAD notes because they are being substituted for.  This
14369    saves searching in the most common cases.
14370
14371    Each note in the list is either ignored or placed on some insns, depending
14372    on the type of note.  */
14373
14374 static void
14375 distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2,
14376                   rtx elim_i2, rtx elim_i1, rtx elim_i0)
14377 {
14378   rtx note, next_note;
14379   rtx tem_note;
14380   rtx_insn *tem_insn;
14381
14382   for (note = notes; note; note = next_note)
14383     {
14384       rtx_insn *place = 0, *place2 = 0;
14385
14386       next_note = XEXP (note, 1);
14387       switch (REG_NOTE_KIND (note))
14388         {
14389         case REG_BR_PROB:
14390         case REG_BR_PRED:
14391           /* Doesn't matter much where we put this, as long as it's somewhere.
14392              It is preferable to keep these notes on branches, which is most
14393              likely to be i3.  */
14394           place = i3;
14395           break;
14396
14397         case REG_NON_LOCAL_GOTO:
14398           if (JUMP_P (i3))
14399             place = i3;
14400           else
14401             {
14402               gcc_assert (i2 && JUMP_P (i2));
14403               place = i2;
14404             }
14405           break;
14406
14407         case REG_EH_REGION:
14408           {
14409             /* The landing pad handling needs to be kept in sync with the
14410                prerequisite checking in try_combine.  */
14411             int lp_nr = INTVAL (XEXP (note, 0));
14412             /* A REG_EH_REGION note transfering control can only ever come
14413                from i3.  */
14414             if (lp_nr > 0)
14415               gcc_assert (from_insn == i3);
14416             /* We are making sure there is a single effective REG_EH_REGION
14417                note and it's valid to put it on i3.  */
14418             if (!insn_could_throw_p (from_insn)
14419                 && !(lp_nr == INT_MIN && can_nonlocal_goto (from_insn)))
14420               /* Throw away stray notes on insns that can never throw or
14421                  make a nonlocal goto.  */
14422               ;
14423             else
14424               {
14425                 if (CALL_P (i3))
14426                   place = i3;
14427                 else
14428                   {
14429                     gcc_assert (cfun->can_throw_non_call_exceptions);
14430                     /* If i3 can still trap preserve the note, otherwise we've
14431                        combined things such that we can now prove that the
14432                        instructions can't trap.  Drop the note in this case.  */
14433                     if (may_trap_p (i3))
14434                       place = i3;
14435                   }
14436               }
14437             break;
14438           }
14439
14440         case REG_ARGS_SIZE:
14441           /* ??? How to distribute between i3-i1.  Assume i3 contains the
14442              entire adjustment.  Assert i3 contains at least some adjust.  */
14443           if (!noop_move_p (i3))
14444             {
14445               poly_int64 old_size, args_size = get_args_size (note);
14446               /* fixup_args_size_notes looks at REG_NORETURN note,
14447                  so ensure the note is placed there first.  */
14448               if (CALL_P (i3))
14449                 {
14450                   rtx *np;
14451                   for (np = &next_note; *np; np = &XEXP (*np, 1))
14452                     if (REG_NOTE_KIND (*np) == REG_NORETURN)
14453                       {
14454                         rtx n = *np;
14455                         *np = XEXP (n, 1);
14456                         XEXP (n, 1) = REG_NOTES (i3);
14457                         REG_NOTES (i3) = n;
14458                         break;
14459                       }
14460                 }
14461               old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
14462               /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14463                  REG_ARGS_SIZE note to all noreturn calls, allow that here.  */
14464               gcc_assert (maybe_ne (old_size, args_size)
14465                           || (CALL_P (i3)
14466                               && !ACCUMULATE_OUTGOING_ARGS
14467                               && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
14468             }
14469           break;
14470
14471         case REG_NORETURN:
14472         case REG_SETJMP:
14473         case REG_TM:
14474         case REG_CALL_DECL:
14475         case REG_UNTYPED_CALL:
14476         case REG_CALL_NOCF_CHECK:
14477           /* These notes must remain with the call.  It should not be
14478              possible for both I2 and I3 to be a call.  */
14479           if (CALL_P (i3))
14480             place = i3;
14481           else
14482             {
14483               gcc_assert (i2 && CALL_P (i2));
14484               place = i2;
14485             }
14486           break;
14487
14488         case REG_UNUSED:
14489           /* Any clobbers for i3 may still exist, and so we must process
14490              REG_UNUSED notes from that insn.
14491
14492              Any clobbers from i2 or i1 can only exist if they were added by
14493              recog_for_combine.  In that case, recog_for_combine created the
14494              necessary REG_UNUSED notes.  Trying to keep any original
14495              REG_UNUSED notes from these insns can cause incorrect output
14496              if it is for the same register as the original i3 dest.
14497              In that case, we will notice that the register is set in i3,
14498              and then add a REG_UNUSED note for the destination of i3, which
14499              is wrong.  However, it is possible to have REG_UNUSED notes from
14500              i2 or i1 for register which were both used and clobbered, so
14501              we keep notes from i2 or i1 if they will turn into REG_DEAD
14502              notes.  */
14503
14504           /* If this register is set or clobbered between FROM_INSN and I3,
14505              we should not create a note for it.  */
14506           if (reg_set_between_p (XEXP (note, 0), from_insn, i3))
14507             break;
14508
14509           /* If this register is set or clobbered in I3, put the note there
14510              unless there is one already.  */
14511           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
14512             {
14513               if (from_insn != i3)
14514                 break;
14515
14516               if (! (REG_P (XEXP (note, 0))
14517                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
14518                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
14519                 place = i3;
14520             }
14521           /* Otherwise, if this register is used by I3, then this register
14522              now dies here, so we must put a REG_DEAD note here unless there
14523              is one already.  */
14524           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
14525                    && ! (REG_P (XEXP (note, 0))
14526                          ? find_regno_note (i3, REG_DEAD,
14527                                             REGNO (XEXP (note, 0)))
14528                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
14529             {
14530               PUT_REG_NOTE_KIND (note, REG_DEAD);
14531               place = i3;
14532             }
14533
14534           /* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14535              but we can't tell which at this point.  We must reset any
14536              expectations we had about the value that was previously
14537              stored in the reg.  ??? Ideally, we'd adjust REG_N_SETS
14538              and, if appropriate, restore its previous value, but we
14539              don't have enough information for that at this point.  */
14540           else
14541             {
14542               record_value_for_reg (XEXP (note, 0), NULL, NULL_RTX);
14543
14544               /* Otherwise, if this register is now referenced in i2
14545                  then the register used to be modified in one of the
14546                  original insns.  If it was i3 (say, in an unused
14547                  parallel), it's now completely gone, so the note can
14548                  be discarded.  But if it was modified in i2, i1 or i0
14549                  and we still reference it in i2, then we're
14550                  referencing the previous value, and since the
14551                  register was modified and REG_UNUSED, we know that
14552                  the previous value is now dead.  So, if we only
14553                  reference the register in i2, we change the note to
14554                  REG_DEAD, to reflect the previous value.  However, if
14555                  we're also setting or clobbering the register as
14556                  scratch, we know (because the register was not
14557                  referenced in i3) that it's unused, just as it was
14558                  unused before, and we place the note in i2.  */
14559               if (from_insn != i3 && i2 && INSN_P (i2)
14560                   && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
14561                 {
14562                   if (!reg_set_p (XEXP (note, 0), PATTERN (i2)))
14563                     PUT_REG_NOTE_KIND (note, REG_DEAD);
14564                   if (! (REG_P (XEXP (note, 0))
14565                          ? find_regno_note (i2, REG_NOTE_KIND (note),
14566                                             REGNO (XEXP (note, 0)))
14567                          : find_reg_note (i2, REG_NOTE_KIND (note),
14568                                           XEXP (note, 0))))
14569                     place = i2;
14570                 }
14571             }
14572
14573           break;
14574
14575         case REG_EQUAL:
14576         case REG_EQUIV:
14577         case REG_NOALIAS:
14578           /* These notes say something about results of an insn.  We can
14579              only support them if they used to be on I3 in which case they
14580              remain on I3.  Otherwise they are ignored.
14581
14582              If the note refers to an expression that is not a constant, we
14583              must also ignore the note since we cannot tell whether the
14584              equivalence is still true.  It might be possible to do
14585              slightly better than this (we only have a problem if I2DEST
14586              or I1DEST is present in the expression), but it doesn't
14587              seem worth the trouble.  */
14588
14589           if (from_insn == i3
14590               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
14591             place = i3;
14592           break;
14593
14594         case REG_INC:
14595           /* These notes say something about how a register is used.  They must
14596              be present on any use of the register in I2 or I3.  */
14597           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
14598             place = i3;
14599
14600           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
14601             {
14602               if (place)
14603                 place2 = i2;
14604               else
14605                 place = i2;
14606             }
14607           break;
14608
14609         case REG_LABEL_TARGET:
14610         case REG_LABEL_OPERAND:
14611           /* This can show up in several ways -- either directly in the
14612              pattern, or hidden off in the constant pool with (or without?)
14613              a REG_EQUAL note.  */
14614           /* ??? Ignore the without-reg_equal-note problem for now.  */
14615           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
14616               || ((tem_note = find_reg_note (i3, REG_EQUAL, NULL_RTX))
14617                   && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
14618                   && label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0)))
14619             place = i3;
14620
14621           if (i2
14622               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
14623                   || ((tem_note = find_reg_note (i2, REG_EQUAL, NULL_RTX))
14624                       && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
14625                       && label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0))))
14626             {
14627               if (place)
14628                 place2 = i2;
14629               else
14630                 place = i2;
14631             }
14632
14633           /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14634              as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14635              there.  */
14636           if (place && JUMP_P (place)
14637               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
14638               && (JUMP_LABEL (place) == NULL
14639                   || JUMP_LABEL (place) == XEXP (note, 0)))
14640             {
14641               rtx label = JUMP_LABEL (place);
14642
14643               if (!label)
14644                 JUMP_LABEL (place) = XEXP (note, 0);
14645               else if (LABEL_P (label))
14646                 LABEL_NUSES (label)--;
14647             }
14648
14649           if (place2 && JUMP_P (place2)
14650               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
14651               && (JUMP_LABEL (place2) == NULL
14652                   || JUMP_LABEL (place2) == XEXP (note, 0)))
14653             {
14654               rtx label = JUMP_LABEL (place2);
14655
14656               if (!label)
14657                 JUMP_LABEL (place2) = XEXP (note, 0);
14658               else if (LABEL_P (label))
14659                 LABEL_NUSES (label)--;
14660               place2 = 0;
14661             }
14662           break;
14663
14664         case REG_NONNEG:
14665           /* This note says something about the value of a register prior
14666              to the execution of an insn.  It is too much trouble to see
14667              if the note is still correct in all situations.  It is better
14668              to simply delete it.  */
14669           break;
14670
14671         case REG_DEAD:
14672           /* If we replaced the right hand side of FROM_INSN with a
14673              REG_EQUAL note, the original use of the dying register
14674              will not have been combined into I3 and I2.  In such cases,
14675              FROM_INSN is guaranteed to be the first of the combined
14676              instructions, so we simply need to search back before
14677              FROM_INSN for the previous use or set of this register,
14678              then alter the notes there appropriately.
14679
14680              If the register is used as an input in I3, it dies there.
14681              Similarly for I2, if it is nonzero and adjacent to I3.
14682
14683              If the register is not used as an input in either I3 or I2
14684              and it is not one of the registers we were supposed to eliminate,
14685              there are two possibilities.  We might have a non-adjacent I2
14686              or we might have somehow eliminated an additional register
14687              from a computation.  For example, we might have had A & B where
14688              we discover that B will always be zero.  In this case we will
14689              eliminate the reference to A.
14690
14691              In both cases, we must search to see if we can find a previous
14692              use of A and put the death note there.  */
14693
14694           if (from_insn
14695               && from_insn == i2mod
14696               && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
14697             tem_insn = from_insn;
14698           else
14699             {
14700               if (from_insn
14701                   && CALL_P (from_insn)
14702                   && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
14703                 place = from_insn;
14704               else if (i2 && reg_set_p (XEXP (note, 0), PATTERN (i2)))
14705                 {
14706                   /* If the new I2 sets the same register that is marked
14707                      dead in the note, we do not in general know where to
14708                      put the note.  One important case we _can_ handle is
14709                      when the note comes from I3.  */
14710                   if (from_insn == i3)
14711                     place = i3;
14712                   else
14713                     break;
14714                 }
14715               else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
14716                 place = i3;
14717               else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
14718                        && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
14719                 place = i2;
14720               else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
14721                         && !(i2mod
14722                              && reg_overlap_mentioned_p (XEXP (note, 0),
14723                                                          i2mod_old_rhs)))
14724                        || rtx_equal_p (XEXP (note, 0), elim_i1)
14725                        || rtx_equal_p (XEXP (note, 0), elim_i0))
14726                 break;
14727               tem_insn = i3;
14728             }
14729
14730           if (place == 0)
14731             {
14732               basic_block bb = this_basic_block;
14733
14734               for (tem_insn = PREV_INSN (tem_insn); place == 0; tem_insn = PREV_INSN (tem_insn))
14735                 {
14736                   if (!NONDEBUG_INSN_P (tem_insn))
14737                     {
14738                       if (tem_insn == BB_HEAD (bb))
14739                         break;
14740                       continue;
14741                     }
14742
14743                   /* If the register is being set at TEM_INSN, see if that is all
14744                      TEM_INSN is doing.  If so, delete TEM_INSN.  Otherwise, make this
14745                      into a REG_UNUSED note instead. Don't delete sets to
14746                      global register vars.  */
14747                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
14748                        || !global_regs[REGNO (XEXP (note, 0))])
14749                       && reg_set_p (XEXP (note, 0), PATTERN (tem_insn)))
14750                     {
14751                       rtx set = single_set (tem_insn);
14752                       rtx inner_dest = 0;
14753
14754                       if (set != 0)
14755                         for (inner_dest = SET_DEST (set);
14756                              (GET_CODE (inner_dest) == STRICT_LOW_PART
14757                               || GET_CODE (inner_dest) == SUBREG
14758                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
14759                              inner_dest = XEXP (inner_dest, 0))
14760                           ;
14761
14762                       /* Verify that it was the set, and not a clobber that
14763                          modified the register.
14764
14765                          If we cannot delete the setter due to side
14766                          effects, mark the user with an UNUSED note instead
14767                          of deleting it.  */
14768
14769                       if (set != 0 && ! side_effects_p (SET_SRC (set))
14770                           && rtx_equal_p (XEXP (note, 0), inner_dest))
14771                         {
14772                           /* Move the notes and links of TEM_INSN elsewhere.
14773                              This might delete other dead insns recursively.
14774                              First set the pattern to something that won't use
14775                              any register.  */
14776                           rtx old_notes = REG_NOTES (tem_insn);
14777
14778                           PATTERN (tem_insn) = pc_rtx;
14779                           REG_NOTES (tem_insn) = NULL;
14780
14781                           distribute_notes (old_notes, tem_insn, tem_insn, NULL,
14782                                             NULL_RTX, NULL_RTX, NULL_RTX);
14783                           distribute_links (LOG_LINKS (tem_insn));
14784
14785                           unsigned int regno = REGNO (XEXP (note, 0));
14786                           reg_stat_type *rsp = &reg_stat[regno];
14787                           if (rsp->last_set == tem_insn)
14788                             record_value_for_reg (XEXP (note, 0), NULL, NULL_RTX);
14789
14790                           SET_INSN_DELETED (tem_insn);
14791                           if (tem_insn == i2)
14792                             i2 = NULL;
14793                         }
14794                       else
14795                         {
14796                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
14797
14798                           /*  If there isn't already a REG_UNUSED note, put one
14799                               here.  Do not place a REG_DEAD note, even if
14800                               the register is also used here; that would not
14801                               match the algorithm used in lifetime analysis
14802                               and can cause the consistency check in the
14803                               scheduler to fail.  */
14804                           if (! find_regno_note (tem_insn, REG_UNUSED,
14805                                                  REGNO (XEXP (note, 0))))
14806                             place = tem_insn;
14807                           break;
14808                         }
14809                     }
14810                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem_insn))
14811                            || (CALL_P (tem_insn)
14812                                && find_reg_fusage (tem_insn, USE, XEXP (note, 0))))
14813                     {
14814                       place = tem_insn;
14815
14816                       /* If we are doing a 3->2 combination, and we have a
14817                          register which formerly died in i3 and was not used
14818                          by i2, which now no longer dies in i3 and is used in
14819                          i2 but does not die in i2, and place is between i2
14820                          and i3, then we may need to move a link from place to
14821                          i2.  */
14822                       if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
14823                           && from_insn
14824                           && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
14825                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
14826                         {
14827                           struct insn_link *links = LOG_LINKS (place);
14828                           LOG_LINKS (place) = NULL;
14829                           distribute_links (links);
14830                         }
14831                       break;
14832                     }
14833
14834                   if (tem_insn == BB_HEAD (bb))
14835                     break;
14836                 }
14837
14838             }
14839
14840           /* If the register is set or already dead at PLACE, we needn't do
14841              anything with this note if it is still a REG_DEAD note.
14842              We check here if it is set at all, not if is it totally replaced,
14843              which is what `dead_or_set_p' checks, so also check for it being
14844              set partially.  */
14845
14846           if (place && REG_NOTE_KIND (note) == REG_DEAD)
14847             {
14848               unsigned int regno = REGNO (XEXP (note, 0));
14849               reg_stat_type *rsp = &reg_stat[regno];
14850
14851               if (dead_or_set_p (place, XEXP (note, 0))
14852                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
14853                 {
14854                   /* Unless the register previously died in PLACE, clear
14855                      last_death.  [I no longer understand why this is
14856                      being done.] */
14857                   if (rsp->last_death != place)
14858                     rsp->last_death = 0;
14859                   place = 0;
14860                 }
14861               else
14862                 rsp->last_death = place;
14863
14864               /* If this is a death note for a hard reg that is occupying
14865                  multiple registers, ensure that we are still using all
14866                  parts of the object.  If we find a piece of the object
14867                  that is unused, we must arrange for an appropriate REG_DEAD
14868                  note to be added for it.  However, we can't just emit a USE
14869                  and tag the note to it, since the register might actually
14870                  be dead; so we recourse, and the recursive call then finds
14871                  the previous insn that used this register.  */
14872
14873               if (place && REG_NREGS (XEXP (note, 0)) > 1)
14874                 {
14875                   unsigned int endregno = END_REGNO (XEXP (note, 0));
14876                   bool all_used = true;
14877                   unsigned int i;
14878
14879                   for (i = regno; i < endregno; i++)
14880                     if ((! refers_to_regno_p (i, PATTERN (place))
14881                          && ! find_regno_fusage (place, USE, i))
14882                         || dead_or_set_regno_p (place, i))
14883                       {
14884                         all_used = false;
14885                         break;
14886                       }
14887
14888                   if (! all_used)
14889                     {
14890                       /* Put only REG_DEAD notes for pieces that are
14891                          not already dead or set.  */
14892
14893                       for (i = regno; i < endregno;
14894                            i += hard_regno_nregs (i, reg_raw_mode[i]))
14895                         {
14896                           rtx piece = regno_reg_rtx[i];
14897                           basic_block bb = this_basic_block;
14898
14899                           if (! dead_or_set_p (place, piece)
14900                               && ! reg_bitfield_target_p (piece,
14901                                                           PATTERN (place)))
14902                             {
14903                               rtx new_note = alloc_reg_note (REG_DEAD, piece,
14904                                                              NULL_RTX);
14905
14906                               distribute_notes (new_note, place, place,
14907                                                 NULL, NULL_RTX, NULL_RTX,
14908                                                 NULL_RTX);
14909                             }
14910                           else if (! refers_to_regno_p (i, PATTERN (place))
14911                                    && ! find_regno_fusage (place, USE, i))
14912                             for (tem_insn = PREV_INSN (place); ;
14913                                  tem_insn = PREV_INSN (tem_insn))
14914                               {
14915                                 if (!NONDEBUG_INSN_P (tem_insn))
14916                                   {
14917                                     if (tem_insn == BB_HEAD (bb))
14918                                       break;
14919                                     continue;
14920                                   }
14921                                 if (dead_or_set_p (tem_insn, piece)
14922                                     || reg_bitfield_target_p (piece,
14923                                                               PATTERN (tem_insn)))
14924                                   {
14925                                     add_reg_note (tem_insn, REG_UNUSED, piece);
14926                                     break;
14927                                   }
14928                               }
14929                         }
14930
14931                       place = 0;
14932                     }
14933                 }
14934             }
14935           break;
14936
14937         default:
14938           /* Any other notes should not be present at this point in the
14939              compilation.  */
14940           gcc_unreachable ();
14941         }
14942
14943       if (place)
14944         {
14945           XEXP (note, 1) = REG_NOTES (place);
14946           REG_NOTES (place) = note;
14947
14948           /* Set added_notes_insn to the earliest insn we added a note to.  */
14949           if (added_notes_insn == 0
14950               || DF_INSN_LUID (added_notes_insn) > DF_INSN_LUID (place))
14951             added_notes_insn = place;
14952         }
14953
14954       if (place2)
14955         {
14956           add_shallow_copy_of_reg_note (place2, note);
14957
14958           /* Set added_notes_insn to the earliest insn we added a note to.  */
14959           if (added_notes_insn == 0
14960               || DF_INSN_LUID (added_notes_insn) > DF_INSN_LUID (place2))
14961             added_notes_insn = place2;
14962         }
14963     }
14964 }
14965 \f
14966 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14967    I3, I2, and I1 to new locations.  This is also called to add a link
14968    pointing at I3 when I3's destination is changed.  */
14969
14970 static void
14971 distribute_links (struct insn_link *links)
14972 {
14973   struct insn_link *link, *next_link;
14974
14975   for (link = links; link; link = next_link)
14976     {
14977       rtx_insn *place = 0;
14978       rtx_insn *insn;
14979       rtx set, reg;
14980
14981       next_link = link->next;
14982
14983       /* If the insn that this link points to is a NOTE, ignore it.  */
14984       if (NOTE_P (link->insn))
14985         continue;
14986
14987       set = 0;
14988       rtx pat = PATTERN (link->insn);
14989       if (GET_CODE (pat) == SET)
14990         set = pat;
14991       else if (GET_CODE (pat) == PARALLEL)
14992         {
14993           int i;
14994           for (i = 0; i < XVECLEN (pat, 0); i++)
14995             {
14996               set = XVECEXP (pat, 0, i);
14997               if (GET_CODE (set) != SET)
14998                 continue;
14999
15000               reg = SET_DEST (set);
15001               while (GET_CODE (reg) == ZERO_EXTRACT
15002                      || GET_CODE (reg) == STRICT_LOW_PART
15003                      || GET_CODE (reg) == SUBREG)
15004                 reg = XEXP (reg, 0);
15005
15006               if (!REG_P (reg))
15007                 continue;
15008
15009               if (REGNO (reg) == link->regno)
15010                 break;
15011             }
15012           if (i == XVECLEN (pat, 0))
15013             continue;
15014         }
15015       else
15016         continue;
15017
15018       reg = SET_DEST (set);
15019
15020       while (GET_CODE (reg) == ZERO_EXTRACT
15021              || GET_CODE (reg) == STRICT_LOW_PART
15022              || GET_CODE (reg) == SUBREG)
15023         reg = XEXP (reg, 0);
15024
15025       if (reg == pc_rtx)
15026         continue;
15027
15028       /* A LOG_LINK is defined as being placed on the first insn that uses
15029          a register and points to the insn that sets the register.  Start
15030          searching at the next insn after the target of the link and stop
15031          when we reach a set of the register or the end of the basic block.
15032
15033          Note that this correctly handles the link that used to point from
15034          I3 to I2.  Also note that not much searching is typically done here
15035          since most links don't point very far away.  */
15036
15037       for (insn = NEXT_INSN (link->insn);
15038            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
15039                      || BB_HEAD (this_basic_block->next_bb) != insn));
15040            insn = NEXT_INSN (insn))
15041         if (DEBUG_INSN_P (insn))
15042           continue;
15043         else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
15044           {
15045             if (reg_referenced_p (reg, PATTERN (insn)))
15046               place = insn;
15047             break;
15048           }
15049         else if (CALL_P (insn)
15050                  && find_reg_fusage (insn, USE, reg))
15051           {
15052             place = insn;
15053             break;
15054           }
15055         else if (INSN_P (insn) && reg_set_p (reg, insn))
15056           break;
15057
15058       /* If we found a place to put the link, place it there unless there
15059          is already a link to the same insn as LINK at that point.  */
15060
15061       if (place)
15062         {
15063           struct insn_link *link2;
15064
15065           FOR_EACH_LOG_LINK (link2, place)
15066             if (link2->insn == link->insn && link2->regno == link->regno)
15067               break;
15068
15069           if (link2 == NULL)
15070             {
15071               link->next = LOG_LINKS (place);
15072               LOG_LINKS (place) = link;
15073
15074               /* Set added_links_insn to the earliest insn we added a
15075                  link to.  */
15076               if (added_links_insn == 0
15077                   || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
15078                 added_links_insn = place;
15079             }
15080         }
15081     }
15082 }
15083 \f
15084 /* Check for any register or memory mentioned in EQUIV that is not
15085    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
15086    of EXPR where some registers may have been replaced by constants.  */
15087
15088 static bool
15089 unmentioned_reg_p (rtx equiv, rtx expr)
15090 {
15091   subrtx_iterator::array_type array;
15092   FOR_EACH_SUBRTX (iter, array, equiv, NONCONST)
15093     {
15094       const_rtx x = *iter;
15095       if ((REG_P (x) || MEM_P (x))
15096           && !reg_mentioned_p (x, expr))
15097         return true;
15098     }
15099   return false;
15100 }
15101 \f
15102 /* Make pseudo-to-pseudo copies after every hard-reg-to-pseudo-copy, because
15103    the reg-to-reg copy can usefully combine with later instructions, but we
15104    do not want to combine the hard reg into later instructions, for that
15105    restricts register allocation.  */
15106 static void
15107 make_more_copies (void)
15108 {
15109   basic_block bb;
15110
15111   FOR_EACH_BB_FN (bb, cfun)
15112     {
15113       rtx_insn *insn;
15114
15115       FOR_BB_INSNS (bb, insn)
15116         {
15117           if (!NONDEBUG_INSN_P (insn))
15118             continue;
15119
15120           rtx set = single_set (insn);
15121           if (!set)
15122             continue;
15123
15124           rtx dest = SET_DEST (set);
15125           if (!(REG_P (dest) && !HARD_REGISTER_P (dest)))
15126               continue;
15127
15128           rtx src = SET_SRC (set);
15129           if (!(REG_P (src) && HARD_REGISTER_P (src)))
15130             continue;
15131           if (TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src)))
15132             continue;
15133
15134           rtx new_reg = gen_reg_rtx (GET_MODE (dest));
15135
15136           /* The "original" pseudo copies have important attributes
15137              attached, like pointerness.  We want that for these copies
15138              too, for use by insn recognition and later passes.  */
15139           set_reg_attrs_from_value (new_reg, dest);
15140
15141           rtx_insn *new_insn = gen_move_insn (new_reg, src);
15142           SET_SRC (set) = new_reg;
15143           emit_insn_before (new_insn, insn);
15144           df_insn_rescan (insn);
15145         }
15146     }
15147 }
15148
15149 /* Try combining insns through substitution.  */
15150 static void
15151 rest_of_handle_combine (void)
15152 {
15153   make_more_copies ();
15154
15155   df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
15156   df_note_add_problem ();
15157   df_analyze ();
15158
15159   regstat_init_n_sets_and_refs ();
15160   reg_n_sets_max = max_reg_num ();
15161
15162   bool rebuild_jump_labels_after_combine
15163     = combine_instructions (get_insns (), max_reg_num ());
15164
15165   /* Combining insns may have turned an indirect jump into a
15166      direct jump.  Rebuild the JUMP_LABEL fields of jumping
15167      instructions.  */
15168   if (rebuild_jump_labels_after_combine)
15169     {
15170       if (dom_info_available_p (CDI_DOMINATORS))
15171         free_dominance_info (CDI_DOMINATORS);
15172       timevar_push (TV_JUMP);
15173       rebuild_jump_labels (get_insns ());
15174       cleanup_cfg (0);
15175       timevar_pop (TV_JUMP);
15176     }
15177
15178   regstat_free_n_sets_and_refs ();
15179 }
15180
15181 namespace {
15182
15183 const pass_data pass_data_combine =
15184 {
15185   RTL_PASS, /* type */
15186   "combine", /* name */
15187   OPTGROUP_NONE, /* optinfo_flags */
15188   TV_COMBINE, /* tv_id */
15189   PROP_cfglayout, /* properties_required */
15190   0, /* properties_provided */
15191   0, /* properties_destroyed */
15192   0, /* todo_flags_start */
15193   TODO_df_finish, /* todo_flags_finish */
15194 };
15195
15196 class pass_combine : public rtl_opt_pass
15197 {
15198 public:
15199   pass_combine (gcc::context *ctxt)
15200     : rtl_opt_pass (pass_data_combine, ctxt)
15201   {}
15202
15203   /* opt_pass methods: */
15204   bool gate (function *) final override { return (optimize > 0); }
15205   unsigned int execute (function *) final override
15206     {
15207       rest_of_handle_combine ();
15208       return 0;
15209     }
15210
15211 }; // class pass_combine
15212
15213 } // anon namespace
15214
15215 rtl_opt_pass *
15216 make_pass_combine (gcc::context *ctxt)
15217 {
15218   return new pass_combine (ctxt);
15219 }