| blob | 11bfe1be8640284be5d7134844835c7184ffcdcc |
1 /* 32 and 64-bit millicode, original author Hewlett-Packard
2 adapted for gcc by Paul Bame <bame@debian.org>
3 and Alan Modra <alan@linuxcare.com.au>.
5 Copyright (C) 2001-2024 Free Software Foundation, Inc.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 3, or (at your option) any later
12 version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 for more details.
19 Under Section 7 of GPL version 3, you are granted additional
20 permissions described in the GCC Runtime Library Exception, version
21 3.1, as published by the Free Software Foundation.
23 You should have received a copy of the GNU General Public License and
24 a copy of the GCC Runtime Library Exception along with this program;
25 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
26 <http://www.gnu.org/licenses/>. */
28 /* An executable stack is *not* required for these functions. */
29 #if defined(__ELF__) && defined(__linux__)
30 .section .note.GNU-stack,"",%progbits
31 .previous
32 #endif
34 #ifdef pa64
35 .level 2.0w
36 #endif
38 /* Hardware General Registers. */
39 r0: .reg %r0
40 r1: .reg %r1
41 r2: .reg %r2
42 r3: .reg %r3
43 r4: .reg %r4
44 r5: .reg %r5
45 r6: .reg %r6
46 r7: .reg %r7
47 r8: .reg %r8
48 r9: .reg %r9
49 r10: .reg %r10
50 r11: .reg %r11
51 r12: .reg %r12
52 r13: .reg %r13
53 r14: .reg %r14
54 r15: .reg %r15
55 r16: .reg %r16
56 r17: .reg %r17
57 r18: .reg %r18
58 r19: .reg %r19
59 r20: .reg %r20
60 r21: .reg %r21
61 r22: .reg %r22
62 r23: .reg %r23
63 r24: .reg %r24
64 r25: .reg %r25
65 r26: .reg %r26
66 r27: .reg %r27
67 r28: .reg %r28
68 r29: .reg %r29
69 r30: .reg %r30
70 r31: .reg %r31
72 /* Hardware Space Registers. */
73 sr0: .reg %sr0
74 sr1: .reg %sr1
75 sr2: .reg %sr2
76 sr3: .reg %sr3
77 sr4: .reg %sr4
78 sr5: .reg %sr5
79 sr6: .reg %sr6
80 sr7: .reg %sr7
82 /* Hardware Floating Point Registers. */
83 fr0: .reg %fr0
84 fr1: .reg %fr1
85 fr2: .reg %fr2
86 fr3: .reg %fr3
87 fr4: .reg %fr4
88 fr5: .reg %fr5
89 fr6: .reg %fr6
90 fr7: .reg %fr7
91 fr8: .reg %fr8
92 fr9: .reg %fr9
93 fr10: .reg %fr10
94 fr11: .reg %fr11
95 fr12: .reg %fr12
96 fr13: .reg %fr13
97 fr14: .reg %fr14
98 fr15: .reg %fr15
100 /* Hardware Control Registers. */
101 cr11: .reg %cr11
102 sar: .reg %cr11 /* Shift Amount Register */
104 /* Software Architecture General Registers. */
105 rp: .reg r2 /* return pointer */
106 #ifdef pa64
107 mrp: .reg r2 /* millicode return pointer */
108 #define RETURN_COLUMN 2
109 #else
110 mrp: .reg r31 /* millicode return pointer */
111 #define RETURN_COLUMN 31
112 #endif
113 ret0: .reg r28 /* return value */
114 ret1: .reg r29 /* return value (high part of double) */
115 sp: .reg r30 /* stack pointer */
116 dp: .reg r27 /* data pointer */
117 arg0: .reg r26 /* argument */
118 arg1: .reg r25 /* argument or high part of double argument */
119 arg2: .reg r24 /* argument */
120 arg3: .reg r23 /* argument or high part of double argument */
122 /* Software Architecture Space Registers. */
123 /* sr0 ; return link from BLE */
124 sret: .reg sr1 /* return value */
125 sarg: .reg sr1 /* argument */
126 /* sr4 ; PC SPACE tracker */
127 /* sr5 ; process private data */
129 /* Frame Offsets (millicode convention!) Used when calling other
130 millicode routines. Stack unwinding is dependent upon these
131 definitions. */
132 r31_slot: .equ -20 /* "current RP" slot */
133 sr0_slot: .equ -16 /* "static link" slot */
134 #if defined(pa64)
135 mrp_slot: .equ -16 /* "current RP" slot */
136 psp_slot: .equ -8 /* "previous SP" slot */
137 #else
138 mrp_slot: .equ -20 /* "current RP" slot (replacing "r31_slot") */
139 #endif
142 #define DEFINE(name,value)name: .EQU value
143 #define RDEFINE(name,value)name: .REG value
144 #ifdef milliext
145 #define MILLI_BE(lbl) BE lbl(sr7,r0)
146 #define MILLI_BEN(lbl) BE,n lbl(sr7,r0)
147 #define MILLI_BLE(lbl) BLE lbl(sr7,r0)
148 #define MILLI_BLEN(lbl) BLE,n lbl(sr7,r0)
149 #define MILLIRETN BE,n 0(sr0,mrp)
150 #define MILLIRET BE 0(sr0,mrp)
151 #define MILLI_RETN BE,n 0(sr0,mrp)
152 #define MILLI_RET BE 0(sr0,mrp)
153 #else
154 #define MILLI_BE(lbl) B lbl
155 #define MILLI_BEN(lbl) B,n lbl
156 #define MILLI_BLE(lbl) BL lbl,mrp
157 #define MILLI_BLEN(lbl) BL,n lbl,mrp
158 #define MILLIRETN BV,n 0(mrp)
159 #define MILLIRET BV 0(mrp)
160 #define MILLI_RETN BV,n 0(mrp)
161 #define MILLI_RET BV 0(mrp)
162 #endif
164 #ifdef __STDC__
165 #define CAT(a,b) a##b
166 #else
167 #define CAT(a,b) a/**/b
168 #endif
170 #ifdef ELF
171 #define SUBSPA_MILLI .section .text
172 #define SUBSPA_MILLI_DIV .section .text.div,"ax",@progbits! .align 16
173 #define SUBSPA_MILLI_MUL .section .text.mul,"ax",@progbits! .align 16
174 #define ATTR_MILLI
175 #define SUBSPA_DATA .section .data
176 #define ATTR_DATA
177 #define GLOBAL $global$
178 #define GSYM(sym) !sym:
179 #define LSYM(sym) !CAT(.L,sym:)
180 #define LREF(sym) CAT(.L,sym)
182 #else
184 #ifdef coff
185 /* This used to be .milli but since link32 places different named
186 sections in different segments millicode ends up a long ways away
187 from .text (1meg?). This way they will be a lot closer.
189 The SUBSPA_MILLI_* specify locality sets for certain millicode
190 modules in order to ensure that modules that call one another are
191 placed close together. Without locality sets this is unlikely to
192 happen because of the Dynamite linker library search algorithm. We
193 want these modules close together so that short calls always reach
194 (we don't want to require long calls or use long call stubs). */
196 #define SUBSPA_MILLI .subspa .text
197 #define SUBSPA_MILLI_DIV .subspa .text$dv,align=16
198 #define SUBSPA_MILLI_MUL .subspa .text$mu,align=16
199 #define ATTR_MILLI .attr code,read,execute
200 #define SUBSPA_DATA .subspa .data
201 #define ATTR_DATA .attr init_data,read,write
202 #define GLOBAL _gp
203 #else
204 #define SUBSPA_MILLI .subspa $MILLICODE$,QUAD=0,ALIGN=4,ACCESS=0x2c,SORT=8
205 #define SUBSPA_MILLI_DIV SUBSPA_MILLI
206 #define SUBSPA_MILLI_MUL SUBSPA_MILLI
207 #define ATTR_MILLI
208 #define SUBSPA_DATA .subspa $BSS$,quad=1,align=8,access=0x1f,sort=80,zero
209 #define ATTR_DATA
210 #define GLOBAL $global$
211 #endif
212 #define SPACE_DATA .space $PRIVATE$,spnum=1,sort=16
214 #define GSYM(sym) !sym
215 #define LSYM(sym) !CAT(L$,sym)
216 #define LREF(sym) CAT(L$,sym)
217 #endif
219 #ifdef L_dyncall
220 SUBSPA_MILLI
221 ATTR_DATA
222 GSYM($$dyncall)
223 .export $$dyncall,millicode
224 .proc
225 .callinfo millicode
226 .entry
227 #ifdef LINUX
228 extru,<> %r22,30,1,%r0 ; nullify if plabel bit set
229 bv,n %r0(%r22) ; branch to target
230 ldw -2(%r22),%r21 ; load address of target
231 bv %r0(%r21) ; branch to the real target
232 ldw 2(%r22),%r19 ; load new LTP value
233 #else
234 bb,>=,n %r22,30,LREF(1) ; branch if not plabel address
235 ldw -2(%r22),%r21 ; load address of target to r21
236 ldsid (%sr0,%r21),%r1 ; get the "space ident" selected by r21
237 ldw 2(%r22),%r19 ; load new LTP value
238 mtsp %r1,%sr0 ; move that space identifier into sr0
239 be 0(%sr0,%r21) ; branch to the real target
240 stw %r2,-24(%r30) ; save return address into frame marker
241 LSYM(1)
242 ldsid (%sr0,%r22),%r1 ; get the "space ident" selected by r22
243 mtsp %r1,%sr0 ; move that space identifier into sr0
244 be 0(%sr0,%r22) ; branch to the target
245 stw %r2,-24(%r30) ; save return address into frame marker
246 #endif
247 .exit
248 .procend
249 #endif
251 #ifdef L_divI
252 /* ROUTINES: $$divI, $$divoI
254 Single precision divide for signed binary integers.
256 The quotient is truncated towards zero.
257 The sign of the quotient is the XOR of the signs of the dividend and
258 divisor.
259 Divide by zero is trapped.
260 Divide of -2**31 by -1 is trapped for $$divoI but not for $$divI.
262 INPUT REGISTERS:
263 . arg0 == dividend
264 . arg1 == divisor
265 . mrp == return pc
266 . sr0 == return space when called externally
268 OUTPUT REGISTERS:
269 . arg0 = undefined
270 . arg1 = undefined
271 . ret1 = quotient
273 OTHER REGISTERS AFFECTED:
274 . r1 = undefined
276 SIDE EFFECTS:
277 . Causes a trap under the following conditions:
278 . divisor is zero (traps with ADDIT,= 0,25,0)
279 . dividend==-2**31 and divisor==-1 and routine is $$divoI
280 . (traps with ADDO 26,25,0)
281 . Changes memory at the following places:
282 . NONE
284 PERMISSIBLE CONTEXT:
285 . Unwindable.
286 . Suitable for internal or external millicode.
287 . Assumes the special millicode register conventions.
289 DISCUSSION:
290 . Branchs to other millicode routines using BE
291 . $$div_# for # being 2,3,4,5,6,7,8,9,10,12,14,15
292 .
293 . For selected divisors, calls a divide by constant routine written by
294 . Karl Pettis. Eligible divisors are 1..15 excluding 11 and 13.
295 .
296 . The only overflow case is -2**31 divided by -1.
297 . Both routines return -2**31 but only $$divoI traps. */
299 RDEFINE(temp,r1)
300 RDEFINE(retreg,ret1) /* r29 */
301 RDEFINE(temp1,arg0)
302 SUBSPA_MILLI_DIV
303 ATTR_MILLI
304 .import $$divI_2,millicode
305 .import $$divI_3,millicode
306 .import $$divI_4,millicode
307 .import $$divI_5,millicode
308 .import $$divI_6,millicode
309 .import $$divI_7,millicode
310 .import $$divI_8,millicode
311 .import $$divI_9,millicode
312 .import $$divI_10,millicode
313 .import $$divI_12,millicode
314 .import $$divI_14,millicode
315 .import $$divI_15,millicode
316 .export $$divI,millicode
317 .export $$divoI,millicode
318 .cfi_startproc
319 .cfi_return_column RETURN_COLUMN
320 .proc
321 .callinfo millicode
322 .entry
323 GSYM($$divoI)
324 comib,=,n -1,arg1,LREF(negative1) /* when divisor == -1 */
325 GSYM($$divI)
326 ldo -1(arg1),temp /* is there at most one bit set ? */
327 and,<> arg1,temp,r0 /* if not, don't use power of 2 divide */
328 addi,> 0,arg1,r0 /* if divisor > 0, use power of 2 divide */
329 b,n LREF(neg_denom)
330 LSYM(pow2)
331 addi,>= 0,arg0,retreg /* if numerator is negative, add the */
332 add arg0,temp,retreg /* (denominaotr -1) to correct for shifts */
333 extru,= arg1,15,16,temp /* test denominator with 0xffff0000 */
334 extrs retreg,15,16,retreg /* retreg = retreg >> 16 */
335 or arg1,temp,arg1 /* arg1 = arg1 | (arg1 >> 16) */
336 ldi 0xcc,temp1 /* setup 0xcc in temp1 */
337 extru,= arg1,23,8,temp /* test denominator with 0xff00 */
338 extrs retreg,23,24,retreg /* retreg = retreg >> 8 */
339 or arg1,temp,arg1 /* arg1 = arg1 | (arg1 >> 8) */
340 ldi 0xaa,temp /* setup 0xaa in temp */
341 extru,= arg1,27,4,r0 /* test denominator with 0xf0 */
342 extrs retreg,27,28,retreg /* retreg = retreg >> 4 */
343 and,= arg1,temp1,r0 /* test denominator with 0xcc */
344 extrs retreg,29,30,retreg /* retreg = retreg >> 2 */
345 and,= arg1,temp,r0 /* test denominator with 0xaa */
346 extrs retreg,30,31,retreg /* retreg = retreg >> 1 */
347 MILLIRETN
348 LSYM(neg_denom)
349 addi,< 0,arg1,r0 /* if arg1 >= 0, it's not power of 2 */
350 b,n LREF(regular_seq)
351 sub r0,arg1,temp /* make denominator positive */
352 comb,=,n arg1,temp,LREF(regular_seq) /* test against 0x80000000 and 0 */
353 ldo -1(temp),retreg /* is there at most one bit set ? */
354 and,= temp,retreg,r0 /* if so, the denominator is power of 2 */
355 b,n LREF(regular_seq)
356 sub r0,arg0,retreg /* negate numerator */
357 comb,=,n arg0,retreg,LREF(regular_seq) /* test against 0x80000000 */
358 copy retreg,arg0 /* set up arg0, arg1 and temp */
359 copy temp,arg1 /* before branching to pow2 */
360 b LREF(pow2)
361 ldo -1(arg1),temp
362 LSYM(regular_seq)
363 comib,>>=,n 15,arg1,LREF(small_divisor)
364 add,>= 0,arg0,retreg /* move dividend, if retreg < 0, */
365 LSYM(normal)
366 subi 0,retreg,retreg /* make it positive */
367 sub 0,arg1,temp /* clear carry, */
368 /* negate the divisor */
369 ds 0,temp,0 /* set V-bit to the comple- */
370 /* ment of the divisor sign */
371 add retreg,retreg,retreg /* shift msb bit into carry */
372 ds r0,arg1,temp /* 1st divide step, if no carry */
373 addc retreg,retreg,retreg /* shift retreg with/into carry */
374 ds temp,arg1,temp /* 2nd divide step */
375 addc retreg,retreg,retreg /* shift retreg with/into carry */
376 ds temp,arg1,temp /* 3rd divide step */
377 addc retreg,retreg,retreg /* shift retreg with/into carry */
378 ds temp,arg1,temp /* 4th divide step */
379 addc retreg,retreg,retreg /* shift retreg with/into carry */
380 ds temp,arg1,temp /* 5th divide step */
381 addc retreg,retreg,retreg /* shift retreg with/into carry */
382 ds temp,arg1,temp /* 6th divide step */
383 addc retreg,retreg,retreg /* shift retreg with/into carry */
384 ds temp,arg1,temp /* 7th divide step */
385 addc retreg,retreg,retreg /* shift retreg with/into carry */
386 ds temp,arg1,temp /* 8th divide step */
387 addc retreg,retreg,retreg /* shift retreg with/into carry */
388 ds temp,arg1,temp /* 9th divide step */
389 addc retreg,retreg,retreg /* shift retreg with/into carry */
390 ds temp,arg1,temp /* 10th divide step */
391 addc retreg,retreg,retreg /* shift retreg with/into carry */
392 ds temp,arg1,temp /* 11th divide step */
393 addc retreg,retreg,retreg /* shift retreg with/into carry */
394 ds temp,arg1,temp /* 12th divide step */
395 addc retreg,retreg,retreg /* shift retreg with/into carry */
396 ds temp,arg1,temp /* 13th divide step */
397 addc retreg,retreg,retreg /* shift retreg with/into carry */
398 ds temp,arg1,temp /* 14th divide step */
399 addc retreg,retreg,retreg /* shift retreg with/into carry */
400 ds temp,arg1,temp /* 15th divide step */
401 addc retreg,retreg,retreg /* shift retreg with/into carry */
402 ds temp,arg1,temp /* 16th divide step */
403 addc retreg,retreg,retreg /* shift retreg with/into carry */
404 ds temp,arg1,temp /* 17th divide step */
405 addc retreg,retreg,retreg /* shift retreg with/into carry */
406 ds temp,arg1,temp /* 18th divide step */
407 addc retreg,retreg,retreg /* shift retreg with/into carry */
408 ds temp,arg1,temp /* 19th divide step */
409 addc retreg,retreg,retreg /* shift retreg with/into carry */
410 ds temp,arg1,temp /* 20th divide step */
411 addc retreg,retreg,retreg /* shift retreg with/into carry */
412 ds temp,arg1,temp /* 21st divide step */
413 addc retreg,retreg,retreg /* shift retreg with/into carry */
414 ds temp,arg1,temp /* 22nd divide step */
415 addc retreg,retreg,retreg /* shift retreg with/into carry */
416 ds temp,arg1,temp /* 23rd divide step */
417 addc retreg,retreg,retreg /* shift retreg with/into carry */
418 ds temp,arg1,temp /* 24th divide step */
419 addc retreg,retreg,retreg /* shift retreg with/into carry */
420 ds temp,arg1,temp /* 25th divide step */
421 addc retreg,retreg,retreg /* shift retreg with/into carry */
422 ds temp,arg1,temp /* 26th divide step */
423 addc retreg,retreg,retreg /* shift retreg with/into carry */
424 ds temp,arg1,temp /* 27th divide step */
425 addc retreg,retreg,retreg /* shift retreg with/into carry */
426 ds temp,arg1,temp /* 28th divide step */
427 addc retreg,retreg,retreg /* shift retreg with/into carry */
428 ds temp,arg1,temp /* 29th divide step */
429 addc retreg,retreg,retreg /* shift retreg with/into carry */
430 ds temp,arg1,temp /* 30th divide step */
431 addc retreg,retreg,retreg /* shift retreg with/into carry */
432 ds temp,arg1,temp /* 31st divide step */
433 addc retreg,retreg,retreg /* shift retreg with/into carry */
434 ds temp,arg1,temp /* 32nd divide step, */
435 addc retreg,retreg,retreg /* shift last retreg bit into retreg */
436 xor,>= arg0,arg1,0 /* get correct sign of quotient */
437 sub 0,retreg,retreg /* based on operand signs */
438 MILLIRETN
439 nop
441 LSYM(small_divisor)
443 #if defined(pa64)
444 /* Clear the upper 32 bits of the arg1 register. We are working with */
445 /* small divisors (and 32-bit integers) We must not be mislead */
446 /* by "1" bits left in the upper 32 bits. */
447 depd %r0,31,32,%r25
448 #endif
449 blr,n arg1,r0
450 nop
451 /* table for divisor == 0,1, ... ,15 */
452 addit,= 0,arg1,r0 /* trap if divisor == 0 */
453 nop
454 MILLIRET /* divisor == 1 */
455 copy arg0,retreg
456 MILLI_BEN($$divI_2) /* divisor == 2 */
457 nop
458 MILLI_BEN($$divI_3) /* divisor == 3 */
459 nop
460 MILLI_BEN($$divI_4) /* divisor == 4 */
461 nop
462 MILLI_BEN($$divI_5) /* divisor == 5 */
463 nop
464 MILLI_BEN($$divI_6) /* divisor == 6 */
465 nop
466 MILLI_BEN($$divI_7) /* divisor == 7 */
467 nop
468 MILLI_BEN($$divI_8) /* divisor == 8 */
469 nop
470 MILLI_BEN($$divI_9) /* divisor == 9 */
471 nop
472 MILLI_BEN($$divI_10) /* divisor == 10 */
473 nop
474 b LREF(normal) /* divisor == 11 */
475 add,>= 0,arg0,retreg
476 MILLI_BEN($$divI_12) /* divisor == 12 */
477 nop
478 b LREF(normal) /* divisor == 13 */
479 add,>= 0,arg0,retreg
480 MILLI_BEN($$divI_14) /* divisor == 14 */
481 nop
482 MILLI_BEN($$divI_15) /* divisor == 15 */
483 nop
485 LSYM(negative1)
486 sub 0,arg0,retreg /* result is negation of dividend */
487 MILLIRET
488 addo arg0,arg1,r0 /* trap iff dividend==0x80000000 && divisor==-1 */
489 .exit
490 .procend
491 .cfi_endproc
492 .end
493 #endif
495 #ifdef L_divU
496 /* ROUTINE: $$divU
497 .
498 . Single precision divide for unsigned integers.
499 .
500 . Quotient is truncated towards zero.
501 . Traps on divide by zero.
503 INPUT REGISTERS:
504 . arg0 == dividend
505 . arg1 == divisor
506 . mrp == return pc
507 . sr0 == return space when called externally
509 OUTPUT REGISTERS:
510 . arg0 = undefined
511 . arg1 = undefined
512 . ret1 = quotient
514 OTHER REGISTERS AFFECTED:
515 . r1 = undefined
517 SIDE EFFECTS:
518 . Causes a trap under the following conditions:
519 . divisor is zero
520 . Changes memory at the following places:
521 . NONE
523 PERMISSIBLE CONTEXT:
524 . Unwindable.
525 . Does not create a stack frame.
526 . Suitable for internal or external millicode.
527 . Assumes the special millicode register conventions.
529 DISCUSSION:
530 . Branchs to other millicode routines using BE:
531 . $$divU_# for 3,5,6,7,9,10,12,14,15
532 .
533 . For selected small divisors calls the special divide by constant
534 . routines written by Karl Pettis. These are: 3,5,6,7,9,10,12,14,15. */
536 RDEFINE(temp,r1)
537 RDEFINE(retreg,ret1) /* r29 */
538 RDEFINE(temp1,arg0)
539 SUBSPA_MILLI_DIV
540 ATTR_MILLI
541 .export $$divU,millicode
542 .import $$divU_3,millicode
543 .import $$divU_5,millicode
544 .import $$divU_6,millicode
545 .import $$divU_7,millicode
546 .import $$divU_9,millicode
547 .import $$divU_10,millicode
548 .import $$divU_12,millicode
549 .import $$divU_14,millicode
550 .import $$divU_15,millicode
551 .cfi_startproc
552 .cfi_return_column RETURN_COLUMN
553 .proc
554 .callinfo millicode
555 .entry
556 GSYM($$divU)
557 /* The subtract is not nullified since it does no harm and can be used
558 by the two cases that branch back to "normal". */
559 ldo -1(arg1),temp /* is there at most one bit set ? */
560 and,= arg1,temp,r0 /* if so, denominator is power of 2 */
561 b LREF(regular_seq)
562 addit,= 0,arg1,0 /* trap for zero dvr */
563 copy arg0,retreg
564 extru,= arg1,15,16,temp /* test denominator with 0xffff0000 */
565 extru retreg,15,16,retreg /* retreg = retreg >> 16 */
566 or arg1,temp,arg1 /* arg1 = arg1 | (arg1 >> 16) */
567 ldi 0xcc,temp1 /* setup 0xcc in temp1 */
568 extru,= arg1,23,8,temp /* test denominator with 0xff00 */
569 extru retreg,23,24,retreg /* retreg = retreg >> 8 */
570 or arg1,temp,arg1 /* arg1 = arg1 | (arg1 >> 8) */
571 ldi 0xaa,temp /* setup 0xaa in temp */
572 extru,= arg1,27,4,r0 /* test denominator with 0xf0 */
573 extru retreg,27,28,retreg /* retreg = retreg >> 4 */
574 and,= arg1,temp1,r0 /* test denominator with 0xcc */
575 extru retreg,29,30,retreg /* retreg = retreg >> 2 */
576 and,= arg1,temp,r0 /* test denominator with 0xaa */
577 extru retreg,30,31,retreg /* retreg = retreg >> 1 */
578 MILLIRETN
579 nop
580 LSYM(regular_seq)
581 comib,>= 15,arg1,LREF(special_divisor)
582 subi 0,arg1,temp /* clear carry, negate the divisor */
583 ds r0,temp,r0 /* set V-bit to 1 */
584 LSYM(normal)
585 add arg0,arg0,retreg /* shift msb bit into carry */
586 ds r0,arg1,temp /* 1st divide step, if no carry */
587 addc retreg,retreg,retreg /* shift retreg with/into carry */
588 ds temp,arg1,temp /* 2nd divide step */
589 addc retreg,retreg,retreg /* shift retreg with/into carry */
590 ds temp,arg1,temp /* 3rd divide step */
591 addc retreg,retreg,retreg /* shift retreg with/into carry */
592 ds temp,arg1,temp /* 4th divide step */
593 addc retreg,retreg,retreg /* shift retreg with/into carry */
594 ds temp,arg1,temp /* 5th divide step */
595 addc retreg,retreg,retreg /* shift retreg with/into carry */
596 ds temp,arg1,temp /* 6th divide step */
597 addc retreg,retreg,retreg /* shift retreg with/into carry */
598 ds temp,arg1,temp /* 7th divide step */
599 addc retreg,retreg,retreg /* shift retreg with/into carry */
600 ds temp,arg1,temp /* 8th divide step */
601 addc retreg,retreg,retreg /* shift retreg with/into carry */
602 ds temp,arg1,temp /* 9th divide step */
603 addc retreg,retreg,retreg /* shift retreg with/into carry */
604 ds temp,arg1,temp /* 10th divide step */
605 addc retreg,retreg,retreg /* shift retreg with/into carry */
606 ds temp,arg1,temp /* 11th divide step */
607 addc retreg,retreg,retreg /* shift retreg with/into carry */
608 ds temp,arg1,temp /* 12th divide step */
609 addc retreg,retreg,retreg /* shift retreg with/into carry */
610 ds temp,arg1,temp /* 13th divide step */
611 addc retreg,retreg,retreg /* shift retreg with/into carry */
612 ds temp,arg1,temp /* 14th divide step */
613 addc retreg,retreg,retreg /* shift retreg with/into carry */
614 ds temp,arg1,temp /* 15th divide step */
615 addc retreg,retreg,retreg /* shift retreg with/into carry */
616 ds temp,arg1,temp /* 16th divide step */
617 addc retreg,retreg,retreg /* shift retreg with/into carry */
618 ds temp,arg1,temp /* 17th divide step */
619 addc retreg,retreg,retreg /* shift retreg with/into carry */
620 ds temp,arg1,temp /* 18th divide step */
621 addc retreg,retreg,retreg /* shift retreg with/into carry */
622 ds temp,arg1,temp /* 19th divide step */
623 addc retreg,retreg,retreg /* shift retreg with/into carry */
624 ds temp,arg1,temp /* 20th divide step */
625 addc retreg,retreg,retreg /* shift retreg with/into carry */
626 ds temp,arg1,temp /* 21st divide step */
627 addc retreg,retreg,retreg /* shift retreg with/into carry */
628 ds temp,arg1,temp /* 22nd divide step */
629 addc retreg,retreg,retreg /* shift retreg with/into carry */
630 ds temp,arg1,temp /* 23rd divide step */
631 addc retreg,retreg,retreg /* shift retreg with/into carry */
632 ds temp,arg1,temp /* 24th divide step */
633 addc retreg,retreg,retreg /* shift retreg with/into carry */
634 ds temp,arg1,temp /* 25th divide step */
635 addc retreg,retreg,retreg /* shift retreg with/into carry */
636 ds temp,arg1,temp /* 26th divide step */
637 addc retreg,retreg,retreg /* shift retreg with/into carry */
638 ds temp,arg1,temp /* 27th divide step */
639 addc retreg,retreg,retreg /* shift retreg with/into carry */
640 ds temp,arg1,temp /* 28th divide step */
641 addc retreg,retreg,retreg /* shift retreg with/into carry */
642 ds temp,arg1,temp /* 29th divide step */
643 addc retreg,retreg,retreg /* shift retreg with/into carry */
644 ds temp,arg1,temp /* 30th divide step */
645 addc retreg,retreg,retreg /* shift retreg with/into carry */
646 ds temp,arg1,temp /* 31st divide step */
647 addc retreg,retreg,retreg /* shift retreg with/into carry */
648 ds temp,arg1,temp /* 32nd divide step, */
649 MILLIRET
650 addc retreg,retreg,retreg /* shift last retreg bit into retreg */
652 /* Handle the cases where divisor is a small constant or has high bit on. */
653 LSYM(special_divisor)
654 /* blr arg1,r0 */
655 /* comib,>,n 0,arg1,LREF(big_divisor) ; nullify previous instruction */
657 /* Pratap 8/13/90. The 815 Stirling chip set has a bug that prevents us from
658 generating such a blr, comib sequence. A problem in nullification. So I
659 rewrote this code. */
661 #if defined(pa64)
662 /* Clear the upper 32 bits of the arg1 register. We are working with
663 small divisors (and 32-bit unsigned integers) We must not be mislead
664 by "1" bits left in the upper 32 bits. */
665 depd %r0,31,32,%r25
666 #endif
667 comib,> 0,arg1,LREF(big_divisor)
668 nop
669 blr arg1,r0
670 nop
672 LSYM(zero_divisor) /* this label is here to provide external visibility */
673 addit,= 0,arg1,0 /* trap for zero dvr */
674 nop
675 MILLIRET /* divisor == 1 */
676 copy arg0,retreg
677 MILLIRET /* divisor == 2 */
678 extru arg0,30,31,retreg
679 MILLI_BEN($$divU_3) /* divisor == 3 */
680 nop
681 MILLIRET /* divisor == 4 */
682 extru arg0,29,30,retreg
683 MILLI_BEN($$divU_5) /* divisor == 5 */
684 nop
685 MILLI_BEN($$divU_6) /* divisor == 6 */
686 nop
687 MILLI_BEN($$divU_7) /* divisor == 7 */
688 nop
689 MILLIRET /* divisor == 8 */
690 extru arg0,28,29,retreg
691 MILLI_BEN($$divU_9) /* divisor == 9 */
692 nop
693 MILLI_BEN($$divU_10) /* divisor == 10 */
694 nop
695 b LREF(normal) /* divisor == 11 */
696 ds r0,temp,r0 /* set V-bit to 1 */
697 MILLI_BEN($$divU_12) /* divisor == 12 */
698 nop
699 b LREF(normal) /* divisor == 13 */
700 ds r0,temp,r0 /* set V-bit to 1 */
701 MILLI_BEN($$divU_14) /* divisor == 14 */
702 nop
703 MILLI_BEN($$divU_15) /* divisor == 15 */
704 nop
706 /* Handle the case where the high bit is on in the divisor.
707 Compute: if( dividend>=divisor) quotient=1; else quotient=0;
708 Note: dividend>==divisor iff dividend-divisor does not borrow
709 and not borrow iff carry. */
710 LSYM(big_divisor)
711 sub arg0,arg1,r0
712 MILLIRET
713 addc r0,r0,retreg
714 .exit
715 .procend
716 .cfi_endproc
717 .end
718 #endif
720 #ifdef L_remI
721 /* ROUTINE: $$remI
723 DESCRIPTION:
724 . $$remI returns the remainder of the division of two signed 32-bit
725 . integers. The sign of the remainder is the same as the sign of
726 . the dividend.
729 INPUT REGISTERS:
730 . arg0 == dividend
731 . arg1 == divisor
732 . mrp == return pc
733 . sr0 == return space when called externally
735 OUTPUT REGISTERS:
736 . arg0 = destroyed
737 . arg1 = destroyed
738 . ret1 = remainder
740 OTHER REGISTERS AFFECTED:
741 . r1 = undefined
743 SIDE EFFECTS:
744 . Causes a trap under the following conditions: DIVIDE BY ZERO
745 . Changes memory at the following places: NONE
747 PERMISSIBLE CONTEXT:
748 . Unwindable
749 . Does not create a stack frame
750 . Is usable for internal or external microcode
752 DISCUSSION:
753 . Calls other millicode routines via mrp: NONE
754 . Calls other millicode routines: NONE */
756 RDEFINE(tmp,r1)
757 RDEFINE(retreg,ret1)
759 SUBSPA_MILLI
760 ATTR_MILLI
761 .cfi_startproc
762 .cfi_return_column RETURN_COLUMN
763 .proc
764 .callinfo millicode
765 .entry
766 GSYM($$remI)
767 GSYM($$remoI)
768 .export $$remI,MILLICODE
769 .export $$remoI,MILLICODE
770 ldo -1(arg1),tmp /* is there at most one bit set ? */
771 and,<> arg1,tmp,r0 /* if not, don't use power of 2 */
772 addi,> 0,arg1,r0 /* if denominator > 0, use power */
773 /* of 2 */
774 b,n LREF(neg_denom)
775 LSYM(pow2)
776 comb,>,n 0,arg0,LREF(neg_num) /* is numerator < 0 ? */
777 and arg0,tmp,retreg /* get the result */
778 MILLIRETN
779 LSYM(neg_num)
780 subi 0,arg0,arg0 /* negate numerator */
781 and arg0,tmp,retreg /* get the result */
782 subi 0,retreg,retreg /* negate result */
783 MILLIRETN
784 LSYM(neg_denom)
785 addi,< 0,arg1,r0 /* if arg1 >= 0, it's not power */
786 /* of 2 */
787 b,n LREF(regular_seq)
788 sub r0,arg1,tmp /* make denominator positive */
789 comb,=,n arg1,tmp,LREF(regular_seq) /* test against 0x80000000 and 0 */
790 ldo -1(tmp),retreg /* is there at most one bit set ? */
791 and,= tmp,retreg,r0 /* if not, go to regular_seq */
792 b,n LREF(regular_seq)
793 comb,>,n 0,arg0,LREF(neg_num_2) /* if arg0 < 0, negate it */
794 and arg0,retreg,retreg
795 MILLIRETN
796 LSYM(neg_num_2)
797 subi 0,arg0,tmp /* test against 0x80000000 */
798 and tmp,retreg,retreg
799 subi 0,retreg,retreg
800 MILLIRETN
801 LSYM(regular_seq)
802 addit,= 0,arg1,0 /* trap if div by zero */
803 add,>= 0,arg0,retreg /* move dividend, if retreg < 0, */
804 sub 0,retreg,retreg /* make it positive */
805 sub 0,arg1, tmp /* clear carry, */
806 /* negate the divisor */
807 ds 0, tmp,0 /* set V-bit to the comple- */
808 /* ment of the divisor sign */
809 or 0,0, tmp /* clear tmp */
810 add retreg,retreg,retreg /* shift msb bit into carry */
811 ds tmp,arg1, tmp /* 1st divide step, if no carry */
812 /* out, msb of quotient = 0 */
813 addc retreg,retreg,retreg /* shift retreg with/into carry */
814 LSYM(t1)
815 ds tmp,arg1, tmp /* 2nd divide step */
816 addc retreg,retreg,retreg /* shift retreg with/into carry */
817 ds tmp,arg1, tmp /* 3rd divide step */
818 addc retreg,retreg,retreg /* shift retreg with/into carry */
819 ds tmp,arg1, tmp /* 4th divide step */
820 addc retreg,retreg,retreg /* shift retreg with/into carry */
821 ds tmp,arg1, tmp /* 5th divide step */
822 addc retreg,retreg,retreg /* shift retreg with/into carry */
823 ds tmp,arg1, tmp /* 6th divide step */
824 addc retreg,retreg,retreg /* shift retreg with/into carry */
825 ds tmp,arg1, tmp /* 7th divide step */
826 addc retreg,retreg,retreg /* shift retreg with/into carry */
827 ds tmp,arg1, tmp /* 8th divide step */
828 addc retreg,retreg,retreg /* shift retreg with/into carry */
829 ds tmp,arg1, tmp /* 9th divide step */
830 addc retreg,retreg,retreg /* shift retreg with/into carry */
831 ds tmp,arg1, tmp /* 10th divide step */
832 addc retreg,retreg,retreg /* shift retreg with/into carry */
833 ds tmp,arg1, tmp /* 11th divide step */
834 addc retreg,retreg,retreg /* shift retreg with/into carry */
835 ds tmp,arg1, tmp /* 12th divide step */
836 addc retreg,retreg,retreg /* shift retreg with/into carry */
837 ds tmp,arg1, tmp /* 13th divide step */
838 addc retreg,retreg,retreg /* shift retreg with/into carry */
839 ds tmp,arg1, tmp /* 14th divide step */
840 addc retreg,retreg,retreg /* shift retreg with/into carry */
841 ds tmp,arg1, tmp /* 15th divide step */
842 addc retreg,retreg,retreg /* shift retreg with/into carry */
843 ds tmp,arg1, tmp /* 16th divide step */
844 addc retreg,retreg,retreg /* shift retreg with/into carry */
845 ds tmp,arg1, tmp /* 17th divide step */
846 addc retreg,retreg,retreg /* shift retreg with/into carry */
847 ds tmp,arg1, tmp /* 18th divide step */
848 addc retreg,retreg,retreg /* shift retreg with/into carry */
849 ds tmp,arg1, tmp /* 19th divide step */
850 addc retreg,retreg,retreg /* shift retreg with/into carry */
851 ds tmp,arg1, tmp /* 20th divide step */
852 addc retreg,retreg,retreg /* shift retreg with/into carry */
853 ds tmp,arg1, tmp /* 21st divide step */
854 addc retreg,retreg,retreg /* shift retreg with/into carry */
855 ds tmp,arg1, tmp /* 22nd divide step */
856 addc retreg,retreg,retreg /* shift retreg with/into carry */
857 ds tmp,arg1, tmp /* 23rd divide step */
858 addc retreg,retreg,retreg /* shift retreg with/into carry */
859 ds tmp,arg1, tmp /* 24th divide step */
860 addc retreg,retreg,retreg /* shift retreg with/into carry */
861 ds tmp,arg1, tmp /* 25th divide step */
862 addc retreg,retreg,retreg /* shift retreg with/into carry */
863 ds tmp,arg1, tmp /* 26th divide step */
864 addc retreg,retreg,retreg /* shift retreg with/into carry */
865 ds tmp,arg1, tmp /* 27th divide step */
866 addc retreg,retreg,retreg /* shift retreg with/into carry */
867 ds tmp,arg1, tmp /* 28th divide step */
868 addc retreg,retreg,retreg /* shift retreg with/into carry */
869 ds tmp,arg1, tmp /* 29th divide step */
870 addc retreg,retreg,retreg /* shift retreg with/into carry */
871 ds tmp,arg1, tmp /* 30th divide step */
872 addc retreg,retreg,retreg /* shift retreg with/into carry */
873 ds tmp,arg1, tmp /* 31st divide step */
874 addc retreg,retreg,retreg /* shift retreg with/into carry */
875 ds tmp,arg1, tmp /* 32nd divide step, */
876 addc retreg,retreg,retreg /* shift last bit into retreg */
877 movb,>=,n tmp,retreg,LREF(finish) /* branch if pos. tmp */
878 add,< arg1,0,0 /* if arg1 > 0, add arg1 */
879 add,tr tmp,arg1,retreg /* for correcting remainder tmp */
880 sub tmp,arg1,retreg /* else add absolute value arg1 */
881 LSYM(finish)
882 add,>= arg0,0,0 /* set sign of remainder */
883 sub 0,retreg,retreg /* to sign of dividend */
884 MILLIRET
885 nop
886 .exit
887 .procend
888 .cfi_endproc
889 #ifdef milliext
890 .origin 0x00000200
891 #endif
892 .end
893 #endif
895 #ifdef L_remU
896 /* ROUTINE: $$remU
897 . Single precision divide for remainder with unsigned binary integers.
898 .
899 . The remainder must be dividend-(dividend/divisor)*divisor.
900 . Divide by zero is trapped.
902 INPUT REGISTERS:
903 . arg0 == dividend
904 . arg1 == divisor
905 . mrp == return pc
906 . sr0 == return space when called externally
908 OUTPUT REGISTERS:
909 . arg0 = undefined
910 . arg1 = undefined
911 . ret1 = remainder
913 OTHER REGISTERS AFFECTED:
914 . r1 = undefined
916 SIDE EFFECTS:
917 . Causes a trap under the following conditions: DIVIDE BY ZERO
918 . Changes memory at the following places: NONE
920 PERMISSIBLE CONTEXT:
921 . Unwindable.
922 . Does not create a stack frame.
923 . Suitable for internal or external millicode.
924 . Assumes the special millicode register conventions.
926 DISCUSSION:
927 . Calls other millicode routines using mrp: NONE
928 . Calls other millicode routines: NONE */
931 RDEFINE(temp,r1)
932 RDEFINE(rmndr,ret1) /* r29 */
933 SUBSPA_MILLI
934 ATTR_MILLI
935 .export $$remU,millicode
936 .cfi_startproc
937 .cfi_return_column RETURN_COLUMN
938 .proc
939 .callinfo millicode
940 .entry
941 GSYM($$remU)
942 ldo -1(arg1),temp /* is there at most one bit set ? */
943 and,= arg1,temp,r0 /* if not, don't use power of 2 */
944 b LREF(regular_seq)
945 addit,= 0,arg1,r0 /* trap on div by zero */
946 and arg0,temp,rmndr /* get the result for power of 2 */
947 MILLIRETN
948 LSYM(regular_seq)
949 comib,>=,n 0,arg1,LREF(special_case)
950 subi 0,arg1,rmndr /* clear carry, negate the divisor */
951 ds r0,rmndr,r0 /* set V-bit to 1 */
952 add arg0,arg0,temp /* shift msb bit into carry */
953 ds r0,arg1,rmndr /* 1st divide step, if no carry */
954 addc temp,temp,temp /* shift temp with/into carry */
955 ds rmndr,arg1,rmndr /* 2nd divide step */
956 addc temp,temp,temp /* shift temp with/into carry */
957 ds rmndr,arg1,rmndr /* 3rd divide step */
958 addc temp,temp,temp /* shift temp with/into carry */
959 ds rmndr,arg1,rmndr /* 4th divide step */
960 addc temp,temp,temp /* shift temp with/into carry */
961 ds rmndr,arg1,rmndr /* 5th divide step */
962 addc temp,temp,temp /* shift temp with/into carry */
963 ds rmndr,arg1,rmndr /* 6th divide step */
964 addc temp,temp,temp /* shift temp with/into carry */
965 ds rmndr,arg1,rmndr /* 7th divide step */
966 addc temp,temp,temp /* shift temp with/into carry */
967 ds rmndr,arg1,rmndr /* 8th divide step */
968 addc temp,temp,temp /* shift temp with/into carry */
969 ds rmndr,arg1,rmndr /* 9th divide step */
970 addc temp,temp,temp /* shift temp with/into carry */
971 ds rmndr,arg1,rmndr /* 10th divide step */
972 addc temp,temp,temp /* shift temp with/into carry */
973 ds rmndr,arg1,rmndr /* 11th divide step */
974 addc temp,temp,temp /* shift temp with/into carry */
975 ds rmndr,arg1,rmndr /* 12th divide step */
976 addc temp,temp,temp /* shift temp with/into carry */
977 ds rmndr,arg1,rmndr /* 13th divide step */
978 addc temp,temp,temp /* shift temp with/into carry */
979 ds rmndr,arg1,rmndr /* 14th divide step */
980 addc temp,temp,temp /* shift temp with/into carry */
981 ds rmndr,arg1,rmndr /* 15th divide step */
982 addc temp,temp,temp /* shift temp with/into carry */
983 ds rmndr,arg1,rmndr /* 16th divide step */
984 addc temp,temp,temp /* shift temp with/into carry */
985 ds rmndr,arg1,rmndr /* 17th divide step */
986 addc temp,temp,temp /* shift temp with/into carry */
987 ds rmndr,arg1,rmndr /* 18th divide step */
988 addc temp,temp,temp /* shift temp with/into carry */
989 ds rmndr,arg1,rmndr /* 19th divide step */
990 addc temp,temp,temp /* shift temp with/into carry */
991 ds rmndr,arg1,rmndr /* 20th divide step */
992 addc temp,temp,temp /* shift temp with/into carry */
993 ds rmndr,arg1,rmndr /* 21st divide step */
994 addc temp,temp,temp /* shift temp with/into carry */
995 ds rmndr,arg1,rmndr /* 22nd divide step */
996 addc temp,temp,temp /* shift temp with/into carry */
997 ds rmndr,arg1,rmndr /* 23rd divide step */
998 addc temp,temp,temp /* shift temp with/into carry */
999 ds rmndr,arg1,rmndr /* 24th divide step */
1000 addc temp,temp,temp /* shift temp with/into carry */
1001 ds rmndr,arg1,rmndr /* 25th divide step */
1002 addc temp,temp,temp /* shift temp with/into carry */
1003 ds rmndr,arg1,rmndr /* 26th divide step */
1004 addc temp,temp,temp /* shift temp with/into carry */
1005 ds rmndr,arg1,rmndr /* 27th divide step */
1006 addc temp,temp,temp /* shift temp with/into carry */
1007 ds rmndr,arg1,rmndr /* 28th divide step */
1008 addc temp,temp,temp /* shift temp with/into carry */
1009 ds rmndr,arg1,rmndr /* 29th divide step */
1010 addc temp,temp,temp /* shift temp with/into carry */
1011 ds rmndr,arg1,rmndr /* 30th divide step */
1012 addc temp,temp,temp /* shift temp with/into carry */
1013 ds rmndr,arg1,rmndr /* 31st divide step */
1014 addc temp,temp,temp /* shift temp with/into carry */
1015 ds rmndr,arg1,rmndr /* 32nd divide step, */
1016 comiclr,<= 0,rmndr,r0
1017 add rmndr,arg1,rmndr /* correction */
1018 MILLIRETN
1019 nop
1021 /* Putting >= on the last DS and deleting COMICLR does not work! */
1022 LSYM(special_case)
1023 sub,>>= arg0,arg1,rmndr
1024 copy arg0,rmndr
1025 MILLIRETN
1026 nop
1027 .exit
1028 .procend
1029 .cfi_endproc
1030 .end
1031 #endif
1033 #ifdef L_div_const
1034 /* ROUTINE: $$divI_2
1035 . $$divI_3 $$divU_3
1036 . $$divI_4
1037 . $$divI_5 $$divU_5
1038 . $$divI_6 $$divU_6
1039 . $$divI_7 $$divU_7
1040 . $$divI_8
1041 . $$divI_9 $$divU_9
1042 . $$divI_10 $$divU_10
1043 .
1044 . $$divI_12 $$divU_12
1045 .
1046 . $$divI_14 $$divU_14
1047 . $$divI_15 $$divU_15
1048 . $$divI_16
1049 . $$divI_17 $$divU_17
1050 .
1051 . Divide by selected constants for single precision binary integers.
1053 INPUT REGISTERS:
1054 . arg0 == dividend
1055 . mrp == return pc
1056 . sr0 == return space when called externally
1058 OUTPUT REGISTERS:
1059 . arg0 = undefined
1060 . arg1 = undefined
1061 . ret1 = quotient
1063 OTHER REGISTERS AFFECTED:
1064 . r1 = undefined
1066 SIDE EFFECTS:
1067 . Causes a trap under the following conditions: NONE
1068 . Changes memory at the following places: NONE
1070 PERMISSIBLE CONTEXT:
1071 . Unwindable.
1072 . Does not create a stack frame.
1073 . Suitable for internal or external millicode.
1074 . Assumes the special millicode register conventions.
1076 DISCUSSION:
1077 . Calls other millicode routines using mrp: NONE
1078 . Calls other millicode routines: NONE */
1081 /* TRUNCATED DIVISION BY SMALL INTEGERS
1083 We are interested in q(x) = floor(x/y), where x >= 0 and y > 0
1084 (with y fixed).
1086 Let a = floor(z/y), for some choice of z. Note that z will be
1087 chosen so that division by z is cheap.
1089 Let r be the remainder(z/y). In other words, r = z - ay.
1091 Now, our method is to choose a value for b such that
1093 q'(x) = floor((ax+b)/z)
1095 is equal to q(x) over as large a range of x as possible. If the
1096 two are equal over a sufficiently large range, and if it is easy to
1097 form the product (ax), and it is easy to divide by z, then we can
1098 perform the division much faster than the general division algorithm.
1100 So, we want the following to be true:
1102 . For x in the following range:
1103 .
1104 . ky <= x < (k+1)y
1105 .
1106 . implies that
1107 .
1108 . k <= (ax+b)/z < (k+1)
1110 We want to determine b such that this is true for all k in the
1111 range {0..K} for some maximum K.
1113 Since (ax+b) is an increasing function of x, we can take each
1114 bound separately to determine the "best" value for b.
1116 (ax+b)/z < (k+1) implies
1118 (a((k+1)y-1)+b < (k+1)z implies
1120 b < a + (k+1)(z-ay) implies
1122 b < a + (k+1)r
1124 This needs to be true for all k in the range {0..K}. In
1125 particular, it is true for k = 0 and this leads to a maximum
1126 acceptable value for b.
1128 b < a+r or b <= a+r-1
1130 Taking the other bound, we have
1132 k <= (ax+b)/z implies
1134 k <= (aky+b)/z implies
1136 k(z-ay) <= b implies
1138 kr <= b
1140 Clearly, the largest range for k will be achieved by maximizing b,
1141 when r is not zero. When r is zero, then the simplest choice for b
1142 is 0. When r is not 0, set
1144 . b = a+r-1
1146 Now, by construction, q'(x) = floor((ax+b)/z) = q(x) = floor(x/y)
1147 for all x in the range:
1149 . 0 <= x < (K+1)y
1151 We need to determine what K is. Of our two bounds,
1153 . b < a+(k+1)r is satisfied for all k >= 0, by construction.
1155 The other bound is
1157 . kr <= b
1159 This is always true if r = 0. If r is not 0 (the usual case), then
1160 K = floor((a+r-1)/r), is the maximum value for k.
1162 Therefore, the formula q'(x) = floor((ax+b)/z) yields the correct
1163 answer for q(x) = floor(x/y) when x is in the range
1165 (0,(K+1)y-1) K = floor((a+r-1)/r)
1167 To be most useful, we want (K+1)y-1 = (max x) >= 2**32-1 so that
1168 the formula for q'(x) yields the correct value of q(x) for all x
1169 representable by a single word in HPPA.
1171 We are also constrained in that computing the product (ax), adding
1172 b, and dividing by z must all be done quickly, otherwise we will be
1173 better off going through the general algorithm using the DS
1174 instruction, which uses approximately 70 cycles.
1176 For each y, there is a choice of z which satisfies the constraints
1177 for (K+1)y >= 2**32. We may not, however, be able to satisfy the
1178 timing constraints for arbitrary y. It seems that z being equal to
1179 a power of 2 or a power of 2 minus 1 is as good as we can do, since
1180 it minimizes the time to do division by z. We want the choice of z
1181 to also result in a value for (a) that minimizes the computation of
1182 the product (ax). This is best achieved if (a) has a regular bit
1183 pattern (so the multiplication can be done with shifts and adds).
1184 The value of (a) also needs to be less than 2**32 so the product is
1185 always guaranteed to fit in 2 words.
1187 In actual practice, the following should be done:
1189 1) For negative x, you should take the absolute value and remember
1190 . the fact so that the result can be negated. This obviously does
1191 . not apply in the unsigned case.
1192 2) For even y, you should factor out the power of 2 that divides y
1193 . and divide x by it. You can then proceed by dividing by the
1194 . odd factor of y.
1196 Here is a table of some odd values of y, and corresponding choices
1197 for z which are "good".
1199 y z r a (hex) max x (hex)
1201 3 2**32 1 55555555 100000001
1202 5 2**32 1 33333333 100000003
1203 7 2**24-1 0 249249 (infinite)
1204 9 2**24-1 0 1c71c7 (infinite)
1205 11 2**20-1 0 1745d (infinite)
1206 13 2**24-1 0 13b13b (infinite)
1207 15 2**32 1 11111111 10000000d
1208 17 2**32 1 f0f0f0f 10000000f
1210 If r is 1, then b = a+r-1 = a. This simplifies the computation
1211 of (ax+b), since you can compute (x+1)(a) instead. If r is 0,
1212 then b = 0 is ok to use which simplifies (ax+b).
1214 The bit patterns for 55555555, 33333333, and 11111111 are obviously
1215 very regular. The bit patterns for the other values of a above are:
1217 y (hex) (binary)
1219 7 249249 001001001001001001001001 << regular >>
1220 9 1c71c7 000111000111000111000111 << regular >>
1221 11 1745d 000000010111010001011101 << irregular >>
1222 13 13b13b 000100111011000100111011 << irregular >>
1224 The bit patterns for (a) corresponding to (y) of 11 and 13 may be
1225 too irregular to warrant using this method.
1227 When z is a power of 2 minus 1, then the division by z is slightly
1228 more complicated, involving an iterative solution.
1230 The code presented here solves division by 1 through 17, except for
1231 11 and 13. There are algorithms for both signed and unsigned
1232 quantities given.
1234 TIMINGS (cycles)
1236 divisor positive negative unsigned
1238 . 1 2 2 2
1239 . 2 4 4 2
1240 . 3 19 21 19
1241 . 4 4 4 2
1242 . 5 18 22 19
1243 . 6 19 22 19
1244 . 8 4 4 2
1245 . 10 18 19 17
1246 . 12 18 20 18
1247 . 15 16 18 16
1248 . 16 4 4 2
1249 . 17 16 18 16
1251 Now, the algorithm for 7, 9, and 14 is an iterative one. That is,
1252 a loop body is executed until the tentative quotient is 0. The
1253 number of times the loop body is executed varies depending on the
1254 dividend, but is never more than two times. If the dividend is
1255 less than the divisor, then the loop body is not executed at all.
1256 Each iteration adds 4 cycles to the timings.
1258 divisor positive negative unsigned
1260 . 7 19+4n 20+4n 20+4n n = number of iterations
1261 . 9 21+4n 22+4n 21+4n
1262 . 14 21+4n 22+4n 20+4n
1264 To give an idea of how the number of iterations varies, here is a
1265 table of dividend versus number of iterations when dividing by 7.
1267 smallest largest required
1268 dividend dividend iterations
1270 . 0 6 0
1271 . 7 0x6ffffff 1
1272 0x1000006 0xffffffff 2
1274 There is some overlap in the range of numbers requiring 1 and 2
1275 iterations. */
1277 RDEFINE(t2,r1)
1278 RDEFINE(x2,arg0) /* r26 */
1279 RDEFINE(t1,arg1) /* r25 */
1280 RDEFINE(x1,ret1) /* r29 */
1282 SUBSPA_MILLI_DIV
1283 ATTR_MILLI
1285 .proc
1286 .callinfo millicode
1287 .entry
1288 /* NONE of these routines require a stack frame
1289 ALL of these routines are unwindable from millicode */
1291 GSYM($$divide_by_constant)
1292 .export $$divide_by_constant,millicode
1293 /* Provides a "nice" label for the code covered by the unwind descriptor
1294 for things like gprof. */
1296 /* DIVISION BY 2 (shift by 1) */
1297 GSYM($$divI_2)
1298 .export $$divI_2,millicode
1299 comclr,>= arg0,0,0
1300 addi 1,arg0,arg0
1301 MILLIRET
1302 extrs arg0,30,31,ret1
1305 /* DIVISION BY 4 (shift by 2) */
1306 GSYM($$divI_4)
1307 .export $$divI_4,millicode
1308 comclr,>= arg0,0,0
1309 addi 3,arg0,arg0
1310 MILLIRET
1311 extrs arg0,29,30,ret1
1314 /* DIVISION BY 8 (shift by 3) */
1315 GSYM($$divI_8)
1316 .export $$divI_8,millicode
1317 comclr,>= arg0,0,0
1318 addi 7,arg0,arg0
1319 MILLIRET
1320 extrs arg0,28,29,ret1
1322 /* DIVISION BY 16 (shift by 4) */
1323 GSYM($$divI_16)
1324 .export $$divI_16,millicode
1325 comclr,>= arg0,0,0
1326 addi 15,arg0,arg0
1327 MILLIRET
1328 extrs arg0,27,28,ret1
1330 /****************************************************************************
1331 *
1332 * DIVISION BY DIVISORS OF FFFFFFFF, and powers of 2 times these
1333 *
1334 * includes 3,5,15,17 and also 6,10,12
1335 *
1336 ****************************************************************************/
1338 /* DIVISION BY 3 (use z = 2**32; a = 55555555) */
1340 GSYM($$divI_3)
1341 .export $$divI_3,millicode
1342 comb,<,N x2,0,LREF(neg3)
1344 addi 1,x2,x2 /* this cannot overflow */
1345 extru x2,1,2,x1 /* multiply by 5 to get started */
1346 sh2add x2,x2,x2
1347 b LREF(pos)
1348 addc x1,0,x1
1350 LSYM(neg3)
1351 subi 1,x2,x2 /* this cannot overflow */
1352 extru x2,1,2,x1 /* multiply by 5 to get started */
1353 sh2add x2,x2,x2
1354 b LREF(neg)
1355 addc x1,0,x1
1357 GSYM($$divU_3)
1358 .export $$divU_3,millicode
1359 addi 1,x2,x2 /* this CAN overflow */
1360 addc 0,0,x1
1361 shd x1,x2,30,t1 /* multiply by 5 to get started */
1362 sh2add x2,x2,x2
1363 b LREF(pos)
1364 addc x1,t1,x1
1366 /* DIVISION BY 5 (use z = 2**32; a = 33333333) */
1368 GSYM($$divI_5)
1369 .export $$divI_5,millicode
1370 comb,<,N x2,0,LREF(neg5)
1372 addi 3,x2,t1 /* this cannot overflow */
1373 sh1add x2,t1,x2 /* multiply by 3 to get started */
1374 b LREF(pos)
1375 addc 0,0,x1
1377 LSYM(neg5)
1378 sub 0,x2,x2 /* negate x2 */
1379 addi 1,x2,x2 /* this cannot overflow */
1380 shd 0,x2,31,x1 /* get top bit (can be 1) */
1381 sh1add x2,x2,x2 /* multiply by 3 to get started */
1382 b LREF(neg)
1383 addc x1,0,x1
1385 GSYM($$divU_5)
1386 .export $$divU_5,millicode
1387 addi 1,x2,x2 /* this CAN overflow */
1388 addc 0,0,x1
1389 shd x1,x2,31,t1 /* multiply by 3 to get started */
1390 sh1add x2,x2,x2
1391 b LREF(pos)
1392 addc t1,x1,x1
1394 /* DIVISION BY 6 (shift to divide by 2 then divide by 3) */
1395 GSYM($$divI_6)
1396 .export $$divI_6,millicode
1397 comb,<,N x2,0,LREF(neg6)
1398 extru x2,30,31,x2 /* divide by 2 */
1399 addi 5,x2,t1 /* compute 5*(x2+1) = 5*x2+5 */
1400 sh2add x2,t1,x2 /* multiply by 5 to get started */
1401 b LREF(pos)
1402 addc 0,0,x1
1404 LSYM(neg6)
1405 subi 2,x2,x2 /* negate, divide by 2, and add 1 */
1406 /* negation and adding 1 are done */
1407 /* at the same time by the SUBI */
1408 extru x2,30,31,x2
1409 shd 0,x2,30,x1
1410 sh2add x2,x2,x2 /* multiply by 5 to get started */
1411 b LREF(neg)
1412 addc x1,0,x1
1414 GSYM($$divU_6)
1415 .export $$divU_6,millicode
1416 extru x2,30,31,x2 /* divide by 2 */
1417 addi 1,x2,x2 /* cannot carry */
1418 shd 0,x2,30,x1 /* multiply by 5 to get started */
1419 sh2add x2,x2,x2
1420 b LREF(pos)
1421 addc x1,0,x1
1423 /* DIVISION BY 10 (shift to divide by 2 then divide by 5) */
1424 GSYM($$divU_10)
1425 .export $$divU_10,millicode
1426 extru x2,30,31,x2 /* divide by 2 */
1427 addi 3,x2,t1 /* compute 3*(x2+1) = (3*x2)+3 */
1428 sh1add x2,t1,x2 /* multiply by 3 to get started */
1429 addc 0,0,x1
1430 LSYM(pos)
1431 shd x1,x2,28,t1 /* multiply by 0x11 */
1432 shd x2,0,28,t2
1433 add x2,t2,x2
1434 addc x1,t1,x1
1435 LSYM(pos_for_17)
1436 shd x1,x2,24,t1 /* multiply by 0x101 */
1437 shd x2,0,24,t2
1438 add x2,t2,x2
1439 addc x1,t1,x1
1441 shd x1,x2,16,t1 /* multiply by 0x10001 */
1442 shd x2,0,16,t2
1443 add x2,t2,x2
1444 MILLIRET
1445 addc x1,t1,x1
1447 GSYM($$divI_10)
1448 .export $$divI_10,millicode
1449 comb,< x2,0,LREF(neg10)
1450 copy 0,x1
1451 extru x2,30,31,x2 /* divide by 2 */
1452 addib,TR 1,x2,LREF(pos) /* add 1 (cannot overflow) */
1453 sh1add x2,x2,x2 /* multiply by 3 to get started */
1455 LSYM(neg10)
1456 subi 2,x2,x2 /* negate, divide by 2, and add 1 */
1457 /* negation and adding 1 are done */
1458 /* at the same time by the SUBI */
1459 extru x2,30,31,x2
1460 sh1add x2,x2,x2 /* multiply by 3 to get started */
1461 LSYM(neg)
1462 shd x1,x2,28,t1 /* multiply by 0x11 */
1463 shd x2,0,28,t2
1464 add x2,t2,x2
1465 addc x1,t1,x1
1466 LSYM(neg_for_17)
1467 shd x1,x2,24,t1 /* multiply by 0x101 */
1468 shd x2,0,24,t2
1469 add x2,t2,x2
1470 addc x1,t1,x1
1472 shd x1,x2,16,t1 /* multiply by 0x10001 */
1473 shd x2,0,16,t2
1474 add x2,t2,x2
1475 addc x1,t1,x1
1476 MILLIRET
1477 sub 0,x1,x1
1479 /* DIVISION BY 12 (shift to divide by 4 then divide by 3) */
1480 GSYM($$divI_12)
1481 .export $$divI_12,millicode
1482 comb,< x2,0,LREF(neg12)
1483 copy 0,x1
1484 extru x2,29,30,x2 /* divide by 4 */
1485 addib,tr 1,x2,LREF(pos) /* compute 5*(x2+1) = 5*x2+5 */
1486 sh2add x2,x2,x2 /* multiply by 5 to get started */
1488 LSYM(neg12)
1489 subi 4,x2,x2 /* negate, divide by 4, and add 1 */
1490 /* negation and adding 1 are done */
1491 /* at the same time by the SUBI */
1492 extru x2,29,30,x2
1493 b LREF(neg)
1494 sh2add x2,x2,x2 /* multiply by 5 to get started */
1496 GSYM($$divU_12)
1497 .export $$divU_12,millicode
1498 extru x2,29,30,x2 /* divide by 4 */
1499 addi 5,x2,t1 /* cannot carry */
1500 sh2add x2,t1,x2 /* multiply by 5 to get started */
1501 b LREF(pos)
1502 addc 0,0,x1
1504 /* DIVISION BY 15 (use z = 2**32; a = 11111111) */
1505 GSYM($$divI_15)
1506 .export $$divI_15,millicode
1507 comb,< x2,0,LREF(neg15)
1508 copy 0,x1
1509 addib,tr 1,x2,LREF(pos)+4
1510 shd x1,x2,28,t1
1512 LSYM(neg15)
1513 b LREF(neg)
1514 subi 1,x2,x2
1516 GSYM($$divU_15)
1517 .export $$divU_15,millicode
1518 addi 1,x2,x2 /* this CAN overflow */
1519 b LREF(pos)
1520 addc 0,0,x1
1522 /* DIVISION BY 17 (use z = 2**32; a = f0f0f0f) */
1523 GSYM($$divI_17)
1524 .export $$divI_17,millicode
1525 comb,<,n x2,0,LREF(neg17)
1526 addi 1,x2,x2 /* this cannot overflow */
1527 shd 0,x2,28,t1 /* multiply by 0xf to get started */
1528 shd x2,0,28,t2
1529 sub t2,x2,x2
1530 b LREF(pos_for_17)
1531 subb t1,0,x1
1533 LSYM(neg17)
1534 subi 1,x2,x2 /* this cannot overflow */
1535 shd 0,x2,28,t1 /* multiply by 0xf to get started */
1536 shd x2,0,28,t2
1537 sub t2,x2,x2
1538 b LREF(neg_for_17)
1539 subb t1,0,x1
1541 GSYM($$divU_17)
1542 .export $$divU_17,millicode
1543 addi 1,x2,x2 /* this CAN overflow */
1544 addc 0,0,x1
1545 shd x1,x2,28,t1 /* multiply by 0xf to get started */
1546 LSYM(u17)
1547 shd x2,0,28,t2
1548 sub t2,x2,x2
1549 b LREF(pos_for_17)
1550 subb t1,x1,x1
1553 /* DIVISION BY DIVISORS OF FFFFFF, and powers of 2 times these
1554 includes 7,9 and also 14
1557 z = 2**24-1
1558 r = z mod x = 0
1560 so choose b = 0
1562 Also, in order to divide by z = 2**24-1, we approximate by dividing
1563 by (z+1) = 2**24 (which is easy), and then correcting.
1565 (ax) = (z+1)q' + r
1566 . = zq' + (q'+r)
1568 So to compute (ax)/z, compute q' = (ax)/(z+1) and r = (ax) mod (z+1)
1569 Then the true remainder of (ax)/z is (q'+r). Repeat the process
1570 with this new remainder, adding the tentative quotients together,
1571 until a tentative quotient is 0 (and then we are done). There is
1572 one last correction to be done. It is possible that (q'+r) = z.
1573 If so, then (q'+r)/(z+1) = 0 and it looks like we are done. But,
1574 in fact, we need to add 1 more to the quotient. Now, it turns
1575 out that this happens if and only if the original value x is
1576 an exact multiple of y. So, to avoid a three instruction test at
1577 the end, instead use 1 instruction to add 1 to x at the beginning. */
1579 /* DIVISION BY 7 (use z = 2**24-1; a = 249249) */
1580 GSYM($$divI_7)
1581 .export $$divI_7,millicode
1582 comb,<,n x2,0,LREF(neg7)
1583 LSYM(7)
1584 addi 1,x2,x2 /* cannot overflow */
1585 shd 0,x2,29,x1
1586 sh3add x2,x2,x2
1587 addc x1,0,x1
1588 LSYM(pos7)
1589 shd x1,x2,26,t1
1590 shd x2,0,26,t2
1591 add x2,t2,x2
1592 addc x1,t1,x1
1594 shd x1,x2,20,t1
1595 shd x2,0,20,t2
1596 add x2,t2,x2
1597 addc x1,t1,t1
1599 /* computed <t1,x2>. Now divide it by (2**24 - 1) */
1601 copy 0,x1
1602 shd,= t1,x2,24,t1 /* tentative quotient */
1603 LSYM(1)
1604 addb,tr t1,x1,LREF(2) /* add to previous quotient */
1605 extru x2,31,24,x2 /* new remainder (unadjusted) */
1607 MILLIRETN
1609 LSYM(2)
1610 addb,tr t1,x2,LREF(1) /* adjust remainder */
1611 extru,= x2,7,8,t1 /* new quotient */
1613 LSYM(neg7)
1614 subi 1,x2,x2 /* negate x2 and add 1 */
1615 LSYM(8)
1616 shd 0,x2,29,x1
1617 sh3add x2,x2,x2
1618 addc x1,0,x1
1620 LSYM(neg7_shift)
1621 shd x1,x2,26,t1
1622 shd x2,0,26,t2
1623 add x2,t2,x2
1624 addc x1,t1,x1
1626 shd x1,x2,20,t1
1627 shd x2,0,20,t2
1628 add x2,t2,x2
1629 addc x1,t1,t1
1631 /* computed <t1,x2>. Now divide it by (2**24 - 1) */
1633 copy 0,x1
1634 shd,= t1,x2,24,t1 /* tentative quotient */
1635 LSYM(3)
1636 addb,tr t1,x1,LREF(4) /* add to previous quotient */
1637 extru x2,31,24,x2 /* new remainder (unadjusted) */
1639 MILLIRET
1640 sub 0,x1,x1 /* negate result */
1642 LSYM(4)
1643 addb,tr t1,x2,LREF(3) /* adjust remainder */
1644 extru,= x2,7,8,t1 /* new quotient */
1646 GSYM($$divU_7)
1647 .export $$divU_7,millicode
1648 addi 1,x2,x2 /* can carry */
1649 addc 0,0,x1
1650 shd x1,x2,29,t1
1651 sh3add x2,x2,x2
1652 b LREF(pos7)
1653 addc t1,x1,x1
1655 /* DIVISION BY 9 (use z = 2**24-1; a = 1c71c7) */
1656 GSYM($$divI_9)
1657 .export $$divI_9,millicode
1658 comb,<,n x2,0,LREF(neg9)
1659 addi 1,x2,x2 /* cannot overflow */
1660 shd 0,x2,29,t1
1661 shd x2,0,29,t2
1662 sub t2,x2,x2
1663 b LREF(pos7)
1664 subb t1,0,x1
1666 LSYM(neg9)
1667 subi 1,x2,x2 /* negate and add 1 */
1668 shd 0,x2,29,t1
1669 shd x2,0,29,t2
1670 sub t2,x2,x2
1671 b LREF(neg7_shift)
1672 subb t1,0,x1
1674 GSYM($$divU_9)
1675 .export $$divU_9,millicode
1676 addi 1,x2,x2 /* can carry */
1677 addc 0,0,x1
1678 shd x1,x2,29,t1
1679 shd x2,0,29,t2
1680 sub t2,x2,x2
1681 b LREF(pos7)
1682 subb t1,x1,x1
1684 /* DIVISION BY 14 (shift to divide by 2 then divide by 7) */
1685 GSYM($$divI_14)
1686 .export $$divI_14,millicode
1687 comb,<,n x2,0,LREF(neg14)
1688 GSYM($$divU_14)
1689 .export $$divU_14,millicode
1690 b LREF(7) /* go to 7 case */
1691 extru x2,30,31,x2 /* divide by 2 */
1693 LSYM(neg14)
1694 subi 2,x2,x2 /* negate (and add 2) */
1695 b LREF(8)
1696 extru x2,30,31,x2 /* divide by 2 */
1697 .exit
1698 .procend
1699 .end
1700 #endif
1702 #ifdef L_mulI
1703 /* VERSION "@(#)$$mulI $ Revision: 12.4 $ $ Date: 94/03/17 17:18:51 $" */
1704 /******************************************************************************
1705 This routine is used on PA2.0 processors when gcc -mno-fpregs is used
1707 ROUTINE: $$mulI
1710 DESCRIPTION:
1712 $$mulI multiplies two single word integers, giving a single
1713 word result.
1716 INPUT REGISTERS:
1718 arg0 = Operand 1
1719 arg1 = Operand 2
1720 r31 == return pc
1721 sr0 == return space when called externally
1724 OUTPUT REGISTERS:
1726 arg0 = undefined
1727 arg1 = undefined
1728 ret1 = result
1730 OTHER REGISTERS AFFECTED:
1732 r1 = undefined
1734 SIDE EFFECTS:
1736 Causes a trap under the following conditions: NONE
1737 Changes memory at the following places: NONE
1739 PERMISSIBLE CONTEXT:
1741 Unwindable
1742 Does not create a stack frame
1743 Is usable for internal or external microcode
1745 DISCUSSION:
1747 Calls other millicode routines via mrp: NONE
1748 Calls other millicode routines: NONE
1750 ***************************************************************************/
1753 #define a0 %arg0
1754 #define a1 %arg1
1755 #define t0 %r1
1756 #define r %ret1
1758 #define a0__128a0 zdep a0,24,25,a0
1759 #define a0__256a0 zdep a0,23,24,a0
1760 #define a1_ne_0_b_l0 comb,<> a1,0,LREF(l0)
1761 #define a1_ne_0_b_l1 comb,<> a1,0,LREF(l1)
1762 #define a1_ne_0_b_l2 comb,<> a1,0,LREF(l2)
1763 #define b_n_ret_t0 b,n LREF(ret_t0)
1764 #define b_e_shift b LREF(e_shift)
1765 #define b_e_t0ma0 b LREF(e_t0ma0)
1766 #define b_e_t0 b LREF(e_t0)
1767 #define b_e_t0a0 b LREF(e_t0a0)
1768 #define b_e_t02a0 b LREF(e_t02a0)
1769 #define b_e_t04a0 b LREF(e_t04a0)
1770 #define b_e_2t0 b LREF(e_2t0)
1771 #define b_e_2t0a0 b LREF(e_2t0a0)
1772 #define b_e_2t04a0 b LREF(e2t04a0)
1773 #define b_e_3t0 b LREF(e_3t0)
1774 #define b_e_4t0 b LREF(e_4t0)
1775 #define b_e_4t0a0 b LREF(e_4t0a0)
1776 #define b_e_4t08a0 b LREF(e4t08a0)
1777 #define b_e_5t0 b LREF(e_5t0)
1778 #define b_e_8t0 b LREF(e_8t0)
1779 #define b_e_8t0a0 b LREF(e_8t0a0)
1780 #define r__r_a0 add r,a0,r
1781 #define r__r_2a0 sh1add a0,r,r
1782 #define r__r_4a0 sh2add a0,r,r
1783 #define r__r_8a0 sh3add a0,r,r
1784 #define r__r_t0 add r,t0,r
1785 #define r__r_2t0 sh1add t0,r,r
1786 #define r__r_4t0 sh2add t0,r,r
1787 #define r__r_8t0 sh3add t0,r,r
1788 #define t0__3a0 sh1add a0,a0,t0
1789 #define t0__4a0 sh2add a0,0,t0
1790 #define t0__5a0 sh2add a0,a0,t0
1791 #define t0__8a0 sh3add a0,0,t0
1792 #define t0__9a0 sh3add a0,a0,t0
1793 #define t0__16a0 zdep a0,27,28,t0
1794 #define t0__32a0 zdep a0,26,27,t0
1795 #define t0__64a0 zdep a0,25,26,t0
1796 #define t0__128a0 zdep a0,24,25,t0
1797 #define t0__t0ma0 sub t0,a0,t0
1798 #define t0__t0_a0 add t0,a0,t0
1799 #define t0__t0_2a0 sh1add a0,t0,t0
1800 #define t0__t0_4a0 sh2add a0,t0,t0
1801 #define t0__t0_8a0 sh3add a0,t0,t0
1802 #define t0__2t0_a0 sh1add t0,a0,t0
1803 #define t0__3t0 sh1add t0,t0,t0
1804 #define t0__4t0 sh2add t0,0,t0
1805 #define t0__4t0_a0 sh2add t0,a0,t0
1806 #define t0__5t0 sh2add t0,t0,t0
1807 #define t0__8t0 sh3add t0,0,t0
1808 #define t0__8t0_a0 sh3add t0,a0,t0
1809 #define t0__9t0 sh3add t0,t0,t0
1810 #define t0__16t0 zdep t0,27,28,t0
1811 #define t0__32t0 zdep t0,26,27,t0
1812 #define t0__256a0 zdep a0,23,24,t0
1815 SUBSPA_MILLI
1816 ATTR_MILLI
1817 .align 16
1818 .proc
1819 .callinfo millicode
1820 .export $$mulI,millicode
1821 GSYM($$mulI)
1822 combt,<<= a1,a0,LREF(l4) /* swap args if unsigned a1>a0 */
1823 copy 0,r /* zero out the result */
1824 xor a0,a1,a0 /* swap a0 & a1 using the */
1825 xor a0,a1,a1 /* old xor trick */
1826 xor a0,a1,a0
1827 LSYM(l4)
1828 combt,<= 0,a0,LREF(l3) /* if a0>=0 then proceed like unsigned */
1829 zdep a1,30,8,t0 /* t0 = (a1&0xff)<<1 ********* */
1830 sub,> 0,a1,t0 /* otherwise negate both and */
1831 combt,<=,n a0,t0,LREF(l2) /* swap back if |a0|<|a1| */
1832 sub 0,a0,a1
1833 movb,tr,n t0,a0,LREF(l2) /* 10th inst. */
1835 LSYM(l0) r__r_t0 /* add in this partial product */
1836 LSYM(l1) a0__256a0 /* a0 <<= 8 ****************** */
1837 LSYM(l2) zdep a1,30,8,t0 /* t0 = (a1&0xff)<<1 ********* */
1838 LSYM(l3) blr t0,0 /* case on these 8 bits ****** */
1839 extru a1,23,24,a1 /* a1 >>= 8 ****************** */
1841 /*16 insts before this. */
1842 /* a0 <<= 8 ************************** */
1843 LSYM(x0) a1_ne_0_b_l2 ! a0__256a0 ! MILLIRETN ! nop
1844 LSYM(x1) a1_ne_0_b_l1 ! r__r_a0 ! MILLIRETN ! nop
1845 LSYM(x2) a1_ne_0_b_l1 ! r__r_2a0 ! MILLIRETN ! nop
1846 LSYM(x3) a1_ne_0_b_l0 ! t0__3a0 ! MILLIRET ! r__r_t0
1847 LSYM(x4) a1_ne_0_b_l1 ! r__r_4a0 ! MILLIRETN ! nop
1848 LSYM(x5) a1_ne_0_b_l0 ! t0__5a0 ! MILLIRET ! r__r_t0
1849 LSYM(x6) t0__3a0 ! a1_ne_0_b_l1 ! r__r_2t0 ! MILLIRETN
1850 LSYM(x7) t0__3a0 ! a1_ne_0_b_l0 ! r__r_4a0 ! b_n_ret_t0
1851 LSYM(x8) a1_ne_0_b_l1 ! r__r_8a0 ! MILLIRETN ! nop
1852 LSYM(x9) a1_ne_0_b_l0 ! t0__9a0 ! MILLIRET ! r__r_t0
1853 LSYM(x10) t0__5a0 ! a1_ne_0_b_l1 ! r__r_2t0 ! MILLIRETN
1854 LSYM(x11) t0__3a0 ! a1_ne_0_b_l0 ! r__r_8a0 ! b_n_ret_t0
1855 LSYM(x12) t0__3a0 ! a1_ne_0_b_l1 ! r__r_4t0 ! MILLIRETN
1856 LSYM(x13) t0__5a0 ! a1_ne_0_b_l0 ! r__r_8a0 ! b_n_ret_t0
1857 LSYM(x14) t0__3a0 ! t0__2t0_a0 ! b_e_shift ! r__r_2t0
1858 LSYM(x15) t0__5a0 ! a1_ne_0_b_l0 ! t0__3t0 ! b_n_ret_t0
1859 LSYM(x16) t0__16a0 ! a1_ne_0_b_l1 ! r__r_t0 ! MILLIRETN
1860 LSYM(x17) t0__9a0 ! a1_ne_0_b_l0 ! t0__t0_8a0 ! b_n_ret_t0
1861 LSYM(x18) t0__9a0 ! a1_ne_0_b_l1 ! r__r_2t0 ! MILLIRETN
1862 LSYM(x19) t0__9a0 ! a1_ne_0_b_l0 ! t0__2t0_a0 ! b_n_ret_t0
1863 LSYM(x20) t0__5a0 ! a1_ne_0_b_l1 ! r__r_4t0 ! MILLIRETN
1864 LSYM(x21) t0__5a0 ! a1_ne_0_b_l0 ! t0__4t0_a0 ! b_n_ret_t0
1865 LSYM(x22) t0__5a0 ! t0__2t0_a0 ! b_e_shift ! r__r_2t0
1866 LSYM(x23) t0__5a0 ! t0__2t0_a0 ! b_e_t0 ! t0__2t0_a0
1867 LSYM(x24) t0__3a0 ! a1_ne_0_b_l1 ! r__r_8t0 ! MILLIRETN
1868 LSYM(x25) t0__5a0 ! a1_ne_0_b_l0 ! t0__5t0 ! b_n_ret_t0
1869 LSYM(x26) t0__3a0 ! t0__4t0_a0 ! b_e_shift ! r__r_2t0
1870 LSYM(x27) t0__3a0 ! a1_ne_0_b_l0 ! t0__9t0 ! b_n_ret_t0
1871 LSYM(x28) t0__3a0 ! t0__2t0_a0 ! b_e_shift ! r__r_4t0
1872 LSYM(x29) t0__3a0 ! t0__2t0_a0 ! b_e_t0 ! t0__4t0_a0
1873 LSYM(x30) t0__5a0 ! t0__3t0 ! b_e_shift ! r__r_2t0
1874 LSYM(x31) t0__32a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
1875 LSYM(x32) t0__32a0 ! a1_ne_0_b_l1 ! r__r_t0 ! MILLIRETN
1876 LSYM(x33) t0__8a0 ! a1_ne_0_b_l0 ! t0__4t0_a0 ! b_n_ret_t0
1877 LSYM(x34) t0__16a0 ! t0__t0_a0 ! b_e_shift ! r__r_2t0
1878 LSYM(x35) t0__9a0 ! t0__3t0 ! b_e_t0 ! t0__t0_8a0
1879 LSYM(x36) t0__9a0 ! a1_ne_0_b_l1 ! r__r_4t0 ! MILLIRETN
1880 LSYM(x37) t0__9a0 ! a1_ne_0_b_l0 ! t0__4t0_a0 ! b_n_ret_t0
1881 LSYM(x38) t0__9a0 ! t0__2t0_a0 ! b_e_shift ! r__r_2t0
1882 LSYM(x39) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__2t0_a0
1883 LSYM(x40) t0__5a0 ! a1_ne_0_b_l1 ! r__r_8t0 ! MILLIRETN
1884 LSYM(x41) t0__5a0 ! a1_ne_0_b_l0 ! t0__8t0_a0 ! b_n_ret_t0
1885 LSYM(x42) t0__5a0 ! t0__4t0_a0 ! b_e_shift ! r__r_2t0
1886 LSYM(x43) t0__5a0 ! t0__4t0_a0 ! b_e_t0 ! t0__2t0_a0
1887 LSYM(x44) t0__5a0 ! t0__2t0_a0 ! b_e_shift ! r__r_4t0
1888 LSYM(x45) t0__9a0 ! a1_ne_0_b_l0 ! t0__5t0 ! b_n_ret_t0
1889 LSYM(x46) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__t0_a0
1890 LSYM(x47) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__t0_2a0
1891 LSYM(x48) t0__3a0 ! a1_ne_0_b_l0 ! t0__16t0 ! b_n_ret_t0
1892 LSYM(x49) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__t0_4a0
1893 LSYM(x50) t0__5a0 ! t0__5t0 ! b_e_shift ! r__r_2t0
1894 LSYM(x51) t0__9a0 ! t0__t0_8a0 ! b_e_t0 ! t0__3t0
1895 LSYM(x52) t0__3a0 ! t0__4t0_a0 ! b_e_shift ! r__r_4t0
1896 LSYM(x53) t0__3a0 ! t0__4t0_a0 ! b_e_t0 ! t0__4t0_a0
1897 LSYM(x54) t0__9a0 ! t0__3t0 ! b_e_shift ! r__r_2t0
1898 LSYM(x55) t0__9a0 ! t0__3t0 ! b_e_t0 ! t0__2t0_a0
1899 LSYM(x56) t0__3a0 ! t0__2t0_a0 ! b_e_shift ! r__r_8t0
1900 LSYM(x57) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__3t0
1901 LSYM(x58) t0__3a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__4t0_a0
1902 LSYM(x59) t0__9a0 ! t0__2t0_a0 ! b_e_t02a0 ! t0__3t0
1903 LSYM(x60) t0__5a0 ! t0__3t0 ! b_e_shift ! r__r_4t0
1904 LSYM(x61) t0__5a0 ! t0__3t0 ! b_e_t0 ! t0__4t0_a0
1905 LSYM(x62) t0__32a0 ! t0__t0ma0 ! b_e_shift ! r__r_2t0
1906 LSYM(x63) t0__64a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
1907 LSYM(x64) t0__64a0 ! a1_ne_0_b_l1 ! r__r_t0 ! MILLIRETN
1908 LSYM(x65) t0__8a0 ! a1_ne_0_b_l0 ! t0__8t0_a0 ! b_n_ret_t0
1909 LSYM(x66) t0__32a0 ! t0__t0_a0 ! b_e_shift ! r__r_2t0
1910 LSYM(x67) t0__8a0 ! t0__4t0_a0 ! b_e_t0 ! t0__2t0_a0
1911 LSYM(x68) t0__8a0 ! t0__2t0_a0 ! b_e_shift ! r__r_4t0
1912 LSYM(x69) t0__8a0 ! t0__2t0_a0 ! b_e_t0 ! t0__4t0_a0
1913 LSYM(x70) t0__64a0 ! t0__t0_4a0 ! b_e_t0 ! t0__t0_2a0
1914 LSYM(x71) t0__9a0 ! t0__8t0 ! b_e_t0 ! t0__t0ma0
1915 LSYM(x72) t0__9a0 ! a1_ne_0_b_l1 ! r__r_8t0 ! MILLIRETN
1916 LSYM(x73) t0__9a0 ! t0__8t0_a0 ! b_e_shift ! r__r_t0
1917 LSYM(x74) t0__9a0 ! t0__4t0_a0 ! b_e_shift ! r__r_2t0
1918 LSYM(x75) t0__9a0 ! t0__4t0_a0 ! b_e_t0 ! t0__2t0_a0
1919 LSYM(x76) t0__9a0 ! t0__2t0_a0 ! b_e_shift ! r__r_4t0
1920 LSYM(x77) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__4t0_a0
1921 LSYM(x78) t0__9a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__2t0_a0
1922 LSYM(x79) t0__16a0 ! t0__5t0 ! b_e_t0 ! t0__t0ma0
1923 LSYM(x80) t0__16a0 ! t0__5t0 ! b_e_shift ! r__r_t0
1924 LSYM(x81) t0__9a0 ! t0__9t0 ! b_e_shift ! r__r_t0
1925 LSYM(x82) t0__5a0 ! t0__8t0_a0 ! b_e_shift ! r__r_2t0
1926 LSYM(x83) t0__5a0 ! t0__8t0_a0 ! b_e_t0 ! t0__2t0_a0
1927 LSYM(x84) t0__5a0 ! t0__4t0_a0 ! b_e_shift ! r__r_4t0
1928 LSYM(x85) t0__8a0 ! t0__2t0_a0 ! b_e_t0 ! t0__5t0
1929 LSYM(x86) t0__5a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__2t0_a0
1930 LSYM(x87) t0__9a0 ! t0__9t0 ! b_e_t02a0 ! t0__t0_4a0
1931 LSYM(x88) t0__5a0 ! t0__2t0_a0 ! b_e_shift ! r__r_8t0
1932 LSYM(x89) t0__5a0 ! t0__2t0_a0 ! b_e_t0 ! t0__8t0_a0
1933 LSYM(x90) t0__9a0 ! t0__5t0 ! b_e_shift ! r__r_2t0
1934 LSYM(x91) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__2t0_a0
1935 LSYM(x92) t0__5a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__2t0_a0
1936 LSYM(x93) t0__32a0 ! t0__t0ma0 ! b_e_t0 ! t0__3t0
1937 LSYM(x94) t0__9a0 ! t0__5t0 ! b_e_2t0 ! t0__t0_2a0
1938 LSYM(x95) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__5t0
1939 LSYM(x96) t0__8a0 ! t0__3t0 ! b_e_shift ! r__r_4t0
1940 LSYM(x97) t0__8a0 ! t0__3t0 ! b_e_t0 ! t0__4t0_a0
1941 LSYM(x98) t0__32a0 ! t0__3t0 ! b_e_t0 ! t0__t0_2a0
1942 LSYM(x99) t0__8a0 ! t0__4t0_a0 ! b_e_t0 ! t0__3t0
1943 LSYM(x100) t0__5a0 ! t0__5t0 ! b_e_shift ! r__r_4t0
1944 LSYM(x101) t0__5a0 ! t0__5t0 ! b_e_t0 ! t0__4t0_a0
1945 LSYM(x102) t0__32a0 ! t0__t0_2a0 ! b_e_t0 ! t0__3t0
1946 LSYM(x103) t0__5a0 ! t0__5t0 ! b_e_t02a0 ! t0__4t0_a0
1947 LSYM(x104) t0__3a0 ! t0__4t0_a0 ! b_e_shift ! r__r_8t0
1948 LSYM(x105) t0__5a0 ! t0__4t0_a0 ! b_e_t0 ! t0__5t0
1949 LSYM(x106) t0__3a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__4t0_a0
1950 LSYM(x107) t0__9a0 ! t0__t0_4a0 ! b_e_t02a0 ! t0__8t0_a0
1951 LSYM(x108) t0__9a0 ! t0__3t0 ! b_e_shift ! r__r_4t0
1952 LSYM(x109) t0__9a0 ! t0__3t0 ! b_e_t0 ! t0__4t0_a0
1953 LSYM(x110) t0__9a0 ! t0__3t0 ! b_e_2t0 ! t0__2t0_a0
1954 LSYM(x111) t0__9a0 ! t0__4t0_a0 ! b_e_t0 ! t0__3t0
1955 LSYM(x112) t0__3a0 ! t0__2t0_a0 ! b_e_t0 ! t0__16t0
1956 LSYM(x113) t0__9a0 ! t0__4t0_a0 ! b_e_t02a0 ! t0__3t0
1957 LSYM(x114) t0__9a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__3t0
1958 LSYM(x115) t0__9a0 ! t0__2t0_a0 ! b_e_2t0a0 ! t0__3t0
1959 LSYM(x116) t0__3a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__4t0_a0
1960 LSYM(x117) t0__3a0 ! t0__4t0_a0 ! b_e_t0 ! t0__9t0
1961 LSYM(x118) t0__3a0 ! t0__4t0_a0 ! b_e_t0a0 ! t0__9t0
1962 LSYM(x119) t0__3a0 ! t0__4t0_a0 ! b_e_t02a0 ! t0__9t0
1963 LSYM(x120) t0__5a0 ! t0__3t0 ! b_e_shift ! r__r_8t0
1964 LSYM(x121) t0__5a0 ! t0__3t0 ! b_e_t0 ! t0__8t0_a0
1965 LSYM(x122) t0__5a0 ! t0__3t0 ! b_e_2t0 ! t0__4t0_a0
1966 LSYM(x123) t0__5a0 ! t0__8t0_a0 ! b_e_t0 ! t0__3t0
1967 LSYM(x124) t0__32a0 ! t0__t0ma0 ! b_e_shift ! r__r_4t0
1968 LSYM(x125) t0__5a0 ! t0__5t0 ! b_e_t0 ! t0__5t0
1969 LSYM(x126) t0__64a0 ! t0__t0ma0 ! b_e_shift ! r__r_2t0
1970 LSYM(x127) t0__128a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
1971 LSYM(x128) t0__128a0 ! a1_ne_0_b_l1 ! r__r_t0 ! MILLIRETN
1972 LSYM(x129) t0__128a0 ! a1_ne_0_b_l0 ! t0__t0_a0 ! b_n_ret_t0
1973 LSYM(x130) t0__64a0 ! t0__t0_a0 ! b_e_shift ! r__r_2t0
1974 LSYM(x131) t0__8a0 ! t0__8t0_a0 ! b_e_t0 ! t0__2t0_a0
1975 LSYM(x132) t0__8a0 ! t0__4t0_a0 ! b_e_shift ! r__r_4t0
1976 LSYM(x133) t0__8a0 ! t0__4t0_a0 ! b_e_t0 ! t0__4t0_a0
1977 LSYM(x134) t0__8a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__2t0_a0
1978 LSYM(x135) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__3t0
1979 LSYM(x136) t0__8a0 ! t0__2t0_a0 ! b_e_shift ! r__r_8t0
1980 LSYM(x137) t0__8a0 ! t0__2t0_a0 ! b_e_t0 ! t0__8t0_a0
1981 LSYM(x138) t0__8a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__4t0_a0
1982 LSYM(x139) t0__8a0 ! t0__2t0_a0 ! b_e_2t0a0 ! t0__4t0_a0
1983 LSYM(x140) t0__3a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__5t0
1984 LSYM(x141) t0__8a0 ! t0__2t0_a0 ! b_e_4t0a0 ! t0__2t0_a0
1985 LSYM(x142) t0__9a0 ! t0__8t0 ! b_e_2t0 ! t0__t0ma0
1986 LSYM(x143) t0__16a0 ! t0__9t0 ! b_e_t0 ! t0__t0ma0
1987 LSYM(x144) t0__9a0 ! t0__8t0 ! b_e_shift ! r__r_2t0
1988 LSYM(x145) t0__9a0 ! t0__8t0 ! b_e_t0 ! t0__2t0_a0
1989 LSYM(x146) t0__9a0 ! t0__8t0_a0 ! b_e_shift ! r__r_2t0
1990 LSYM(x147) t0__9a0 ! t0__8t0_a0 ! b_e_t0 ! t0__2t0_a0
1991 LSYM(x148) t0__9a0 ! t0__4t0_a0 ! b_e_shift ! r__r_4t0
1992 LSYM(x149) t0__9a0 ! t0__4t0_a0 ! b_e_t0 ! t0__4t0_a0
1993 LSYM(x150) t0__9a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__2t0_a0
1994 LSYM(x151) t0__9a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__2t0_a0
1995 LSYM(x152) t0__9a0 ! t0__2t0_a0 ! b_e_shift ! r__r_8t0
1996 LSYM(x153) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__8t0_a0
1997 LSYM(x154) t0__9a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__4t0_a0
1998 LSYM(x155) t0__32a0 ! t0__t0ma0 ! b_e_t0 ! t0__5t0
1999 LSYM(x156) t0__9a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__2t0_a0
2000 LSYM(x157) t0__32a0 ! t0__t0ma0 ! b_e_t02a0 ! t0__5t0
2001 LSYM(x158) t0__16a0 ! t0__5t0 ! b_e_2t0 ! t0__t0ma0
2002 LSYM(x159) t0__32a0 ! t0__5t0 ! b_e_t0 ! t0__t0ma0
2003 LSYM(x160) t0__5a0 ! t0__4t0 ! b_e_shift ! r__r_8t0
2004 LSYM(x161) t0__8a0 ! t0__5t0 ! b_e_t0 ! t0__4t0_a0
2005 LSYM(x162) t0__9a0 ! t0__9t0 ! b_e_shift ! r__r_2t0
2006 LSYM(x163) t0__9a0 ! t0__9t0 ! b_e_t0 ! t0__2t0_a0
2007 LSYM(x164) t0__5a0 ! t0__8t0_a0 ! b_e_shift ! r__r_4t0
2008 LSYM(x165) t0__8a0 ! t0__4t0_a0 ! b_e_t0 ! t0__5t0
2009 LSYM(x166) t0__5a0 ! t0__8t0_a0 ! b_e_2t0 ! t0__2t0_a0
2010 LSYM(x167) t0__5a0 ! t0__8t0_a0 ! b_e_2t0a0 ! t0__2t0_a0
2011 LSYM(x168) t0__5a0 ! t0__4t0_a0 ! b_e_shift ! r__r_8t0
2012 LSYM(x169) t0__5a0 ! t0__4t0_a0 ! b_e_t0 ! t0__8t0_a0
2013 LSYM(x170) t0__32a0 ! t0__t0_2a0 ! b_e_t0 ! t0__5t0
2014 LSYM(x171) t0__9a0 ! t0__2t0_a0 ! b_e_t0 ! t0__9t0
2015 LSYM(x172) t0__5a0 ! t0__4t0_a0 ! b_e_4t0 ! t0__2t0_a0
2016 LSYM(x173) t0__9a0 ! t0__2t0_a0 ! b_e_t02a0 ! t0__9t0
2017 LSYM(x174) t0__32a0 ! t0__t0_2a0 ! b_e_t04a0 ! t0__5t0
2018 LSYM(x175) t0__8a0 ! t0__2t0_a0 ! b_e_5t0 ! t0__2t0_a0
2019 LSYM(x176) t0__5a0 ! t0__4t0_a0 ! b_e_8t0 ! t0__t0_a0
2020 LSYM(x177) t0__5a0 ! t0__4t0_a0 ! b_e_8t0a0 ! t0__t0_a0
2021 LSYM(x178) t0__5a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__8t0_a0
2022 LSYM(x179) t0__5a0 ! t0__2t0_a0 ! b_e_2t0a0 ! t0__8t0_a0
2023 LSYM(x180) t0__9a0 ! t0__5t0 ! b_e_shift ! r__r_4t0
2024 LSYM(x181) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__4t0_a0
2025 LSYM(x182) t0__9a0 ! t0__5t0 ! b_e_2t0 ! t0__2t0_a0
2026 LSYM(x183) t0__9a0 ! t0__5t0 ! b_e_2t0a0 ! t0__2t0_a0
2027 LSYM(x184) t0__5a0 ! t0__9t0 ! b_e_4t0 ! t0__t0_a0
2028 LSYM(x185) t0__9a0 ! t0__4t0_a0 ! b_e_t0 ! t0__5t0
2029 LSYM(x186) t0__32a0 ! t0__t0ma0 ! b_e_2t0 ! t0__3t0
2030 LSYM(x187) t0__9a0 ! t0__4t0_a0 ! b_e_t02a0 ! t0__5t0
2031 LSYM(x188) t0__9a0 ! t0__5t0 ! b_e_4t0 ! t0__t0_2a0
2032 LSYM(x189) t0__5a0 ! t0__4t0_a0 ! b_e_t0 ! t0__9t0
2033 LSYM(x190) t0__9a0 ! t0__2t0_a0 ! b_e_2t0 ! t0__5t0
2034 LSYM(x191) t0__64a0 ! t0__3t0 ! b_e_t0 ! t0__t0ma0
2035 LSYM(x192) t0__8a0 ! t0__3t0 ! b_e_shift ! r__r_8t0
2036 LSYM(x193) t0__8a0 ! t0__3t0 ! b_e_t0 ! t0__8t0_a0
2037 LSYM(x194) t0__8a0 ! t0__3t0 ! b_e_2t0 ! t0__4t0_a0
2038 LSYM(x195) t0__8a0 ! t0__8t0_a0 ! b_e_t0 ! t0__3t0
2039 LSYM(x196) t0__8a0 ! t0__3t0 ! b_e_4t0 ! t0__2t0_a0
2040 LSYM(x197) t0__8a0 ! t0__3t0 ! b_e_4t0a0 ! t0__2t0_a0
2041 LSYM(x198) t0__64a0 ! t0__t0_2a0 ! b_e_t0 ! t0__3t0
2042 LSYM(x199) t0__8a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__3t0
2043 LSYM(x200) t0__5a0 ! t0__5t0 ! b_e_shift ! r__r_8t0
2044 LSYM(x201) t0__5a0 ! t0__5t0 ! b_e_t0 ! t0__8t0_a0
2045 LSYM(x202) t0__5a0 ! t0__5t0 ! b_e_2t0 ! t0__4t0_a0
2046 LSYM(x203) t0__5a0 ! t0__5t0 ! b_e_2t0a0 ! t0__4t0_a0
2047 LSYM(x204) t0__8a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__3t0
2048 LSYM(x205) t0__5a0 ! t0__8t0_a0 ! b_e_t0 ! t0__5t0
2049 LSYM(x206) t0__64a0 ! t0__t0_4a0 ! b_e_t02a0 ! t0__3t0
2050 LSYM(x207) t0__8a0 ! t0__2t0_a0 ! b_e_3t0 ! t0__4t0_a0
2051 LSYM(x208) t0__5a0 ! t0__5t0 ! b_e_8t0 ! t0__t0_a0
2052 LSYM(x209) t0__5a0 ! t0__5t0 ! b_e_8t0a0 ! t0__t0_a0
2053 LSYM(x210) t0__5a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__5t0
2054 LSYM(x211) t0__5a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__5t0
2055 LSYM(x212) t0__3a0 ! t0__4t0_a0 ! b_e_4t0 ! t0__4t0_a0
2056 LSYM(x213) t0__3a0 ! t0__4t0_a0 ! b_e_4t0a0 ! t0__4t0_a0
2057 LSYM(x214) t0__9a0 ! t0__t0_4a0 ! b_e_2t04a0 ! t0__8t0_a0
2058 LSYM(x215) t0__5a0 ! t0__4t0_a0 ! b_e_5t0 ! t0__2t0_a0
2059 LSYM(x216) t0__9a0 ! t0__3t0 ! b_e_shift ! r__r_8t0
2060 LSYM(x217) t0__9a0 ! t0__3t0 ! b_e_t0 ! t0__8t0_a0
2061 LSYM(x218) t0__9a0 ! t0__3t0 ! b_e_2t0 ! t0__4t0_a0
2062 LSYM(x219) t0__9a0 ! t0__8t0_a0 ! b_e_t0 ! t0__3t0
2063 LSYM(x220) t0__3a0 ! t0__9t0 ! b_e_4t0 ! t0__2t0_a0
2064 LSYM(x221) t0__3a0 ! t0__9t0 ! b_e_4t0a0 ! t0__2t0_a0
2065 LSYM(x222) t0__9a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__3t0
2066 LSYM(x223) t0__9a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__3t0
2067 LSYM(x224) t0__9a0 ! t0__3t0 ! b_e_8t0 ! t0__t0_a0
2068 LSYM(x225) t0__9a0 ! t0__5t0 ! b_e_t0 ! t0__5t0
2069 LSYM(x226) t0__3a0 ! t0__2t0_a0 ! b_e_t02a0 ! t0__32t0
2070 LSYM(x227) t0__9a0 ! t0__5t0 ! b_e_t02a0 ! t0__5t0
2071 LSYM(x228) t0__9a0 ! t0__2t0_a0 ! b_e_4t0 ! t0__3t0
2072 LSYM(x229) t0__9a0 ! t0__2t0_a0 ! b_e_4t0a0 ! t0__3t0
2073 LSYM(x230) t0__9a0 ! t0__5t0 ! b_e_5t0 ! t0__t0_a0
2074 LSYM(x231) t0__9a0 ! t0__2t0_a0 ! b_e_3t0 ! t0__4t0_a0
2075 LSYM(x232) t0__3a0 ! t0__2t0_a0 ! b_e_8t0 ! t0__4t0_a0
2076 LSYM(x233) t0__3a0 ! t0__2t0_a0 ! b_e_8t0a0 ! t0__4t0_a0
2077 LSYM(x234) t0__3a0 ! t0__4t0_a0 ! b_e_2t0 ! t0__9t0
2078 LSYM(x235) t0__3a0 ! t0__4t0_a0 ! b_e_2t0a0 ! t0__9t0
2079 LSYM(x236) t0__9a0 ! t0__2t0_a0 ! b_e_4t08a0 ! t0__3t0
2080 LSYM(x237) t0__16a0 ! t0__5t0 ! b_e_3t0 ! t0__t0ma0
2081 LSYM(x238) t0__3a0 ! t0__4t0_a0 ! b_e_2t04a0 ! t0__9t0
2082 LSYM(x239) t0__16a0 ! t0__5t0 ! b_e_t0ma0 ! t0__3t0
2083 LSYM(x240) t0__9a0 ! t0__t0_a0 ! b_e_8t0 ! t0__3t0
2084 LSYM(x241) t0__9a0 ! t0__t0_a0 ! b_e_8t0a0 ! t0__3t0
2085 LSYM(x242) t0__5a0 ! t0__3t0 ! b_e_2t0 ! t0__8t0_a0
2086 LSYM(x243) t0__9a0 ! t0__9t0 ! b_e_t0 ! t0__3t0
2087 LSYM(x244) t0__5a0 ! t0__3t0 ! b_e_4t0 ! t0__4t0_a0
2088 LSYM(x245) t0__8a0 ! t0__3t0 ! b_e_5t0 ! t0__2t0_a0
2089 LSYM(x246) t0__5a0 ! t0__8t0_a0 ! b_e_2t0 ! t0__3t0
2090 LSYM(x247) t0__5a0 ! t0__8t0_a0 ! b_e_2t0a0 ! t0__3t0
2091 LSYM(x248) t0__32a0 ! t0__t0ma0 ! b_e_shift ! r__r_8t0
2092 LSYM(x249) t0__32a0 ! t0__t0ma0 ! b_e_t0 ! t0__8t0_a0
2093 LSYM(x250) t0__5a0 ! t0__5t0 ! b_e_2t0 ! t0__5t0
2094 LSYM(x251) t0__5a0 ! t0__5t0 ! b_e_2t0a0 ! t0__5t0
2095 LSYM(x252) t0__64a0 ! t0__t0ma0 ! b_e_shift ! r__r_4t0
2096 LSYM(x253) t0__64a0 ! t0__t0ma0 ! b_e_t0 ! t0__4t0_a0
2097 LSYM(x254) t0__128a0 ! t0__t0ma0 ! b_e_shift ! r__r_2t0
2098 LSYM(x255) t0__256a0 ! a1_ne_0_b_l0 ! t0__t0ma0 ! b_n_ret_t0
2099 /*1040 insts before this. */
2100 LSYM(ret_t0) MILLIRET
2101 LSYM(e_t0) r__r_t0
2102 LSYM(e_shift) a1_ne_0_b_l2
2103 a0__256a0 /* a0 <<= 8 *********** */
2104 MILLIRETN
2105 LSYM(e_t0ma0) a1_ne_0_b_l0
2106 t0__t0ma0
2107 MILLIRET
2108 r__r_t0
2109 LSYM(e_t0a0) a1_ne_0_b_l0
2110 t0__t0_a0
2111 MILLIRET
2112 r__r_t0
2113 LSYM(e_t02a0) a1_ne_0_b_l0
2114 t0__t0_2a0
2115 MILLIRET
2116 r__r_t0
2117 LSYM(e_t04a0) a1_ne_0_b_l0
2118 t0__t0_4a0
2119 MILLIRET
2120 r__r_t0
2121 LSYM(e_2t0) a1_ne_0_b_l1
2122 r__r_2t0
2123 MILLIRETN
2124 LSYM(e_2t0a0) a1_ne_0_b_l0
2125 t0__2t0_a0
2126 MILLIRET
2127 r__r_t0
2128 LSYM(e2t04a0) t0__t0_2a0
2129 a1_ne_0_b_l1
2130 r__r_2t0
2131 MILLIRETN
2132 LSYM(e_3t0) a1_ne_0_b_l0
2133 t0__3t0
2134 MILLIRET
2135 r__r_t0
2136 LSYM(e_4t0) a1_ne_0_b_l1
2137 r__r_4t0
2138 MILLIRETN
2139 LSYM(e_4t0a0) a1_ne_0_b_l0
2140 t0__4t0_a0
2141 MILLIRET
2142 r__r_t0
2143 LSYM(e4t08a0) t0__t0_2a0
2144 a1_ne_0_b_l1
2145 r__r_4t0
2146 MILLIRETN
2147 LSYM(e_5t0) a1_ne_0_b_l0
2148 t0__5t0
2149 MILLIRET
2150 r__r_t0
2151 LSYM(e_8t0) a1_ne_0_b_l1
2152 r__r_8t0
2153 MILLIRETN
2154 LSYM(e_8t0a0) a1_ne_0_b_l0
2155 t0__8t0_a0
2156 MILLIRET
2157 r__r_t0
2159 .procend
2160 .end
2161 #endif