sim/iq2000/cpu.h

   1 /* CPU family header for iq2000bf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 3 of the License, or
  12 (at your option) any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with this program.  If not, see <http://www.gnu.org/licenses/>.
  21
  22 */
  23
  24 #ifndef CPU_IQ2000BF_H
  25 #define CPU_IQ2000BF_H
  26
  27 /* Maximum number of instructions that are fetched at a time.
  28    This is for LIW type instructions sets (e.g. m32r).  */
  29 #define MAX_LIW_INSNS 1
  30
  31 /* Maximum number of instructions that can be executed in parallel.  */
  32 #define MAX_PARALLEL_INSNS 1
  33
  34 /* CPU state information.  */
  35 typedef struct {
  36   /* Hardware elements.  */
  37   struct {
  38   /* program counter */
  39   USI h_pc;
  40 #define GET_H_PC() get_h_pc (current_cpu)
  41 #define SET_H_PC(x) \
  42 do { \
  43 set_h_pc (current_cpu, (x));\
  44 ;} while (0)
  45   /* General purpose registers */
  46   SI h_gr[32];
  47 #define GET_H_GR(index) (((index) == (0))) ? (0) : (CPU (h_gr[index]))
  48 #define SET_H_GR(index, x) \
  49 do { \
  50 if ((((index)) == (0))) {\
  51 ((void) 0); /*nop*/\
  52 }\
  53  else {\
  54 CPU (h_gr[(index)]) = (x);\
  55 }\
  56 ;} while (0)
  57   } hardware;
  58 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
  59 } IQ2000BF_CPU_DATA;
  60
  61 /* Cover fns for register access.  */
  62 USI iq2000bf_h_pc_get (SIM_CPU *);
  63 void iq2000bf_h_pc_set (SIM_CPU *, USI);
  64 SI iq2000bf_h_gr_get (SIM_CPU *, UINT);
  65 void iq2000bf_h_gr_set (SIM_CPU *, UINT, SI);
  66
  67 /* These must be hand-written.  */
  68 extern CPUREG_FETCH_FN iq2000bf_fetch_register;
  69 extern CPUREG_STORE_FN iq2000bf_store_register;
  70
  71 typedef struct {
  72   int empty;
  73 } MODEL_IQ2000_DATA;
  74
  75 /* Instruction argument buffer.  */
  76
  77 union sem_fields {
  78   struct { /* no operands */
  79     int empty;
  80   } fmt_empty;
  81   struct { /*  */
  82     IADDR i_jmptarg;
  83   } sfmt_j;
  84   struct { /*  */
  85     IADDR i_offset;
  86     UINT f_rs;
  87     UINT f_rt;
  88   } sfmt_bbi;
  89   struct { /*  */
  90     UINT f_imm;
  91     UINT f_rs;
  92     UINT f_rt;
  93   } sfmt_addi;
  94   struct { /*  */
  95     UINT f_mask;
  96     UINT f_rd;
  97     UINT f_rs;
  98     UINT f_rt;
  99   } sfmt_mrgb;
 100   struct { /*  */
 101     UINT f_maskl;
 102     UINT f_rd;
 103     UINT f_rs;
 104     UINT f_rt;
 105     UINT f_shamt;
 106   } sfmt_ram;
 107 #if WITH_SCACHE_PBB
 108   /* Writeback handler.  */
 109   struct {
 110     /* Pointer to argbuf entry for insn whose results need writing back.  */
 111     const struct argbuf *abuf;
 112   } write;
 113   /* x-before handler */
 114   struct {
 115     /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 116     int first_p;
 117   } before;
 118   /* x-after handler */
 119   struct {
 120     int empty;
 121   } after;
 122   /* This entry is used to terminate each pbb.  */
 123   struct {
 124     /* Number of insns in pbb.  */
 125     int insn_count;
 126     /* Next pbb to execute.  */
 127     SCACHE *next;
 128     SCACHE *branch_target;
 129   } chain;
 130 #endif
 131 };
 132
 133 /* The ARGBUF struct.  */
 134 struct argbuf {
 135   /* These are the baseclass definitions.  */
 136   IADDR addr;
 137   const IDESC *idesc;
 138   char trace_p;
 139   char profile_p;
 140   /* ??? Temporary hack for skip insns.  */
 141   char skip_count;
 142   char unused;
 143   /* cpu specific data follows */
 144   union sem semantic;
 145   int written;
 146   union sem_fields fields;
 147 };
 148
 149 /* A cached insn.
 150
 151    ??? SCACHE used to contain more than just argbuf.  We could delete the
 152    type entirely and always just use ARGBUF, but for future concerns and as
 153    a level of abstraction it is left in.  */
 154
 155 struct scache {
 156   struct argbuf argbuf;
 157 };
 158
 159 /* Macros to simplify extraction, reading and semantic code.
 160    These define and assign the local vars that contain the insn's fields.  */
 161
 162 #define EXTRACT_IFMT_EMPTY_VARS \
 163   unsigned int length;
 164 #define EXTRACT_IFMT_EMPTY_CODE \
 165   length = 0; \
 166
 167 #define EXTRACT_IFMT_ADD_VARS \
 168   UINT f_opcode; \
 169   UINT f_rs; \
 170   UINT f_rt; \
 171   UINT f_rd; \
 172   UINT f_shamt; \
 173   UINT f_func; \
 174   unsigned int length;
 175 #define EXTRACT_IFMT_ADD_CODE \
 176   length = 4; \
 177   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 178   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 179   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 180   f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 181   f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
 182   f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
 183
 184 #define EXTRACT_IFMT_ADDI_VARS \
 185   UINT f_opcode; \
 186   UINT f_rs; \
 187   UINT f_rt; \
 188   UINT f_imm; \
 189   unsigned int length;
 190 #define EXTRACT_IFMT_ADDI_CODE \
 191   length = 4; \
 192   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 193   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 194   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 195   f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
 196
 197 #define EXTRACT_IFMT_RAM_VARS \
 198   UINT f_opcode; \
 199   UINT f_rs; \
 200   UINT f_rt; \
 201   UINT f_rd; \
 202   UINT f_shamt; \
 203   UINT f_5; \
 204   UINT f_maskl; \
 205   unsigned int length;
 206 #define EXTRACT_IFMT_RAM_CODE \
 207   length = 4; \
 208   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 209   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 210   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 211   f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 212   f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
 213   f_5 = EXTRACT_LSB0_UINT (insn, 32, 5, 1); \
 214   f_maskl = EXTRACT_LSB0_UINT (insn, 32, 4, 5); \
 215
 216 #define EXTRACT_IFMT_SLL_VARS \
 217   UINT f_opcode; \
 218   UINT f_rs; \
 219   UINT f_rt; \
 220   UINT f_rd; \
 221   UINT f_shamt; \
 222   UINT f_func; \
 223   unsigned int length;
 224 #define EXTRACT_IFMT_SLL_CODE \
 225   length = 4; \
 226   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 227   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 228   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 229   f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 230   f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
 231   f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
 232
 233 #define EXTRACT_IFMT_SLMV_VARS \
 234   UINT f_opcode; \
 235   UINT f_rs; \
 236   UINT f_rt; \
 237   UINT f_rd; \
 238   UINT f_shamt; \
 239   UINT f_func; \
 240   unsigned int length;
 241 #define EXTRACT_IFMT_SLMV_CODE \
 242   length = 4; \
 243   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 244   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 245   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 246   f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 247   f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
 248   f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
 249
 250 #define EXTRACT_IFMT_SLTI_VARS \
 251   UINT f_opcode; \
 252   UINT f_rs; \
 253   UINT f_rt; \
 254   UINT f_imm; \
 255   unsigned int length;
 256 #define EXTRACT_IFMT_SLTI_CODE \
 257   length = 4; \
 258   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 259   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 260   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 261   f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
 262
 263 #define EXTRACT_IFMT_BBI_VARS \
 264   UINT f_opcode; \
 265   UINT f_rs; \
 266   UINT f_rt; \
 267   SI f_offset; \
 268   unsigned int length;
 269 #define EXTRACT_IFMT_BBI_CODE \
 270   length = 4; \
 271   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 272   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 273   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 274   f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
 275
 276 #define EXTRACT_IFMT_BBV_VARS \
 277   UINT f_opcode; \
 278   UINT f_rs; \
 279   UINT f_rt; \
 280   SI f_offset; \
 281   unsigned int length;
 282 #define EXTRACT_IFMT_BBV_CODE \
 283   length = 4; \
 284   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 285   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 286   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 287   f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
 288
 289 #define EXTRACT_IFMT_BGEZ_VARS \
 290   UINT f_opcode; \
 291   UINT f_rs; \
 292   UINT f_rt; \
 293   SI f_offset; \
 294   unsigned int length;
 295 #define EXTRACT_IFMT_BGEZ_CODE \
 296   length = 4; \
 297   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 298   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 299   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 300   f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
 301
 302 #define EXTRACT_IFMT_JALR_VARS \
 303   UINT f_opcode; \
 304   UINT f_rs; \
 305   UINT f_rt; \
 306   UINT f_rd; \
 307   UINT f_shamt; \
 308   UINT f_func; \
 309   unsigned int length;
 310 #define EXTRACT_IFMT_JALR_CODE \
 311   length = 4; \
 312   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 313   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 314   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 315   f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 316   f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
 317   f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
 318
 319 #define EXTRACT_IFMT_JR_VARS \
 320   UINT f_opcode; \
 321   UINT f_rs; \
 322   UINT f_rt; \
 323   UINT f_rd; \
 324   UINT f_shamt; \
 325   UINT f_func; \
 326   unsigned int length;
 327 #define EXTRACT_IFMT_JR_CODE \
 328   length = 4; \
 329   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 330   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 331   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 332   f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 333   f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
 334   f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
 335
 336 #define EXTRACT_IFMT_LB_VARS \
 337   UINT f_opcode; \
 338   UINT f_rs; \
 339   UINT f_rt; \
 340   UINT f_imm; \
 341   unsigned int length;
 342 #define EXTRACT_IFMT_LB_CODE \
 343   length = 4; \
 344   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 345   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 346   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 347   f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
 348
 349 #define EXTRACT_IFMT_LUI_VARS \
 350   UINT f_opcode; \
 351   UINT f_rs; \
 352   UINT f_rt; \
 353   UINT f_imm; \
 354   unsigned int length;
 355 #define EXTRACT_IFMT_LUI_CODE \
 356   length = 4; \
 357   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 358   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 359   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 360   f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
 361
 362 #define EXTRACT_IFMT_BREAK_VARS \
 363   UINT f_opcode; \
 364   UINT f_rs; \
 365   UINT f_rt; \
 366   UINT f_rd; \
 367   UINT f_shamt; \
 368   UINT f_func; \
 369   unsigned int length;
 370 #define EXTRACT_IFMT_BREAK_CODE \
 371   length = 4; \
 372   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 373   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 374   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 375   f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 376   f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
 377   f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
 378
 379 #define EXTRACT_IFMT_SYSCALL_VARS \
 380   UINT f_opcode; \
 381   UINT f_excode; \
 382   UINT f_func; \
 383   unsigned int length;
 384 #define EXTRACT_IFMT_SYSCALL_CODE \
 385   length = 4; \
 386   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 387   f_excode = EXTRACT_LSB0_UINT (insn, 32, 25, 20); \
 388   f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
 389
 390 #define EXTRACT_IFMT_ANDOUI_VARS \
 391   UINT f_opcode; \
 392   UINT f_rs; \
 393   UINT f_rt; \
 394   UINT f_imm; \
 395   unsigned int length;
 396 #define EXTRACT_IFMT_ANDOUI_CODE \
 397   length = 4; \
 398   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 399   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 400   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 401   f_imm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
 402
 403 #define EXTRACT_IFMT_MRGB_VARS \
 404   UINT f_opcode; \
 405   UINT f_rs; \
 406   UINT f_rt; \
 407   UINT f_rd; \
 408   UINT f_10; \
 409   UINT f_mask; \
 410   UINT f_func; \
 411   unsigned int length;
 412 #define EXTRACT_IFMT_MRGB_CODE \
 413   length = 4; \
 414   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 415   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 416   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 417   f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 418   f_10 = EXTRACT_LSB0_UINT (insn, 32, 10, 1); \
 419   f_mask = EXTRACT_LSB0_UINT (insn, 32, 9, 4); \
 420   f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
 421
 422 #define EXTRACT_IFMT_BC0F_VARS \
 423   UINT f_opcode; \
 424   UINT f_rs; \
 425   UINT f_rt; \
 426   SI f_offset; \
 427   unsigned int length;
 428 #define EXTRACT_IFMT_BC0F_CODE \
 429   length = 4; \
 430   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 431   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 432   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 433   f_offset = ((((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (2))) + (((pc) + (4)))); \
 434
 435 #define EXTRACT_IFMT_CFC0_VARS \
 436   UINT f_opcode; \
 437   UINT f_rs; \
 438   UINT f_rt; \
 439   UINT f_rd; \
 440   UINT f_10_11; \
 441   unsigned int length;
 442 #define EXTRACT_IFMT_CFC0_CODE \
 443   length = 4; \
 444   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 445   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 446   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 447   f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 448   f_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
 449
 450 #define EXTRACT_IFMT_CHKHDR_VARS \
 451   UINT f_opcode; \
 452   UINT f_rs; \
 453   UINT f_rt; \
 454   UINT f_rd; \
 455   UINT f_shamt; \
 456   UINT f_func; \
 457   unsigned int length;
 458 #define EXTRACT_IFMT_CHKHDR_CODE \
 459   length = 4; \
 460   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 461   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 462   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 463   f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 464   f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
 465   f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
 466
 467 #define EXTRACT_IFMT_LULCK_VARS \
 468   UINT f_opcode; \
 469   UINT f_rs; \
 470   UINT f_rt; \
 471   UINT f_rd; \
 472   UINT f_shamt; \
 473   UINT f_func; \
 474   unsigned int length;
 475 #define EXTRACT_IFMT_LULCK_CODE \
 476   length = 4; \
 477   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 478   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 479   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 480   f_rd = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
 481   f_shamt = EXTRACT_LSB0_UINT (insn, 32, 10, 5); \
 482   f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
 483
 484 #define EXTRACT_IFMT_PKRLR1_VARS \
 485   UINT f_opcode; \
 486   UINT f_rs; \
 487   UINT f_rt; \
 488   UINT f_count; \
 489   UINT f_index; \
 490   unsigned int length;
 491 #define EXTRACT_IFMT_PKRLR1_CODE \
 492   length = 4; \
 493   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 494   f_rs = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
 495   f_rt = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
 496   f_count = EXTRACT_LSB0_UINT (insn, 32, 15, 7); \
 497   f_index = EXTRACT_LSB0_UINT (insn, 32, 8, 9); \
 498
 499 #define EXTRACT_IFMT_RFE_VARS \
 500   UINT f_opcode; \
 501   UINT f_25; \
 502   UINT f_24_19; \
 503   UINT f_func; \
 504   unsigned int length;
 505 #define EXTRACT_IFMT_RFE_CODE \
 506   length = 4; \
 507   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 508   f_25 = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \
 509   f_24_19 = EXTRACT_LSB0_UINT (insn, 32, 24, 19); \
 510   f_func = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
 511
 512 #define EXTRACT_IFMT_J_VARS \
 513   UINT f_opcode; \
 514   UINT f_rsrvd; \
 515   USI f_jtarg; \
 516   unsigned int length;
 517 #define EXTRACT_IFMT_J_CODE \
 518   length = 4; \
 519   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
 520   f_rsrvd = EXTRACT_LSB0_UINT (insn, 32, 25, 10); \
 521   f_jtarg = ((((pc) & (0xf0000000))) | (((EXTRACT_LSB0_UINT (insn, 32, 15, 16)) << (2)))); \
 522
 523 /* Collection of various things for the trace handler to use.  */
 524
 525 typedef struct trace_record {
 526   IADDR pc;
 527   /* FIXME:wip */
 528 } TRACE_RECORD;
 529
 530 #endif /* CPU_IQ2000BF_H */