other-licenses/7zstub/src/Asm/arm/7zCrcOpt.asm

   1         CODE32
   2
   3         EXPORT  |CrcUpdateT4@16|
   4
   5         AREA    |.text|, CODE, ARM
   6
   7         MACRO
   8         CRC32_STEP_1
   9
  10         ldrb    r4, [r1], #1
  11         subs    r2, r2, #1
  12         eor     r4, r4, r0
  13         and     r4, r4, #0xFF
  14         ldr     r4, [r3, +r4, lsl #2]
  15         eor     r0, r4, r0, lsr #8
  16
  17         MEND
  18
  19
  20         MACRO
  21         CRC32_STEP_4 $STREAM_WORD
  22
  23         eor     r7, r7, r8
  24         eor     r7, r7, r9
  25         eor     r0, r0, r7
  26         eor     r0, r0, $STREAM_WORD
  27         ldr     $STREAM_WORD, [r1], #4
  28
  29         and     r7, r0, #0xFF
  30         and     r8, r0, #0xFF00
  31         and     r9, r0, #0xFF0000
  32         and     r0, r0, #0xFF000000
  33
  34         ldr     r7, [r6, +r7, lsl #2]
  35         ldr     r8, [r5, +r8, lsr #6]
  36         ldr     r9, [r4, +r9, lsr #14]
  37         ldr     r0, [r3, +r0, lsr #22]
  38
  39         MEND
  40
  41
  42 |CrcUpdateT4@16| PROC
  43
  44         stmdb   sp!, {r4-r11, lr}
  45         cmp     r2, #0
  46         beq     |$fin|
  47
  48 |$v1|
  49         tst     r1, #7
  50         beq     |$v2|
  51         CRC32_STEP_1
  52         bne     |$v1|
  53
  54 |$v2|
  55         cmp     r2, #16
  56         blo     |$v3|
  57
  58         ldr     r10, [r1], #4
  59         ldr     r11, [r1], #4
  60
  61         add     r4, r3, #0x400
  62         add     r5, r3, #0x800
  63         add     r6, r3, #0xC00
  64
  65         mov     r7, #0
  66         mov     r8, #0
  67         mov     r9, #0
  68
  69         sub     r2, r2, #16
  70
  71 |$loop|
  72         ; pld     [r1, #0x40]
  73
  74         CRC32_STEP_4 r10
  75         CRC32_STEP_4 r11
  76
  77         subs    r2, r2, #8
  78         bhs     |$loop|
  79
  80         sub     r1, r1, #8
  81         add     r2, r2, #16
  82
  83         eor     r7, r7, r8
  84         eor     r7, r7, r9
  85         eor     r0, r0, r7
  86
  87 |$v3|
  88         cmp     r2, #0
  89         beq     |$fin|
  90
  91 |$v4|
  92         CRC32_STEP_1
  93         bne     |$v4|
  94
  95 |$fin|
  96         ldmia   sp!, {r4-r11, pc}
  97
  98 |CrcUpdateT4@16| ENDP
  99
 100         END