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  13 <h1 id="icarusattributenamingconventions">Icarus Attribute Naming Conventions</h1>
  14 <div class="level1">
  15 <pre class="code">ATTRIBUTE NAMING CONVENTIONS
  16
  17 Attributes that are specific to Icarus Verilog, and are intended to be
  18 of use to programmers, start with the prefix &quot;ivl_&quot;.
  19
  20 Attributes with the &quot;_ivl_&quot; prefix are set aside for internal
  21 use. They may be generated internally by the compiler. They need not
  22 be documented here.
  23
  24 ATTRIBUTES TO CONTROL SYNTHESIS
  25
  26 The following is a summary of Verilog attributes that Icarus Verilog
  27 understands within Verilog source files to control synthesis
  28 behavior. This section documents generic synthesis attributes. For
  29 target specific attributes, see target specific documentation.
  30
  31 These attributes only effect the behavior of the synthesizer. For
  32 example, the ivl_combinational will not generate an error message
  33 if the Verilog is being compiled for simulation. (It may generate a
  34 warning.)
  35
  36
  37 * Attributes for &quot;always&quot; and &quot;initial&quot; statements
  38
  39 (* ivl_combinational *)
  40
  41     This attribute tells the compiler that the statement models
  42     combinational logic. If the compiler finds that it cannot make
  43     combinational logic out of a marked always statement, it will
  44     report an error.
  45
  46     This attribute can be used to prevent accidentally inferring
  47     latches or flip-flops where the user intended combinational
  48     logic.
  49
  50 (* ivl_synthesis_on *)
  51
  52     This attribute tells the compiler that the marked always statement
  53     is synthesizable. The compiler will attempt to synthesize the
  54     code in the marked &quot;always&quot; statement. If it cannot in any way
  55     synthesize it, then it will report an error.
  56
  57 (* ivl_synthesis_off *)
  58
  59     If this value is attached to an &quot;always&quot; statement, then the
  60     compiler will *not* synthesize the &quot;always&quot; statement. This can be
  61     used, for example, to mark embedded test bench code.
  62
  63
  64 * Attributes for modules
  65
  66 (* ivl_synthesis_cell *)
  67
  68     If this value is attached to a module during synthesis, that
  69     module will be considered a target architecture primitive, and
  70     its interior will not be synthesized further.  The module can
  71     therefore hold a model for simulation purposes.
  72
  73
  74 * Attributes for signals (wire/reg/integer/tri/etc.)
  75
  76 (* PAD = &quot;&lt;pad assignment list&gt;&quot; *)
  77
  78     If this attribute is attached to a signal that happens to be a
  79     root module port, then targets that support it will use the string
  80     value as a list of pin assignments for the port/signal. The format
  81     is a comma separated list of location tokens, with the format of
  82     the token itself defined by the back-end tools in use.
  83
  84 * Other Attributes
  85
  86 [ none defined yet ]
  87
  88
  89 MISC
  90
  91 (* _ivl_schedule_push *)
  92
  93     If this attribute is attached to a thread object (always or
  94     initial statement) then the vvp code generator will generate code
  95     that causes the scheduler to push this thread at compile time. The
  96     compiler may internally add this attribute to always statements if
  97     it detects that it is combinational. This helps resolve time-0
  98     races.</pre>
  99
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