| blob | 57ee8d29ed7403992ae75060305eff4ac2519458 |
3 <html>
4 <head>
10 </head>
11 <body>
16 * Copyright (c) 2001 Stephen Williams (steve@icarus.com)
17 *
19 */
21 VVP SIMULATION ENGINE
23 The VVP simulator takes as input source code not unlike assembly
24 language for a conventional processor. It is intended to be machine
25 generated code emitted by other tools, including the Icarus Verilog
26 compiler, so the syntax, though readable, is not necessarily
27 convenient for humans.
30 GENERAL FORMAT
32 The source file is a collection of statements. Each statement may have
33 a label, an opcode, and operands that depend on the opcode. For some
34 opcodes, the label is optional (or meaningless) and for others it is
35 required.
37 Every statement is terminated by a semicolon. The semicolon is also
38 the start of a comment line, so you can put comment text after the
39 semicolon that terminates a statement. Like so:
41 Label .functor and, 0x5a, x, y ; This is a comment.
43 The semicolon is required, whether the comment is there or not.
45 Statements may span multiple lines, as long as there is no text (other
46 then the first character of a label) in the first column of the
47 continuation line.
49 HEADER SYNTAX
51 Before any other non-commentary code starts, the source may contain
52 some header statements. These are used for passing parameters or
53 global details from the compiler to the vvp run-time. In all cases,
54 the header statement starts with a left-justified keyword.
58 This header statement names a vpi module that vvp should load before
59 the rest of the program is compiled. The compiler looks in the
61 dynamic load them.
65 This header statement specifies the time precision of a single tick of
66 the simulation clock. This is mostly used for display (and VPI)
67 purposes, because the engine itself does not care about units. The
68 compiler scales time values ahead of time.
70 The value is the size of a simulation tick in seconds, and is
72 nanosecond. If the record is left out, then the precision is taken to
73 be +0.
75 LABELS AND SYMBOLS
77 Labels and symbols consist of the characters:
79 a-z
80 A-Z
82 .$_<>
85 are easily distinguished from keywords and numbers. A Label is a
86 symbol that starts a statement. If a label is present in a statement,
87 it must start in the first text column. This is how the lexical
88 analyzer distinguishes a label from a symbol. If a symbol is present
89 in a statement, it is in the operand. Opcodes of statements must be a
90 keyword.
92 Symbols are references to labels. It is not necessary for a label to
93 be declared before its use in a symbol, but it must be declared
94 eventually. When symbols refer to functors, the symbol represents the
95 vvp_ipoint_t pointer to the output. (Inputs cannot, and need not, be
96 references symbolically.)
98 If the functor is part of a vector, then the symbol is the
99 vvp_ipoint_t for the first functor. The [] operator can then be used
100 to reference a functor other then the first in the vector.
102 There are some special symbols that in certain contexts have special
103 meanings. As inputs to functors, the symbols "C<0>", "C<1>", "C<x>"
107 SCOPE STATEMENTS:
110 PARAMETER STATEMENTS:
112 Parameters are named constants within a scope. These parameters have a
113 type and value, and also a label so that they can be referenced as VPI
114 objects.
116 The syntax of a parameter is:
122 following:
124 real -- The parameter has a real value
125 string -- The parameter has a string value
127 -- The parameter is a vector, with specified
129 unsigned.
131 The value, then, is appropriate for the data type. For example:
136 FUNCTOR STATEMENTS:
138 A functor statement is a statement that uses the ``.functor''
139 opcode. Functors are the basic structural units of a simulation, and
140 include a type (in the form of a truth table) and up to four inputs. A
141 label is required for functors.
143 The general syntax of a functor is:
147 The symbol list is 4 names of labels of other functors. These connect
148 inputs of the functor of the statement to the output of other
150 type selects the truth lookup table to use for the functor
151 implementation. Most of the core gate types have built in tables.
153 The initial values of all the inputs and the output is x. Any other
155 symbols, then the inputs are initialized to the specified bit value,
156 and if this causes the output to be something other then x, a
157 propagation event is created to be executed at the start of run time.
159 The strengths of inputs are ignored by functors, and the output has
160 fixed drive0 and drive1 strengths. So strength information is
161 typically lost as it passes through functors.
163 Almost all of the structural aspects of a simulation can be
164 represented by functors, which perform the very basic task of
165 combining up to four inputs down to one output.
167 - MUXZ
169 Q | A B S n/a
170 --+-------------
171 A | * * 0
172 B | * * 1
175 DFF STATEMENTS:
177 The Verilog language itself does not have a DFF primitive, but post
178 synthesis readily creates DFF devices that are best simulated with a
179 common device. Thus, there is the DFF statement to create DFF devices:
186 type of datum at all. The device will transfer the input to the output
188 asynchronous input that is immediately stored and transferred to the
189 output when data arrives here. This is useful for implementing
190 asynchronous set/clear functions.
192 UDP STATEMENTS:
194 A UDP statement either defines a User Defined Primitive, or
195 instantiates a previously defined UDP by creating a UDP functor. A
196 UDP functor has as many inputs as the UDP definition requires.
198 UDPs come in sequential and combinatorial flavors. Sequential UDPs
199 carry an output state and can respond to edges at the inputs. The
200 output of combinatorial UDPs is a function of its current inputs
201 only.
203 The function of a UDP is defined via a table. The rows of the table
204 are strings which describe input states or edges, and the new output
205 state. Combinatorial UDPs require one character for each input, and
206 one character at the end for the output state. Sequential UDPs need
207 an additional char for the current state, which is the first char of
208 the row.
210 Any input transition or the new state must match at most one row (or
211 all matches must provide the same output state). If no row matches,
217 An input or current output state can be
227 For Sequential UDPs, at most one input state specification may be
228 replaced by an edge specification. Valid edges are:
238 A combinatorial UDP is defined like this:
240 <type> .udp/comb "<name>", <number>, "<row0>", "<row1>", ... ;
244 need an additional initialization value:
246 <type> .udp/sequ "<name>", <number>, <init>, "<row0>", "<row1>", ... ;
252 A UDP functor instance is created so:
258 input of the UDP.
261 VARIABLE STATEMENTS:
263 A variable is a bit vector that can be written by behavioral code (so
264 has no structural input) and propagates its output to a functor. The
265 general syntax of a variable is:
272 sake of VPI code that might access it. The variable is placed in the
273 current scope. The variable also has a width, defined by the indices
274 for the most significant and lest significant bits. If the indices are
275 equal (normally 0) the vector has width of one. If the width is greater
276 then one, a contiguous array of functors is created and the value of
277 the label is the address of the least significant bit.
279 A variable does not take inputs, since its value is set behaviorally
280 by assignment events. It does have output, though, and its output is
281 propagated into the net of functors in the usual way.
283 A variable gets its value by assignments from procedural code: %set
284 and %assign. These instructions write values to the port-0 input. From
285 there, the value is held.
287 Behavioral code can also invoke %cassign/v statements that work like
288 %set/v, but instead write to port-1 of the variable node. Writes to
289 port-1 of a variable activate continuous assign mode, where the values
290 written to port-0 are ignored. The continuous assign mode remains
293 Behavioral code may also invoke %force/v statements that write to port-2
294 to invoke force mode. This overrides continuous assign mode until a
297 NET STATEMENTS:
299 A net is similar to a variable, except that a thread cannot write to
300 it (unless it uses a force) and it is given a different VPI type
301 code. The syntax of a .net statement is also similar to but not
302 exactly the same as the .var statement:
312 Like a .var statement, the .net statement creates a VPI object with
313 the basename and dimensions given as parameters. The symbol is a
314 functor that feeds into the vector of the net, and the vpiHandle
315 holds references to that functor.
317 The input of a .net is replicated to its output. In this sense, it
318 acts like a diode. The purpose of this node is to hold various VPI
319 and event trappings. The .net and .net8 nodes are vector types. They
320 both may represent wires, but the .net8 nodes preserve strength values
321 that arrive through them, while .net nodes reduce strength values to
322 4-value logic. The .net8 nodes should only be used when strength
323 information really is possible.
326 represents. This label does not map to a functor, so only references
327 that know they want to access .nets are able to locate the symbol. In
328 particular, this includes behavioral %load and %wait instructions. The
329 references to net and reg objects are done through the .net label
330 instead of a general functor symbol. The instruction stores the
331 functor pointer, though.
333 The .alias statements do not create new nodes, but instead create net
334 names that are aliases of an existing node. This handles special cases
335 where a net has different names, possibly in different scopes.
337 MEMORY STATEMENTS:
339 Memories are arrays of words, each word a vvp_vector4_t vector of the
340 same width. The memory is canonically addressed as a 1-dimensional
341 array of words, although indices are stored with the memory for
342 calculating a canonical address from a multi-dimensional address.
345 connecting a read port to an existing memory, and (3) initializing the
346 memory's contents.
352 allowed for multidimensional indexing. This statement creates the
353 memory array and makes it available to procedural code.
355 Procedural access to the memory references the memory as single array
356 of words, with the base address==0, and the last address the size (in
357 words) of the memory -1. It is up to the compiler to convert Verilog
358 index sets to a canonical address. The multi-dimensional index set is
359 available for VPI use.
361 Structural read access is implemented in terms of address and data
362 ports. The addresses applied to the address port are expected to be
363 in canonical form.
365 A read port is a functor that takes a single input, the read address,
366 and outputs the word value at the given (canonical) address.
373 Any address input change, or any change in the addressed memory
374 contents, is immediately propagated to the port output.
376 A write port is a superset of a read port. It is a 4-input functor
377 that accepts the word address, an event input, a write enable input,
378 and the data input.
380 <label> .mem/port <memid>, <address>, <event>, <we>, <data> ;
384 port. For asynchronous transparent write operation, connect
388 There is no Verilog construct that calls for a structural write port
389 to a memory, but synthesis may ask for lpm_ram_d[pq] objects.
391 To initialize a memory, use:
396 address (canonical) of the first word to be initialized. The start
397 address allows multiple statements be used to initialize words of a
398 memory.
400 The values are one per word.
402 Procedural access to the memory employs an index register to address a
403 bit location in the memory, via the commands:
409 The memory bit is addressed by index register 3. The value of
411 word occupies a multiple of four bits.
414 EVENT STATEMENTS
416 Threads need to interact with the functors of a netlist synchronously,
417 as well as asynchronously. There are cases where the web of functors
418 needs to wake up a waiting thread. The web of functors signals threads
419 through .event objects, that are declared like so:
425 This event statement declares an object that a %wait instruction
426 can take as an operand. When a thread executes a %wait, it puts
427 itself in the notification list of the event and suspends. The
432 string, then this is a named event which receives events by the %set
433 instruction instead of from the output of a functor.
435 If the event has inputs (a requirement unless it is a named event)
436 then it has up to 4 symbols that address functors. The event then
437 detects the appropriate edge on any of the inputs and signals when the
438 event is true. Normally (in Verilog) a posedge or negedge event only
439 watches a single bit, so the generated code would only include a
440 single symbol for the addressed bit. However, if there are several
441 events of the same edge in an event OR expression, the compiler may
442 combine up to 4 into a single event.
444 If many more events need to be combined together (for example due to
445 an event or expression in the Verilog) then this form can be used:
449 In this case, the symbols list all the events that are to be combined
450 to trigger this event. Only one of the input events needs to trigger
451 to make this one go.
454 RESOLVER STATEMENTS:
456 Resolver statements are strength-aware functors with 4 inputs, but
457 their job typically is to calculate a resolved output using strength
458 resolution. The type of the functor is used to select a specific
459 resolution function.
465 The output from the resolver is vvp_vector8_t value. That is, the
466 result is a vector with strength included.
469 PART SELECT STATEMENTS:
471 Part select statements are functors with three inputs. They take in at
472 port-0 a vector, and output a selected (likely smaller) part of that
473 vector. The other inputs specify what those parts are, as a canonical
474 bit number, and a width. Normally, those bits are constant values.
480 The input is typically a .reg or .net, but can be any vector node in
481 the netlist.
483 The .part/pv variation is the inverse of the .part version, in that
484 the output is actually written to a *part* of the output. The node
485 uses special part-select-write functions to propagate a part of a
487 that part is written to. Destination nodes use this value to check
488 further output widths.
490 The .part/v variation takes a vector (or long) input on port-1 as the
491 base of the part select. Thus, the part select can move around.
493 PART CONCATENATION STATEMENTS:
495 The opposite of the part select statement is the part concatenation
496 statement. The .concat statement is a functor node that takes at input
497 vector values and produces a single vector output that is the
498 concatenation of all the inputs.
503 expected widths of all the inputs. These widths are needed to figure
504 the positions of the input vectors in the generated output, and are
505 listed in order LSB to MSB. The inputs themselves are also listed LSB
506 to MSB, with the LSB vector input coming through port-0 of the real
507 functor.
509 The initial output value is (W+X+Y+Z) bits of 'bx. As input values are
510 propagated, the bits are placed in the correct place in the output
511 vector value, and a new output value is propagated.
514 REPEAT VECTOR STATEMENTS:
516 The repeat vector statement is similar to the concatenation statement,
517 expect that the input is repeated a constant number of times. The
518 format of the repeat vector statement is:
524 vector value is repeated to make the output width. The input width is
527 REDUCTION LOGIC
529 The reduction logic statements take in a single vector, and propagate
530 a single bit.
539 the device has a single input, which is a vector of any width. The
540 device performs the logic on all the bits of the vector (a la Verilog)
541 and produces and propagates a single bit width vector.
543 EXPANSION LOGIC
545 Sign extension nodes are the opposite of reduction logic, in that they
546 take a narrow vector, or single bit, and pad it out to a wider
547 vector.
551 The .expand/s node takes an input symbol and sign-extends it to the
552 given width.
554 FORCE STATEMENTS (old method - remove me):
556 A force statement creates functors that represent a Verilog force
557 statement.
564 There will be as many force functors as there are symbols in the
567 To activate and deactivate a force on a single bit, use:
574 being forced.
576 FORCE STATEMENTS (new method - implement me):
578 A %force instruction, as described in the .var section, forces a
579 constant value onto a .var or .net, and the matching %release releases
580 that value. However, there are times when the value of a functor
581 (i.e. another .net) needs to be forced onto a .var or .net. For this
582 task, the %force/link instruction exists:
589 will automatically drive values to the force port of the destination
590 node. The matching %release/link instruction removes the link (a
591 %release is still needed) to the destination. The %release/link
592 releases the last %force/link, no matter where the link is from. A new
593 %force/link will remove a previous link.
595 The instructions:
600 are the same concept, but for the continuous assign port.
602 STRUCTURAL ARITHMETIC STATEMENTS:
604 The various Verilog arithmetic operators (+-*/%) are available to
605 structural contexts as two-input functors that take in vectors. All of
606 these operators take two inputs and generate a fixed width output. The
607 input vectors will be padded if needed to get the desired output width.
615 In all cases, there are no width limits, so long as the width is
616 fixed.
618 NOTE: The .arith/mult inputs are not necessarily the width of the
619 output. I have not decided how to handle this.
621 These devices support .s and .r suffixes. The .s means the node is a
622 signed vector device, the .r a real valued device.
624 STRUCTURAL COMPARE STATEMENTS:
626 The arithmetic statements handle various arithmetic operators that
627 have wide outputs, but the comparators have single bit output, so they
628 are implemented a bit differently. The syntax, however, is very
629 similar:
640 Whereas the arithmetic statements generate an output the width of
643 comparisons. (Equality doesn't need to care about sign.)
646 STRUCTURAL SHIFTER STATEMENTS:
648 Variable shifts in structural context are implemented with .shift
649 statements:
654 The shifter has a width that defines the vector width of the output, a
656 that is the amount to shift. The vectors that come from port 0 are the
657 data to be shifted and must have exactly the width of the output. The
658 input to port 1 is the amount to shift.
661 STRUCTURAL FUNCTION CALLS:
663 The .ufunc statement defines a call to a user defined function.
665 <label> .ufunc <flabel>, <wid>, <isymbols> ( <psymbols> ) <rsymbol> ;
668 function implementation. This is code that the simulator will branch
669 to.
674 function. These are points in the net, and the ufunc device watches
675 these nets for input changes.
679 the function. The ufunc performs an assignment to these variables
680 before calling the function.
683 result will be found when the function code ends. This value is picked
684 up and propagated to the output of the functor.
686 THREAD STATEMENTS:
688 Thread statements create the initial threads for a simulation. These
689 represent the initial and always blocks, and possibly other causes to
690 create threads at startup.
694 This statement creates a thread with a starting address at the
697 addressed instruction.
700 thread. Supported flags are:
702 $push -- Cause the thread to be pushed in the scheduler. This
703 only effects startup (time 0) by arranging for pushed
704 threads to be started before non-pushed threads. This
705 is useful for resolving time-0 races.
707 * Threads in general
709 Thread statements create the initial threads of a design. These
711 Verilog, and possibly some other synthetic threads for various
712 purposes. It is also possible to create transient threads from
713 behavioral code. These are needed to support such constructs as
714 fork/join, named blocks and task activation.
716 A transient thread is created with a %fork instruction. When a
717 transient thread is created this way, the operand to the %fork gives
718 the starting address, and the new thread is said to be a child of the
719 forking thread. The children of a thread are pushed onto a stack of
720 children. A thread can have only one direct child.
722 A transient thread is reaped with a %join instruction. %join waits for
723 the top thread in the stack of children to complete, then
724 continues. It is an error to %join when there are no children.
726 As you can see, the transient thread in VVP is a cross between a
727 conventional thread and a function call. In fact, there is no %call
728 instruction in vvp, the job is accomplished with %fork/%join in the
729 caller and %end in the callee. The %fork, then is simply a
730 generalization of a function call, where the caller does not
731 necessarily wait for the callee.
733 For all the behavior of threads and thread parentage to work
734 correctly, all %fork statements must have a corresponding %join in the
735 parent, and %end in the child. Without this proper matching, the
736 hierarchical relationships can get confused. The behavior of erroneous
737 code is undefined.
739 * Thread Context
741 The context of a thread is all the local data that only that thread
742 can address. The local data is broken into two addresses spaces: bit
743 memory and word memory.
746 addressed in strips of arbitrary length. For example, an 8-bit value
750 manufacture complex values elsewhere.
752 The word memory is a region of tagged words. The value in each word
753 may be native long or real. These words have a distinct address space
754 from the bits.
756 * Threads and scopes
758 The Verilog ``disable'' statement deserves some special mention
759 because of how it interacts with threads. In particular, threads
760 throughout the design can affect (end) other threads in the design
761 using the disable statement.
763 In Verilog, the operand to the disable statement is the name of a
764 scope. The behavior of the disable is to cause all threads executing
765 in the scope to end. Termination of a thread includes all the children
766 of the thread. In vvp, all threads are in a scope, so this is how the
767 disable gains access to the desired thread.
769 It is obvious how initial/always thread join a scope. They become part
770 of the scope simply by being declared after a .scope declaration. (See
771 vvp.txt for .scope declarations.) The .thread statement placed in the
772 assembly source after a .scope statement causes the thread to join the
773 named scope.
775 Transient threads join a scope that is the operand to the %fork
776 instruction. The scope is referenced by name, and the thread created
777 by the fork atomically joins that scope. Once the transient thread
778 joins the scope, it stays there until it ends. Threads never change
779 scopes, not even transient threads.
781 TRUTH TABLES
783 The logic that a functor represents is expressed as a truth table. The
784 functor has four inputs and one output. Each input and output has one
786 represent them. So the input of the functor is 8 bits, and the output
789 small enough that the table should take less space then the code to
790 implement the logic.
792 To implement the truth table, we need to assign 2-bit encodings for
793 the 4-value signals. I choose, pseudo-randomly, the following
794 encoding:
803 so:
804 332211
807 pairs in the 8-bit byte are the output:
811 A complete truth table, then is described as 64 8-bit bytes.
813 The vvp engine includes truth tables for the primitive gate types, so
814 none needs to be given by the programmer. It is sufficient to name the
815 type to get that truth table.
818 EXECUTABLE INSTRUCTIONS
820 Threads run executable code, much like a processor executes machine
821 code. VVP has a variety of opcodes for executable instructions. All of
823 space. Labels attached to executable instructions get assigned the
824 address of the instruction, and can be the target of %jmp instructions
825 and starting points for threads.
827 The opcodes.txt file has a more detailed description of all the
828 various instructions.
831 THE RELATIONSHIP BETWEEN FUNCTORS, THREADS AND EVENTS
833 Given the above summary of the major components of vvp, some
834 description of their relationship is warranted. Functors provide a
835 structural description of the design (so far as it can be described
836 structurally) and these functors run independently of the threads. In
837 particular, when an input to a functor is set, it calculates a new
838 output value; and if that output is different from the existing
839 output, a propagation event is created. Functor output is calculated
840 by truth table lookup, without the aid of threads.
842 Propagation events are one of three kinds of events in vvp. They are
843 scheduled to execute at some time, and they simply point to the functor
844 that is to have its output propagated. When the event expires, the
845 output of the referenced functor is propagated to all the inputs that
846 it is connected to, and those functors in turn create new events if
847 needed.
849 Assignment events (the second of three types of events) are created
851 executed (a %assign in vvp) an assign event is created, which includes
852 the vvp_ipoint_t pointer to the functor input to receive the value,
853 as well as the value. These are distinct from propagation events because:
855 a) There is no functor that has as its output the value to be
856 assigned (this is how values get into the functor net in
857 the first place), and
859 b) This allows for behavioral code to create waveforms of
860 arbitrary length that feed into a variable. Verilog allows
861 this of non-blocking assignments, but not of gate outputs.
863 The last type of event is the thread schedule event. This event simply
864 points to a thread to be executed. Threads are made up of a virtual
865 processor with a program counter and some private storage. Threads
866 can execute %assign instructions to create assignment events, and can
867 execute %set instructions to do blocking assignments. Threads can also
868 use %load to read the output of functors.
870 The core event scheduler takes these three kinds of events and calls
871 the right kind of code to cause things to happen in the design. If the
872 event is a propagate or assignment event, the network of functors is
873 tickled; if the event is a thread schedule, then a thread is run. The
874 implementation of the event queue is not important, but currently is
875 implemented as a ``skip list''. That is, it is a sorted singly linked
876 list with skip pointers that skip over delta-time events.
878 The functor net and the threads are distinct. They communicate through
879 thread instructions %set, %assign, %waitfor and %load. So far as a thread
880 is concerned, the functor net is a blob of structure that it pokes and
881 prods via certain functor access instructions.
884 VVP COMPILATION AND EXECUTION
886 The vvp program operates in a few steps:
888 1) Initialization
889 Data structures are cleared to empty, and tables are
890 readied for compilation.
892 2) Compilation
893 The input file is read and compiled. Symbol tables are
894 build up as needed, objects are allocated and linked
895 together.
897 3) Cleanup
898 Symbol tables and other resources used only for
899 compilation are released to reduce the memory
900 footprint.
902 4) Simulation
903 Event simulation is run.
906 The initialization step is performed by the compile_init() function in
907 compile.cc. This function in turn calls all the *_init() functions in
908 other parts of the source that need initialization for compile. All
911 Compilation is controlled by the parser, it parse.y. As the parser
912 reads and parses input, the compilation proceeds in the rules by
913 calling various compile_* functions. All these functions live in the
914 compile.cc file. Compilation calls other sections of the code as
915 needed.
917 When the parser completes compilation, compile_cleanup() is called to
918 finish the compilation process. Unresolved references are completed,
919 then all the symbol tables and other compile-time-only resources are
920 released. Once compile_cleanup() returns, there is no more use for the
921 parser for the function in compile.cc.
923 After cleanup, the simulation is started. This is done by executing
924 the schedule_simulate() function. This does any final setup and starts
925 the simulation running and the event queue running.
928 HOW TO GET FROM THERE TO HERE
930 The vvp simulation engine is designed to be able to take as input a
931 compiled form of Verilog. That implies that there is a compiler that
932 compiles Verilog into a form that the vvp engine can read.
935 * Boolean logic gates
937 Gates like AND, OR and NAND are implemented simply and obviously by
938 functor statements. Any logic up to 4 inputs can be implemented with a
939 single functor. For example:
941 and gate (out, i1, i2, i3);
943 becomes:
945 gate .functor and, i1, i2, i3;
947 Notice the first parameter of the .functor is the type. The type
948 includes a truth table that describes the output with a given
949 input. If the gate is wider then four inputs, then cascade
950 functors. For example:
952 and gate (out, i1, i2, i3, i4, i5, i6, i7, i8);
954 becomes:
956 gate.0 .functor and, i1, i2, i3, i4;
957 gate.1 .functor and, i5, i6, i7, i8;
961 * reg and other variables
963 Reg and integer are cases of what Verilog calls ``variables.''
964 Variables are, simply put, things that behavioral code can assign
965 to. These are not the same as ``nets,'' which include wires and the
966 like.
968 Each bit of a variable is created by a ``.var'' statement. For example:
970 reg a;
972 becomes:
977 * named events
979 Events in general are implemented as functors, but named events in
980 particular have no inputs and only the event output. The way to
981 generate code for these is like so:
985 This creates a functor and makes it into a mode-2 functor. Then the
987 generated. This is sufficient to trigger the event.
989 /*
990 * Copyright (c) 2001 Stephen Williams (steve@icarus.com)
991 *
992 * This source code is free software; you can redistribute it
993 * and/or modify it in source code form under the terms of the GNU
994 * General Public License as published by the Free Software
995 * Foundation; either version 2 of the License, or (at your option)
996 * any later version.
997 *
998 * This program is distributed in the hope that it will be useful,
999 * but WITHOUT ANY WARRANTY; without even the implied warranty of
1000 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1001 * GNU General Public License for more details.
1002 *
1003 * You should have received a copy of the GNU General Public License
1004 * along with this program; if not, write to the Free Software
1006 */</pre>
1008 </div>
1009 </body>
1010 </html>