| blob | 8ac790c9ea1f1d7d3eeb940b9f4ba1c5a6b6d067 |
3 <html>
4 <head>
10 </head>
11 <body>
19 NAME
20 Covered - Verilog Code Coverage Analyzer
22 SYNTAX
28 DESCRIPTION
29 Covered is a Verilog code coverage analysis tool that can be useful for
30 determining how well a diagnostic test suite is covering the design
31 under test. Covered reads in the Verilog design files and a VCD or LXT
32 formatted dumpfile from a diagnostic run and generates a database file
33 called a Coverage Description Database (CDD) file, using the score com-
34 mand. This file can be merged with other CDD files from the same
35 design to create accummulated coverage, using the merge command. Once
36 a CDD file is created, the user can use Covered to generate various
37 human-readable coverage reports in an ASCII format or use Covered’s GUI
38 to interactively look at coverage results, using the report command.
39 Additionally, as part of Covered’s score command, race condition possi-
40 bilities are found in the design files and can be either ignored,
41 flagged as warnings or flagged as errors. By specifying race condi-
42 tions as errors, Covered can also be used as a race condition checker.
44 GLOBAL OPTIONS
45 These options are placed immediately after the keyword covered in the
46 command-line. They can be used for any command (with the exception of
47 -v and -h) and have the same effect in each case.
49 -D Debug. Display information helpful for debugging tool problems.
50 Note: This option is now only available when covered is built
51 with the --enable-debug configuration option.
53 -h Help. Display this usage information.
55 -Q Quiet mode. Causes all output to be suppressed.
57 -v Version. Display current Covered version.
59 COMMANDS
60 score Parses Verilog files and VCD/LXT dumpfiles to create database
61 file used for merging and reporting.
63 merge Merges two database files into one.
65 report Generates human-readable coverage reports from database file or
66 starts the coverage report GUI.
68 SCORE COMMAND
69 The following options are valid for the score command:
71 -D define_name
72 Defines the specified name to 1.
74 -D define_name=value
75 Defines the specified name to the specified value.
77 -e block_name
78 Name of module, task, function or named begin/end block to not
79 score. Causes all subblocks in the Verilog tree under this
80 block to also not be scored.
82 -ea Excludes all always blocks from being considered for coverage.
84 -ec Excludes all continuous assignments from being considered for
85 coverage.
87 -ei Excludes all initial blocks from being considered for coverage.
89 -F module_name=(in_expr,)out_expr
90 Indicates to the parser where to find the FSM located in module
91 module_name which has an input state expression called in_expr
92 and output state expression called out_expr. If in_expr is not
93 specified, out_expr is used as both the input and output state
94 expression.
96 -f filename
97 Name of file containing additional arguments to parse.
99 -h Displays this help information.
101 -I directory
102 Directory to find included Verilog files.
104 -i instance_name
105 Verilog hierarchical reference to the module that is at the top
106 of the tree to be scored. This option is necessary if module to
107 verify coverage is not the top-level module in the design. If
108 not specified, -t value is used.
110 -lxt filename
111 Name of LXT/LXT2 dumpfile to score design with. If this or the
112 -vcd option is not used, Covered will only create an initial CDD
113 file from the design and will not attempt to score the design.
115 -o database
116 Name of database to write coverage information to. If not spec-
119 -p filename
120 Overrides default filename used to store intermediate preproces-
121 sor output.
123 -P parameter_scope=value
124 Performs a defparam on the specified parameter with value.
126 -r(S|W|E)
127 Specifies action to take when race condition checking finds
128 problems in design (-rS = Silent, -rW = Warning, -rE = Error).
130 -S Outputs simulation statistics after simulation has completed.
131 This information is currently only useful for the developers of
132 Covered.
134 -t top-level module
135 Specifies the module name of the top-most module that will be
136 measured. Note that this module does not need to be the
137 top-most module in the simulator. This field is required for
138 all calls to the score command.
140 -ts number
141 When scoring occurs, this option allows the user to see how far
142 the simulator has progressed by outputting the current timestep
143 to standard output. The value of number specifies how many
144 timesteps are allowed to be simulated before outputting the cur-
145 rent timestep (results in less calls to output stream).
147 -T min|typ|max
148 Specifies which value to use when encountering a delay expres-
149 sion in the form: min:typ:max. If this option is not speci-
150 fied, ’typ’ select is used by default.
152 -v filename
153 Name of specific Verilog file to score.
155 -vcd filename
156 Name of VCD dumpfile to score design with. If this or the -lxt
157 option is not used, Covered will only create an initial CDD file
158 from the design and will not attempt to score the design.
160 -y directory
161 Directory to find unspecified Verilog files.
163 +libext+.extension(+.extension)*+
164 Extensions of Verilog files to allow in scoring.
166 MERGE COMMAND
167 The following options are valid for the merge command:
169 -h Displays this help information.
171 -o filename
172 File to output new database to. If this argument is not speci-
173 fied, the existing_database is used as the output database name.
175 REPORT COMMAND
176 The following options are valid with the report command:
178 -c If -v is specified, displays covered line, toggle and combina-
179 tional cases. Default is to display uncovered information.
181 -d (s|d|v)
182 Level of detail to provide in coverage report information (s =
183 summary, d = detailed, v = verbose). Default is summary.
185 -h Displays this help information.
187 -i Provides coverage information for instances instead of module.
189 -m [l][t][c][f][r]
190 Type(s) of metrics to report. Default is ltcf.
192 -o filename
193 File to output report information to. Default is standard out-
194 put.
196 -v Deprecated. Replaced by ’-d d’ or ’-d v’.
198 -view Starts the GUI interface for interactive coverage reporting.
200 -w (number)
201 Specifies the maximum line width (in characters) that can be
202 used to output Verilog information. If this option is not spec-
203 ified, all Verilog code in the report will retain the same for-
204 matting as was specified in the original Verilog code. If this
205 option is specified, Verilog code will be formatted to use as
206 much of the current line as possible, wrapping text when the
207 line reaches the maximum line width. The default maximum line
208 width is 115 characters (this value is used if no number is
209 specified with the -w option). If a number is specified with
210 the -w option, this value is used for the maximum line width.
212 AUTHORS
217 SEE ALSO
218 For more information on how to use the Covered code coverage tool,
219 please consult the on-line User’s Guide at http://covered.source-
220 forge.net/user/index.html.
226 </div>
227 </body>
228 </html>