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17 <h1 class=
"sectionedit1" id=
"hierarchical_spice_model">Hierarchical SPICE model
</h1>
21 Example of a hierarchical analog RF SPICE model in the:
<br/>
23 <strong><code>${prefix}/share/doc/geda-gaf/examples/RF_Amp
</code></strong><br/>
25 directory, where
<code>${prefix}
</code> is the installation prefix for gEDA on your
26 system (usually
<strong><code>/usr
</code></strong> or
<strong><code>/usr/local
</code></strong>).
28 <pre class=
"code">This README created
3.31.2003
30 --------------------- Contents of directories -----------------------
32 This directory holds the schematics and associated materials for a
33 SPICE model of Agilent
's MSA-
2643 bipolar amp. The model was obtained
34 from Agilent
's datasheet
5980-
2396E. The directory structure is as
37 RF_Amp (base directory)
39 MSA-
2643.sch -- schematic of stuff inside device package (as shown in
40 p.
7 of datasheet. Note that I have not included the transmission
41 lines in this schematic because no value of Z was included in the data
42 sheet. (Yes, it
's probably
50 ohms, but including them was a
43 sideshow compared to my main intent: build a hierarchical model of an
45 MSA-
2643.cir -- netlisted circuit ready for SPICE simulation.
47 Q1.sch -- schematic model of Q1 MSA-
26 transistor shown on p.
8 of datasheet.
48 Q1.cir -- netlisted circuit holding .SUBCKT model of Q1.
50 Q2.sch -- schematic model of Q2 MSA-
26 transistor shown on p.
8 of datasheet.
51 Q2.cir -- netlisted circuit holding .SUBCKT model of Q2.
55 Simulation.cmd -- a file holding SPICE analysis commands which is read
56 at simulation time by the SPICE simulator.
58 5980-
2396E.pdf -- Agilent datasheet about the MSA-
2643.
63 BJTM1_Q1.mod -- text-based SPICE model of BJT1 used in Q1 .SUBCKT
64 DiodeM1_Q1.mod -- text-based SPICE model of diode M1 used in Q1 .SUBCKT
65 DiodeM2_Q1.mod -- SPICE model of diode M2 used in Q1 .SUBCKT
66 DiodeM3_Q1.mod -- SPICE model of diode M3 used in Q1 .SUBCKT
67 (similar files for Q2 models. . . .)
68 These models were obtained from parameters give in p.
8 of the datasheet.
73 spice-subcircuit-IO-
1.sym
74 spice-subcircuit-LL-
1.sym
75 Q_Model.sym -- symbol pointing to lower level models placed on upper
78 ------------ Usage of hierarchical spice models ---------------------
79 This project exemplifies construction of a hierarchical SPICE
80 simulation using gEDA. The project is built in the following way:
82 1. Use a text editor to create .mod files containing SPICE models of
83 the transistors and diodes on p.
8 of the datasheet.
85 2. Create Q1 and Q2 transistor model schematics using gschem. Place
86 the .SUBCKT SPICE block on the schematic to alert the netlister that
87 the schematic is a lower level .SUBCKT for incorporation into other
88 schematics. Place spice-IO pads on the schematic to instantiate the
89 IOs. Make sure to number the spice-IO pads in the same order as you
90 wish them to appear in the .SUBCKT line in the .cir.
92 3. Generate the .SUBCKT netlist by saying:
94 gnetlist -g spice-sdb -o Q1.cir Q1.sch
95 gnetlist -g spice-sdb -o Q2.cir Q2.sch
97 4. Create a symbol for Q1.cir and Q2.cir which will be dropped onto
98 the higher lever schematic. Name the symbol Q_Model.sym. Set the
99 symbol
"DEVICE
" attribute = NPN_TRANSISTOR_subcircuit. This causes
100 the netlister to use
"write-default-component
" to write out the SPICE
101 line for the component. Make sure that the
"REFDES
" attribute is X?
102 and not Q? -- this enables the .SUBCKT file to be attached to the
105 5. Create the higher layer schematic MSA-
2643.sch. Place
106 two copies of Q_Model.sym onto the schematic, corresponding to Q1 and
107 Q2. Make Q1 point to its model by setting the following attributes:
109 model-name: Q1_MSA26F
114 6. Create the rest of the higher layer schematic the usual way. Make
115 sure to place a spice-include block on the schematic and point it to
116 "Simulation.cmd
". Place any analysis commands (e.g. .DC, .AC, .TRAN,
117 etc.) into the file
"Simulation.cmd
".
119 7. Netlist the higher layer design:
121 gnetlist -g spice-sdb -o MSA-
2643.cir MSA-
2643.sch
123 8. The circuit may be simulated by any desired SPICE simulation
124 and analysis package, e.g. LTSpice.
126 -------------------- Contact ----------------------------
127 Documentation and other materials relevant to SPICE simulation under
128 gEDA lives at http://www.brorson.com/gEDA/SPICE
130 For inquiries or bug reports, please contact me:
133 mailto:sdb@cloud9.net
</pre>
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