docs/wiki/geda-icarus_extensions.html

   1 <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
   2  "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
   3 <html>
   4 <head>
   5   <link rel="stylesheet" media="screen" type="text/css" href="./style.css" />
   6   <link rel="stylesheet" media="screen" type="text/css" href="./design.css" />
   7   <link rel="stylesheet" media="print" type="text/css" href="./print.css" />
   8
   9   <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
  10 </head>
  11 <body>
  12
  13 <h1 class="sectionedit1" id="icarus_verilog_extensions">Icarus Verilog Extensions</h1>
  14 <div class="level1">
  15 <pre class="code">Icarus Verilog Extensions
  16
  17 Icarus Verilog supports certain extensions to the baseline IEEE1364
  18 standard. Some of these are picked from extended variants of the
  19 language, such as SystemVerilog, and some are expressions of internal
  20 behavior of Icarus Verilog, made available as a tool debugging aid.
  21
  22 * Builtin System Functions
  23
  24 ** Extended Verilog Data Types
  25
  26 This feature is turned off if the generation flag &quot;-g&quot; is set to other
  27 then the default &quot;2x&quot;.  For example, &quot;iverilog -g2x&quot; enables extended
  28 data types, and &quot;iverilog -g2&quot; disables them.
  29
  30 Icarus Verilog adds support for extended data types. This extended
  31 type syntax is based on a proposal by Cadence Design Systems,
  32 originally as an update to the IEEE1364. That original proposal has
  33 apparently been absorbed by the IEEE1800 SystemVerilog
  34 standard. Icarus Verilog currently only takes the new primitive types
  35 from the proposal.
  36
  37 Extended data types separates the concept of net/variable from the
  38 data type. Both nets and variables can declared with any data
  39 type. The primitive types available are:
  40
  41     logic  - The familiar 0, 1, x and z, optionally with strength.
  42     bool   - Limited to only 0 and 1
  43     real   - 64bit real values
  44
  45 Nets with logic type may have multiple drivers with strength, and the
  46 value is resolved the usual way. Only logic values may be driven to
  47 logic nets, so bool values driven onto logic nets are implicitly
  48 converted to logic.
  49
  50 Nets with any other type may not have multiple drivers. The compiler
  51 should detect the multiple drivers and report an error.
  52
  53 - Declarations
  54
  55 The declaration of a net is extended to include the type of the wire,
  56 with the syntax:
  57
  58     wire &lt;type&gt; &lt;wire-assignment-list&gt;... ;
  59
  60 The &lt;type&gt;, if omitted, is taken to be logic. The &quot;wire&quot; can be any of
  61 the net keywords. Wires can be logic, bool, real, or vectors of logic
  62 or bool. Some valid examples:
  63
  64     wire real foo = 1.0;
  65     tri logic bus[31:0];
  66     wire bool addr[23:0];
  67     ... and so on.
  68
  69 The declarations of variables is similar. The &quot;reg&quot; keyword is used to
  70 specify that this is a variable. Variables can have the same data
  71 types as nets.
  72
  73 - Ports
  74
  75 Module and task ports in standard verilog are restricted to logic
  76 types. This extension removes that restriction, allowing any type to
  77 pass through the port consistent with the continuous assignment
  78 connectivity that is implied by the type.
  79
  80 - Expressions
  81
  82 Expressions in the face of real values is covered by the baseline
  83 Verilog standard.
  84
  85 The bool type supports the same operators as the logic type, with the
  86 obvious differences imposed by the limited domain.
  87
  88 Comparison operators (not case compare) return logic if either of
  89 their operands is logic. If both are bool or real (including mix of
  90 bool and real) then the result is bool. This is because comparison of
  91 bools and reals always return exactly true or false.
  92
  93 Case comparison returns bool. This differs from baseline Verilog,
  94 which strictly speaking returns a logic, but only 0 or 1 values.
  95
  96 All the arithmetic operators return bool if both of their operands are
  97 bool or real. Otherwise, they return logic.</pre>
  98
  99 </div>
 100 </body>
 101 </html>