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13 <h1 class="sectionedit1" id="icarus_verilog_compiler_man-page">Icarus Verilog compiler man-page</h1>
19 NAME
20 iverilog - Icarus Verilog compiler
23 SYNOPSIS
24 iverilog [-ESVv] [-Bpath] [-ccmdfile] [-g1|-g2|-g2x] [-Dmacro[=defn]]
25 [-pflag=value] [-Iincludedir] [-mmodule] [-Mfile] [-Nfile] [-ooutput-
26 filename] [-stopmodule] [-ttype] [-Tmin/typ/max] [-Wclass] [-ypath]
27 sourcefile
30 DESCRIPTION
31 iverilog is a compiler that translates Verilog source code into exe-
32 cutable programs for simulation, or other netlist formats for further
33 processing. The currently supported targets are vvp for simulation, and
34 xnf and fpga for synthesis. Other target types are added as code gener-
35 ators are implemented.
38 OPTIONS
39 iverilog accepts the following options:
41 -Bbase The iverilog program uses external programs and configuration
42 files to preprocess and compile the Verilog source. Normally,
43 the path used to locate these tools is built into the iverilog
44 program. However, the -B switch allows the user to select a
45 different set of programs. The path given is used to locate
46 ivlpp, ivl, code generators and the VPI modules.
48 -cfile This flag specifies an input file that contains a list of Ver-
49 ilog source files. This is similar to the command file of other
50 Verilog simulators, in that it is a file that contains the file
51 names instead of taking them on the command line. See Command
52 Files below.
54 -Dmacro Defines macro macro with the string ‘1’ as its definition. This
55 form is normally only used to trigger ifdef conditionals in the
56 Verilog source.
58 -Dmacro=defn
59 Defines macro macro as defn.
61 -E Preprocess the Verilog source, but do not compile it. The out-
62 put file is the Verilog input, but with file inclusions and
63 macro references expanded and removed. This is useful, for
64 example, to preprocess Verilog source for use by other compil-
65 ers.
67 -g1|-g2|-g2x
68 Select the Verilog language generation to support in the com-
70 or Verilog with extension(2x). Normally, Icarus Verilog
71 defaults to the latest known generation of the language. This
72 flag is most useful to restrict the language to a set supported
73 by tools of specific generations, for compatibility with other
74 tools.
76 -Iincludedir
77 Append directory includedir to list of directories searched for
78 Verilog include files. The -I switch may be used many times to
79 specify several directories to search, the directories are
80 searched in the order they appear on the command line.
82 -Mpath Write into the file specified by path a list of files that con-
83 tribute to the compilation of the design. This includes files
84 that are included by include directives and files that are
85 automatically loaded by library support. The output is one file
86 name per line, with no leading or trailing space.
88 -mmodule
89 Add this module to the list of VPI modules to be loaded by the
90 simulation. Many modules can be specified, and all will be
91 loaded, in the order specified. The system module is implicit
92 and always included.
94 -Npath This is used for debugging the compiler proper. Dump the final
95 netlist form of the design to the specified file. It otherwise
96 does not affect operation of the compiler. The dump happens
97 after the design is elaborated and optimized.
99 -o filename
100 Place output in the file filename. If no output file name is
101 specified, iverilog uses the default name a.out.
103 -pflag=value
104 Assign a value to a target specific flag. The -p switch may be
105 used as often as necessary to specify all the desired flags.
106 The flags that are used depend on the target that is selected,
107 and are described in target specific documentation. Flags that
108 are not used are ignored.
110 -S Synthesize. Normally, if the target can accept behavioral
111 descriptions the compiler will leave processes in behavioral
112 form. The -S switch causes the compiler to perform synthesis
113 even if it is not necessary for the target. If the target type
114 is a netlist format, the -S switch is unnecessary and has no
115 effect.
117 -s topmodule
118 Specify the top level module to elaborate. Icarus Verilog will
119 by default choose modules that are not instantiated in any
120 other modules, but sometimes that is not sufficient, or instan-
121 tiates too many modules. If the user specifies one or more root
122 modules with -s flags, then they will be used as root modules
123 instead.
125 -Tmin|typ|max
126 Use this switch to select min, typ or max times from
127 min:typ:max expressions. Normally, the compiler will simply use
128 the typ value from these expressions (with a warning) but this
129 switch will tell the compiler explicitly which value to use.
130 This will suppress the warning that the compiler is making a
131 choice.
133 -ttarget
134 Use this switch to specify the target output format. See the
135 TARGETS section below for a list of valid output formats.
137 -v Turn on verbose messages. This will print the command lines
138 that are executed to perform the actual compilation, along with
139 version information from the various components, as well as the
140 version of the product as a whole. You will notice that the
141 command lines include a reference to a key temporary file that
142 passes information to the compiler proper. To keep that file
143 from being deleted at the end of the process, provide a file
144 name of your own in the environment variable IVERILOG_ICONFIG.
146 -V Print the version of the compiler, and exit.
148 -Wclass Turn on different classes of warnings. See the WARNING TYPES
149 section below for descriptions of the different warning groups.
150 If multiple -W switches are used, the warning set is the union
151 of all the requested classes.
153 -ylibdir
154 Append the directory to the library module search path. When
155 the compiler finds an undefined module, it looks in these
156 directories for files with the right name.
159 MODULE LIBRARIES
160 The Icarus Verilog compiler supports module libraries as directories
161 that contain Verilog source files. During elaboration, the compiler
162 notices the instantiation of undefined module types. If the user speci-
163 fies library search directories, the compiler will search the directory
164 for files with the name of the missing module type. If it finds such a
165 file, it loads it as a Verilog source file, they tries again to elabo-
166 rate the module.
168 Library module files should contain only a single module, but this is
169 not a requirement. Library modules may reference other modules in the
170 library or in the main design.
173 TARGETS
174 The Icarus Verilog compiler supports a variety of targets, for differ-
175 ent purposes, and the -t switch is used to select the desired target.
178 null The null target causes no code to be generated. It is useful
179 for checking the syntax of the Verilog source.
181 vvp This is the default. The vvp target generates code for the vvp
182 runtime. The output is a complete program that simulates the
183 design but must be run by the vvp command.
185 xnf This is the Xilinx Netlist Format used by many tools for plac-
186 ing devices in FPGAs or other programmable devices. This target
187 is obsolete, use the fpga target instead.
189 fpga This is a synthesis target that supports a variety of fpga
190 devices, mostly by EDIF format output. The Icarus Verilog fpga
191 code generator can generate complete designs or EDIF macros
192 that can in turn be imported into larger designs by other
193 tools. The fpga target implies the synthesis -S flag.
196 WARNING TYPES
197 These are the types of warnings that can be selected by the -W switch.
198 All the warning types (other then all) can also be prefixed with no- to
199 turn off that warning. This is most useful after a -Wall argument to
200 suppress isolated warning types.
203 all This enables all supported warning categories.
206 implicit
207 This enables warnings for creation of implicit declarations.
208 For example, if a scalar wire X is used but not declared in the
209 Verilog source, this will print a warning at its first use.
212 portbind
213 This enables warnings for ports of module instantiations that
214 are not connected but probably should be. Dangling input ports,
215 for example, will generate a warning.
218 timescale
219 This enables warnings for inconsistent use of the timescale
220 directive. It detects if some modules have no timescale, or if
221 modules inherit timescale from another file. Both probably mean
222 that timescales are inconsistent, and simulation timing can be
223 confusing and dependent on compilation order.
226 SYSTEM FUNCTION TABLE FILES
227 If the source file name as a .sft suffix, then it is taken to be a sys-
228 tem function table file. A System function table file is used to
229 describe to the compiler the return types for system functions. This is
230 necessary because the compiler needs this information to elaborate
231 expressions that contain these system functions, but cannot run the
232 sizetf functions since it has no run-time.
234 The format of the table is ASCII, one function per line. Empty lines
235 are ignored, and lines that start with the ’#’ character are comment
236 lines. Each non-comment line starts with the function name, then the
237 vpi type (i.e. vpiSysFuncReal). The following types are supported:
240 vpiSysFuncReal
241 The function returns a real/realtime value.
244 vpiSysFuncInt
245 The function returns an integer.
249 The function returns a vector with the given width, and is
250 signed or unsigned according to the flag.
253 COMMAND FILES
254 The command file allows the user to place source file names and certain
255 command line switches into a text file instead of on a long command
256 line. Command files can include C or C++ style comments, as well as #
257 comments, if the # starts the line.
260 file name
261 A simple file name or file path is taken to be the name of a
262 Verilog source file. The path starts with the first non-white-
263 space character. Variables are substitued in file names.
266 -y libdir
267 A -y token prefixes a library directory in the command file,
268 exactly like it does on the command line. The parameter to the
269 -y flag may be on the same line or the next non-comment line.
271 Variables in the libdir are substituted.
274 +incdir+includedir
275 The +incdir+ token in command files gives directories to search
276 for include files in much the same way that -I flags work on
277 the command line. The difference is that multiple +includedir
278 directories are valid parameters to a single +incdir+ token,
279 although you may also have multiple +incdir+ lines.
281 Variables in the includedir are substituted.
284 +libext+ext
285 The +libext token in command files fives file extensions to try
286 when looking for a library file. This is useful in conjunction
287 with -y flags to list suffixes to try in each directory before
288 moving on to the next library directory.
291 +libdir+dir
292 This is another way to specify library directories. See the -y
293 flag.
296 +libdir-nocase+dir
297 This is like the +libdir statement, but file names inside the
298 directories declared here are case insensitive. The missing
299 module name in a lookup need not match the file name case, as
304 +define+NAME=value
305 The +define+ token is the same as the -D option on the command
306 line. The value part of the token is optional.
309 +toupper-filename
310 This token causes file names after this in the command file to
311 be translated to uppercase. This helps with situations where a
312 directory has passed through a DOS machine, and in the process
313 the file names become munged.
316 +tolower-filename
317 This is similar to the +toupper-filename hack described above.
320 VARIABLES IN COMMAND FILES
321 In certain cases, iverilog supports variables in command files. These
323 environment variable to read. The entire string is replaced with the
324 contents of that variable. Variables are only substitued in contexts
325 that explicitly support them, including file and directory strings.
327 Variable values come from the operating system environment, and not
328 from preprocessor defines elsewhere in the file or the command line.
331 EXAMPLES
332 These examples assume that you have a Verilog source file called
333 hello.v in the current directory
335 To compile hello.v to an executable file called a.out:
337 iverilog hello.v
339 To compile hello.v to an executable file called hello:
341 iverilog -o hello hello.v
343 To compile and run explicitly using the vvp runtime:
345 iverilog -ohello.vvp -tvvp hello.v
347 To compile hello.v to a file in XNF-format called hello.xnf
349 iverilog -txnf -ohello.xnf hello.v
353 AUTHOR
354 Steve Williams (steve@icarus.com)
357 SEE ALSO
361 COPYRIGHT
362 Copyright © 2002 Stephen Williams
364 This document can be freely redistributed according to the terms of the
365 GNU General Public License version 2.0
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