docs/wiki/geda-icarus_opcodes.html

   1 <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN"
   2  "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
   3 <html>
   4 <head>
   5   <link rel="stylesheet" media="screen" type="text/css" href="./style.css" />
   6   <link rel="stylesheet" media="screen" type="text/css" href="./design.css" />
   7   <link rel="stylesheet" media="print" type="text/css" href="./print.css" />
   8
   9   <meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
  10 </head>
  11 <body>
  12
  13 <h1 class="sectionedit1" id="executable_instruction_opcodes">Executable Instruction Opcodes</h1>
  14 <div class="level1">
  15 <pre class="code">/*
  16  * Copyright (c) 2001-2003 Stephen Williams (steve@icarus.com)
  17  *
  18  *  $Id: opcodes.txt,v 1.69 2005/11/26 17:16:05 steve Exp $
  19  */
  20
  21
  22
  23 EXECUTABLE INSTRUCTION OPCODES
  24
  25 Instruction opcodes all start with a % character and have 0 or more
  26 operands. In no case are there more then 3 operands. This chapter
  27 describes the specific behavior of each opcode, in enough detail
  28 (I hope) that its complete effect can be predicted.
  29
  30 General principles of Arithmetic:
  31
  32 The binary arithmetic instruction in general take three parameters,
  33 the left operand, the right operand, and the base. The left operand is
  34 replaced with the result, which is the same width as the left and
  35 right operands.
  36
  37
  38 * %add &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
  39
  40 This instruction adds the right vector into the left vector, the
  41 vectors having the width &lt;wid&gt;. If any of the bits of either vector
  42 are x or z, the result is x. Otherwise, the result is the arithmetic
  43 sum.
  44
  45 See also the %sub instruction.
  46
  47
  48 * %add/wr &lt;bit-l&gt;, &lt;bit-r&gt;
  49
  50 This is the real valued version of the %add instruction. The arguments
  51 are word indices of the operands. The right operand is added into the
  52 left operand.
  53
  54 See also the %sub/wr instruction.
  55
  56
  57 * %addi &lt;bit-l&gt;, &lt;imm&gt;, &lt;wid&gt;
  58
  59 This instruction adds the immediate value (no x or z bits) into the
  60 left vector. The imm value is limited to 16 significant bits, but it
  61 is zero extended to match any width.
  62
  63 * %and &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
  64
  65 Perform the bitwise AND of the two vectors, and store the result in
  66 the left vector. Each bit is calculated independent of other bits. AND
  67 means the following:
  68
  69         0 and ? --&gt; 0
  70         ? and 0 --&gt; 0
  71         1 and 1 --&gt; 1
  72         otherwise   x
  73
  74 * %assign/m &lt;memory-label&gt;, &lt;delay&gt;, &lt;bit&gt; (OBSOLETE)
  75
  76 This instruction does a non-blocking assignment to a bit in a memory
  77 from the specified thread register &lt;bit&gt;.  The memory bit is addressed
  78 by index register 3.  Bit address zero is the LSB of the first memory
  79 word.
  80
  81 * %assign/mv &lt;memory-label&gt;, &lt;delay&gt;, &lt;bit&gt;
  82
  83 the %assign/mv instruction assigns a vector value to a word in the
  84 labeled memory. The &lt;delay&gt; is the delay in simulation time to the
  85 assignment (0 for non-blocking assignment) and the &lt;bit&gt; is the base
  86 of the vector to write.
  87
  88 The width of the word is retrieved from index register 0.
  89
  90 The address of the word in the memory is from index register 3. The
  91 address is canonical form.
  92
  93 * %assign/v0 &lt;var-label&gt;, &lt;delay&gt;, &lt;bit&gt;
  94 * %assign/v0/d &lt;var-label&gt;, &lt;delayx&gt;, &lt;bit&gt;
  95
  96 The %assign/v0 instruction is a vector version of non-blocking
  97 assignment. The &lt;delay&gt; is the number of clock ticks in the future
  98 where the assignment should be schedule, and the &lt;bit&gt; is the base of
  99 the vector to be assigned to the destination. The vector width is in
 100 index register 0.
 101
 102 The %assign/v0/d variation puts the delay instead into an integer
 103 register that is given by the &lt;delayx&gt; value. This should not be 0, of
 104 course, because integer 0 is taken with the vector width.
 105
 106 The &lt;var-label&gt; references a .var object that can receive non-blocking
 107 assignments. For blocking assignments, see %set/v.
 108
 109 * %assign/v0x1 &lt;var-label&gt;, &lt;delay&gt;, &lt;bit&gt;
 110
 111 This is similar to the %assign/v0 instruction, but adds the index-1
 112 index register with the canonical index of the destination where the
 113 vector is to be written. This allows for part writes into the vector.
 114
 115 * %assign/wr &lt;vpi-label&gt;, &lt;delay&gt;, &lt;index&gt;
 116
 117 This instruction causes a non-blocking assign of the indexed value to
 118 the real object addressed by the &lt;vpi-label&gt; label.
 119
 120 * %assign/x0 &lt;var-label&gt;, &lt;delay&gt;, &lt;bit&gt; (OBSOLETE -- See %assign/v0x)
 121
 122 This does a non-blocking assignment to a functor, similar to the
 123 %assign instruction. The &lt;var-label&gt; identifies the base functor of
 124 the affected variable, and the &lt;delay&gt; gives the delay when the
 125 assignment takes place. The delay may be 0. The actual functor used is
 126 calculated by using &lt;var-label&gt; as a base, and indexing with the
 127 index[0] index register. This supports indexed assignment.
 128
 129 The &lt;bit&gt; is the address of the thread register that contains the bit
 130 value to assign.
 131
 132
 133 * %blend &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 134
 135 This instruction blends the bits of a vector into the destination in a
 136 manner like the expression (x ? &lt;a&gt; : &lt;b&gt;). The truth table is:
 137
 138         1  1 --&gt; 1
 139         0  0 --&gt; 0
 140         z  z --&gt; z
 141         x  x --&gt; x
 142         .... --&gt; x
 143
 144 In other words, if the bits are identical, then take that
 145 value. Otherwise, the value is x.
 146
 147 * %breakpoint
 148
 149 This instruction unconditionally breaks the simulator into the
 150 interactive debugger. The idea is to stop the simulator here and give
 151 the user a chance to display the state of the simulation using
 152 debugger commands.
 153
 154 This may not work on all platforms. If run-time debugging is compiled
 155 out, then this function is a no-op.
 156
 157 * %cassign/v &lt;var-label&gt;, &lt;bit&gt;, &lt;wid&gt;
 158
 159 Perform a continuous assign of a constant value to the target
 160 variable. This is similar to %set, but it uses the cassign port
 161 (port-1) of the signal functor instead of the normal assign, so the
 162 signal responds differently. See &quot;VARIABLE STATEMENTS&quot; in the
 163 README.txt file.
 164
 165
 166 * %cmp/u &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 167 * %cmp/s &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 168
 169 These instructions perform a generic comparison of two vectors of equal
 170 size. The &lt;bit-l&gt; and &lt;bit-r&gt; numbers address the least-significant
 171 bit of each vector, and &lt;wid&gt; is the width. If either operand is 0,
 172 1, 2 or 3 then it is taken to be a constant replicated to the selected
 173 width.
 174
 175 The results of the comparison go into bits 4, 5, 6 and 7:
 176
 177         4: eq  (equal)
 178         5: lt  (less than)
 179         6: eeq (case equal)
 180
 181 The eeq bit is set to 1 if all the bits in the vectors are exactly the
 182 same, or 0 otherwise. The eq bit is true if the values are logically
 183 the same. That is, x and z are considered equal. In other words the eq
 184 bit is the same as ``==&#039;&#039; and the eeq bit ``===&#039;&#039;.
 185
 186 The lt bit is 1 if the left vector is less then the right vector, or 0
 187 if greater then or equal to the right vector. It is the equivalent of
 188 the Verilog &lt; operator. Combinations of these three bits can be used
 189 to implement all the Verilog comparison operators.
 190
 191 The %cmp/u and %cmp/s differ only in the handling of the lt bit. The
 192 %cmp/u does an unsigned compare, whereas the %cmp/s does a signed
 193 compare. In either case, if either operand contains x or z, then lt
 194 bit gets the x value.
 195
 196
 197 * %cmp/wr &lt;bit-l&gt;, &lt;bit-r&gt;
 198
 199 [compare real values.]
 200
 201 * %cmp/ws &lt;bit-l&gt;, &lt;bit-r&gt;
 202 * %cmp/wu &lt;bit-l&gt;, &lt;bit-r&gt;
 203
 204 [compare signed/unsigned integer words.]
 205
 206 * %cmp/z &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 207 * %cmp/x &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 208
 209 These instructions are for implementing the casez and casex
 210 comparisons. These work similar to the %cmp/u instructions, except
 211 only an eq bit is calculated. These comparisons both treat z values in
 212 the left or right operand as don&#039;t care positions. The %cmp/x
 213 instruction will also treat x values in either operand as don&#039;t care.
 214
 215 Only bit 4 is set by these instructions.
 216
 217
 218 * %cvt/ir &lt;bit-l&gt;, &lt;bit-r&gt;
 219 * %cvt/ri &lt;bit-l&gt;, &lt;bit-r&gt;
 220 * %cvt/vr &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 221
 222 Copy a word from r to l, converting it from real to integer (ir) or
 223 integer to real (ri) in the process. The source and destination may
 224 be the same word address, leading to a convert in place.
 225
 226 The %cvt/vr opcode converts a real word &lt;bit-r&gt; to a thread vector
 227 starting at &lt;bit-l&gt; and with the width &lt;wid&gt;. Non-integer precision is
 228 lost in the conversion.
 229
 230 * %deassign &lt;var-label&gt;
 231
 232 Deactivate and disconnect a procedural continuous assignment to a
 233 variable. The &lt;var-label&gt; identifies the affected variable.
 234
 235 * %delay &lt;delay&gt;
 236
 237 This opcode pauses the thread, and causes it to be rescheduled for a
 238 time in the future. The &lt;amount&gt; is the number of the ticks in the
 239 future to reschedule, and is &gt;= 0. If the %delay is zero, then the
 240 thread yields the processor for another thread, but will be resumed in
 241 the current time step.
 242
 243 * %delayx &lt;idx&gt;
 244
 245 This is similar to the %delay opcode, except that the parameter
 246 selects an index register, which contains the actual delay. This
 247 supports run-time calculated delays.
 248
 249 * %disable &lt;scope-label&gt;
 250
 251 This instruction terminates threads that are part of a specific
 252 scope. The label identifies the scope in question, and the threads are
 253 the threads that are currently within that scope.
 254
 255
 256 * %div &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 257 * %div/s &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 258
 259 This instruction arithmetically divides the &lt;bit-l&gt; vector by the
 260 &lt;bit-r&gt; vector, and leaves the result in the &lt;bit-l&gt; vector. IF any of
 261 the bits in either vector are x or z, the entire result is x.
 262
 263 The %div/s instruction is the same as %div, but does signed division.
 264
 265
 266 * %div/wr &lt;bit-l&gt;, &lt;bit-r&gt;
 267
 268 This opcode divides the left operand by the right operand. If the
 269 right operand is 0, then the result is NaN.
 270
 271
 272 * %force/v &lt;label&gt;, &lt;bit&gt;, &lt;wid&gt;
 273
 274 Force a constant value to the target variable. This is similar to %set
 275 and %cassign/v, but it uses the force port (port-2) of the signal
 276 functor instead of the normal assign port (port-0), so the signal
 277 responds differently. See &quot;VARIABLE STATEMENTS&quot; and &quot;NET STATEMENTS&quot;
 278 in the README.txt file.
 279
 280 * %force/x0 &lt;label&gt;, &lt;bit&gt;, &lt;wid&gt;
 281
 282 Force a constant value to part target variable. This is similar to
 283 %set/x instruction, but it uses the force port (port-2) of the signal
 284 functor instead of the normal assign port (port-0), so the signal
 285 responds differently. See &quot;VARIABLE STATEMENTS&quot; and &quot;NET STATEMENTS&quot;
 286 in the README.txt file.
 287
 288 * %fork &lt;code-label&gt;, &lt;scope-label&gt;
 289
 290 This instruction is similar to %jmp, except that it creates a new
 291 thread to start executing at the specified address. The new thread is
 292 created and pushed onto the child stack.  It is also marked runnable,
 293 but is not necessarily started until the current thread yields.
 294
 295 The %fork instruction has no effect other then to push a child thread.
 296
 297 See also %join.
 298
 299
 300 * %inv &lt;bit&gt;, &lt;wid&gt;
 301
 302 Perform a bitwise invert of the vector starting at &lt;bit&gt;. The result
 303 replaces the input. Invert means the following, independently for each
 304 bit:
 305
 306         0  --&gt; 1
 307         1  --&gt; 0
 308         x  --&gt; x
 309         z  --&gt; x
 310
 311
 312 * %ix/get &lt;idx&gt;, &lt;bit&gt;, &lt;wid&gt;
 313
 314 This instruction loads a thread vector starting at &lt;bit&gt;, size &lt;wid&gt;,
 315 into the index register &lt;idx&gt;. The &lt;bit&gt; is the lsb of the value in
 316 thread bit space, and &lt;wid&gt; is the width of the vector.
 317
 318 The function converts the 4-value bits into a binary number, without
 319 sign extension. If any of the bits of the vector is x or z, then the
 320 index register gets the value 0.
 321
 322 The function also writes into bit 4 a 1 if any of the bits of the
 323 input vector are x or z. This is a flag that the 0 value written into
 324 the index register is really the result of calculating from unknown
 325 bits.
 326
 327         4: unknown value
 328         5: (reserved)
 329         6: (reserved)
 330
 331
 332 * %ix/load &lt;idx&gt;, &lt;value&gt;
 333
 334 This instruction loads an immediate value into the addressed index
 335 register. The index register holds numeric values, so the &lt;value&gt; is a
 336 number. The idx value selects the index register, and may be 0, 1, 2
 337 or 3. This is different from %ix/get, which loads the index register
 338 from a value in the thread bit vector.
 339
 340
 341 * %ix/add &lt;idx&gt;, &lt;value&gt;
 342 * %ix/sub &lt;idx&gt;, &lt;value&gt;
 343 * %ix/mul &lt;idx&gt;, &lt;value&gt;
 344
 345 This instruction adds, subtracts, or multiplies an immediate value to
 346 the addressed index register. The index register holds numeric values,
 347 so the &lt;value&gt; is a number. The &lt;idx&gt; value selects the index register,
 348 and may be 0, 1, 2 or 3.
 349
 350
 351 * %jmp &lt;code-label&gt;
 352
 353 The %jmp instruction performs an unconditional branch to a given
 354 location. The parameter is the label of the destination instruction.
 355
 356 * %jmp/[01xz] &lt;code-label&gt;, &lt;bit&gt;
 357
 358 This is a conditional version of the %jmp instruction. In this case,
 359 a single bit (addressed by &lt;bit&gt;) is tested. If it is one of the
 360 values in the part after the /, the jump is taken. For example:
 361
 362         %jmp/xz T_label, 8;
 363
 364 will jump to T_label if bit 8 is x or z.
 365
 366 * %join
 367
 368 This is the partner to %fork. This instruction causes the thread to
 369 wait for the top thread in the child stack to terminate, then
 370 continues. It has no effect in the current thread other then to wait
 371 until the top child is cleared.
 372
 373 It is an error to execute %join if there are no children in the child
 374 stack. Every %join in the thread must have a matching %fork that
 375 spawned off a child thread.
 376
 377 If the matching child instruction is still running, a %join suspends
 378 the calling thread until the child ends. If the child is already
 379 ended, then the %join does not block or yield the thread.
 380
 381 * %load/m &lt;bit&gt;, &lt;memory-label&gt; (OBSOLETE)
 382
 383 This instruction loads a value from a memory bit into the specified
 384 thread register bit. The memory bit is addressed by index register 3.
 385 Bit address zero is the LSB of the first memory word.  This
 386 instruction loads only a single bit.
 387
 388 * %load/mv &lt;bit&gt;, &lt;memory-label&gt;, &lt;wid&gt;
 389
 390 this instruction loads a word from the specified memory. The word
 391 address is in index register 3. The width should match the width of
 392 the memory word.
 393
 394 * %load/nx &lt;bit&gt;, &lt;vpi-label&gt;, &lt;idx&gt;
 395
 396 This instruction load a value from a .net object bit. Since .net
 397 objects don&#039;t really exist (they are only named indirection into the
 398 netlist) this instruction indexes into the .net list of bits.
 399
 400 * %load/v &lt;bit&gt;, &lt;functor-label&gt;, &lt;wid&gt;
 401
 402 This instruction loads a vector value from the given functor node into
 403 the specified thread register bit. The functor-label can refer to a
 404 .net, a .var or a .functor with a vector output. The entire vector,
 405 from the least significant up to &lt;wid&gt; bits, is loaded starting at
 406 thread bit &lt;bit&gt;. It is an error for the width to not match the vector
 407 width at the functor.
 408
 409 * %load/wr &lt;bit&gt;, &lt;vpi-label&gt;
 410
 411 This instruction reads a real value from the vpi-like object to a word
 412 register.
 413
 414 * %load/x &lt;bit&gt;, &lt;functor-label&gt;, &lt;idx&gt;
 415 * %load/x.p &lt;bit&gt;, &lt;functor-label&gt;, &lt;idx&gt;
 416
 417 This is an indexed load. It uses the contents of the specified index
 418 register to select a bit from a vector functor at &lt;functor-label&gt;. The
 419 bit is pulled from the indexed bit of the addressed functor and loaded
 420 into the destination thread bit. If the indexed value is beyond the
 421 width of the vector, then the result is X.
 422
 423 The %load/x.p is the same, but when the operation is done, it
 424 increments the specified index register. This provides a basic
 425 auto-increment feature.
 426
 427 * %loadi/wr &lt;bit&gt;, &lt;mant&gt;, &lt;exp&gt;
 428
 429 This opcode loads an immediate value, floating point, into the word
 430 register selected by &lt;bit&gt;. The mantissa is an unsigned integer value,
 431 up to 32 bits, that multiplied by 2**(&lt;exp&gt;-0x1000) to make a real
 432 value. The sign bit is OR-ed into the &lt;exp&gt; value at bit 0x2000, and
 433 is removed from the &lt;exp&gt; before calculating the real value.
 434
 435
 436 * %mod   &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 437 * %mod/s &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 438
 439 This instruction calculates the modulus %r of the left operand, and
 440 replaces the left operand with the result. The &lt;wid&gt; gives the width
 441 of the left and the right vectors, and the left vector is completely
 442 replaced with the result.
 443
 444 The /s form does signed %.
 445
 446 * %mov &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
 447
 448 This instruction copies a vector from one place in register space to
 449 another. The destination and source vectors are assumed to be the same
 450 width and non-overlapping. The &lt;dst&gt; may not be 0-3, but if the &lt;src&gt;
 451 is one of the 4 constant bits, the effect is to replicate the value
 452 into the destination vector. This is useful for filling a vector.
 453
 454
 455 * %mul &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 456
 457 This instruction multiplies the left vector by the right vector, the
 458 vectors having the width &lt;wid&gt;. If any of the bits of either vector
 459 are x or z, the result is x. Otherwise, the result is the arithmetic
 460 product.
 461
 462
 463 * %mul/wr &lt;bit-l&gt;, &lt;bit-r&gt;
 464
 465 This opcode multiplies two real words together. The result replaces
 466 the left operand.
 467
 468
 469 * %muli &lt;bit-l&gt;, &lt;imm&gt;, &lt;wid&gt;
 470
 471 This instruction is the same as %mul, but the second operand is an
 472 immediate value that is padded to the width of the result.
 473
 474
 475 * %nand &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
 476
 477 Perform the bitwise NAND of the two vectors, and store the result in
 478 the left vector. Each bit is calculated independent of other bits. NAND
 479 means the following:
 480
 481         0 and ? --&gt; 1
 482         ? and 0 --&gt; 1
 483         1 and 1 --&gt; 0
 484         otherwise   x
 485
 486
 487 * %nor &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
 488
 489 Perform the bitwise nor of the vectors. Each bit in the &lt;dst&gt; is
 490 combined with the corresponding bit in the source, according to the
 491 truth table:
 492
 493         1 nor ? --&gt; 0
 494         ? nor 1 --&gt; 0
 495         0 nor 0 --&gt; 1
 496         otherwise  x
 497
 498
 499 * %nor/r &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
 500
 501 The %nor/r instruction is a reduction nor. That is, the &lt;src&gt; is a
 502 vector with width, but the result is a single bit. The &lt;src&gt; vector is
 503 not affected by the operation unless the &lt;dst&gt; bit is within the
 504 vector. The result is calculated before the &lt;dst&gt; bit is written, so
 505 it is valid to place the &lt;dst&gt; within the &lt;src&gt;.
 506
 507 The actual operation performed is the inverted or of all the bits in
 508 the vector.
 509
 510
 511 * %or &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
 512
 513 Perform the bitwise or of the vectors. Each bit in the &lt;dst&gt; is
 514 combined with the corresponding bit in the source, according to the
 515 truth table:
 516
 517         1 or ? --&gt; 1
 518         ? or 1 --&gt; 1
 519         0 or 0 --&gt; 0
 520         otherwise  x
 521
 522
 523 * %or/r &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
 524
 525 This is a reduction version of the %or opcode. The &lt;src&gt; is a vector,
 526 and the &lt;dst&gt; is a writable scalar. The &lt;dst&gt; gets the value of the
 527 or of all the bits of the src vector.
 528
 529
 530 * %release/net &lt;functor-label&gt;
 531 * %release/reg &lt;functor-label&gt;
 532
 533 Release the force on the signal that is represented by the functor
 534 &lt;functor-label&gt;.  The force was previously activated with a %force/v
 535 statement.  If no force was active on this functor the statement does
 536 nothing. The %release/net sends to the labeled functor the release
 537 command with net semantics: the unforced value is propagated to the
 538 output of the signal after the release is complete. The %release/reg
 539 sends the release command with reg semantics: the signal holds its
 540 forced value until another value propagates through.
 541
 542 * %set/v &lt;var-label&gt;, &lt;bit&gt;, &lt;wid&gt;
 543
 544 This sets a vector to a variable, and is used to implement blocking
 545 assignments. The &lt;var-label&gt; identifies the variable to receive the
 546 new value. Once the set completes, the value is immediately available
 547 to be read out of the variable. The &lt;bit&gt; is the address of the thread
 548 register that contains the LSB of the vector, and the &lt;wid&gt; is the
 549 size of the vector. The width must exactly match the width of the
 550 signal.
 551
 552 * %set/mv &lt;memory-label&gt;, &lt;bit&gt;, &lt;wid&gt;
 553
 554 This sets a thread vector to a memory word. The &lt;memory-label&gt;
 555 addresses a memory device, and the &lt;bit&gt;,&lt;wid&gt; describe a vector to be
 556 written. Index register 3 contains the address of the word within the
 557 memory. The address (in canonical form) is precalculated and loaded
 558 into index register 3.
 559
 560
 561 * %set/wr &lt;vpi-label&gt;, &lt;bit&gt;
 562
 563 This instruction writes a real word to the specified VPI-like object.
 564
 565 * %set/x0 &lt;var-label&gt;, &lt;bit&gt;, &lt;wid&gt;
 566
 567 This sets the part of a signal vector, the address calculated by
 568 using the index register 0 to index the base within the vector of
 569 &lt;var-label&gt;. The destination must be a signal of some sort. Otherwise,
 570 the instruction will fail.
 571
 572 The addressing is canonical (0-based) so the compiler must figure out
 573 non-zero offsets, if any. The width is the width of the part being
 574 written. The other bits of the vector are not touched.
 575
 576 The index may be signed, and if less then 0, the beginning bits are
 577 not assigned. Also, if the bits go beyond the end of the signal, those
 578 bits are not written anywhere.
 579
 580
 581 * %shiftl/i0 &lt;bit&gt;, &lt;wid&gt;
 582
 583 This instruction shifts the vector left (towards more significant
 584 bits) by the amount in index register 0. The &lt;bit&gt; is the address of
 585 the lsb of the vector, and &lt;wid&gt; the width of the vector. The shift is
 586 done in place. Zero values are shifted in.
 587
 588 * %shiftr/i0 &lt;bit&gt;, &lt;wid&gt;
 589 * %shiftr/s/i0 &lt;bit&gt;, &lt;wid&gt;
 590
 591 This instruction shifts the vector right (towards the less significant
 592 bits) by the amount in the index register 0. The &lt;bit&gt; is the address
 593 of the lsb of the vector, and &lt;wid&gt; is the width of the vector. The
 594 shift is done in place.
 595
 596 %shiftr/i0 is an unsigned down shift, so zeros are shifted into the
 597 top bits. %shiftr/s/i0 is a signed shift, so the value is sign-extended.
 598
 599 * %sub &lt;bit-l&gt;, &lt;bit-r&gt;, &lt;wid&gt;
 600
 601 This instruction arithmetically subtracts the right vector out of the
 602 left vector. It accomplishes this by adding to the left vector 1 plus
 603 the 1s complement of the right vector. The carry value is dropped, and
 604 the result, placed in &lt;bit-l&gt;, is the subtraction of &lt;bit-r&gt; from the
 605 input &lt;bit-l&gt;. Both vectors have the same width. If any bits in either
 606 operand are x, then the entire result is x.
 607
 608 See also the %add instruction.
 609
 610 * %subi &lt;bit-l&gt;, &lt;imm&gt;, &lt;wid&gt;
 611
 612 This instruction arithmetically subtracts the immediate value from the
 613 left vector. The &lt;imm&gt; value is a 16bit unsigned value zero-extended to
 614 the &lt;wid&gt; of the left vector. The result replaces the left vector.
 615
 616 See also the %addi instruction.
 617
 618
 619 * %sub/wr &lt;bit-l&gt;, &lt;bit-r&gt;
 620
 621 This instruction operates on real values in word registers. The right
 622 indexed value is subtracted from the left indexed value, and the
 623 result placed in the left index.
 624
 625
 626 * %vpi_call &lt;name&gt; [, ...]
 627
 628 This instruction makes a call to a system task that was declared using
 629 VPI. The operands are compiled down to a vpiHandle for the call. The
 630 instruction contains only the vpiHandle for the call. See the vpi.txt
 631 file for more on system task/function calls.
 632
 633
 634 * %vpi_func &lt;name&gt;, &lt;dst&gt;, &lt;wid&gt; [, ...]
 635
 636 This instruction is similar to %vpi_call, except that it is for
 637 calling system functions. The difference here is the &lt;dst&gt; and &lt;wid&gt;
 638 parameters that specify where the return value is to go. The normal
 639 means that the VPI code uses to write the return value causes those
 640 bits to go here.
 641
 642
 643 * %wait &lt;functor-label&gt;
 644
 645 When a thread executes this instruction, it places itself in the
 646 sensitive list for the addressed functor. The functor holds all the
 647 threads that await the functor. When the defined sort of event occurs
 648 on the functor, a thread schedule event is created for all the threads
 649 in its list and the list is cleared.
 650
 651 * %xnor &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
 652
 653 This does a bitwise exclusive nor (~^) of the &lt;src&gt; and &lt;dst&gt; vector,
 654 and leaves the result in the &lt;dst&gt; vector. xnor is this:
 655
 656         0 xnor 0 --&gt; 1
 657         0 xnor 1 --&gt; 0
 658         1 xnor 0 --&gt; 0
 659         1 xnor 1 --&gt; 1
 660         otherwise    x
 661
 662
 663 * %xor &lt;dst&gt;, &lt;src&gt;, &lt;wid&gt;
 664
 665 This does a bitwise exclusive or (^) of the &lt;src&gt; and &lt;dst&gt; vector,
 666 and leaves the result in the &lt;dst&gt; vector. xor is this:
 667
 668         0 xnor 0 --&gt; 0
 669         0 xnor 1 --&gt; 1
 670         1 xnor 0 --&gt; 1
 671         1 xnor 1 --&gt; 0
 672         otherwise    x
 673
 674
 675 /*
 676  * Copyright (c) 2001-2003 Stephen Williams (steve@icarus.com)
 677  *
 678  *    This source code is free software; you can redistribute it
 679  *    and/or modify it in source code form under the terms of the GNU
 680  *    General Public License as published by the Free Software
 681  *    Foundation; either version 2 of the License, or (at your option)
 682  *    any later version.
 683  *
 684  *    This program is distributed in the hope that it will be useful,
 685  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 686  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 687  *    GNU General Public License for more details.
 688  *
 689  *    You should have received a copy of the GNU General Public License
 690  *    along with this program; if not, write to the Free Software
 691  *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
 692  */</pre>
 693
 694 </div>
 695 </body>
 696 </html>