docs/wiki/geda-vhdl_netlister_readme.html

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  13 <h1 class="sectionedit1" id="vhdl_netlister_readme">VHDL netlister README</h1>
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  15 <pre class="code">The VHDL backend
  16
  17 Written by Magnus Danielson and improved by Thomas Heidel
  18
  19
  20 A few things you have to care about:
  21
  22 1. In order to generate valid component declarations, you
  23    have to add an additional attribute to each pin.
  24    &quot;type=IN&quot; or &quot;type=OUT&quot; or &quot;type=INOUT&quot;
  25
  26 2. The &quot;device&quot; attribute must be unique to a symbol!
  27    The verilog symbols of the same type for example, have all
  28    the same device attribute and will therefore not work.
  29
  30 3. Make sure your component-library picks up the vhdl symbols instead
  31    of the verilog symbols  Library paths that show up last are searched
  32    first!</pre>
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