| blob | a547f7da31e042fb1e013e91f317e99ebfe4a590 |
1 v 20060906 1
2 C 31400 56100 1 0 0 resistor-1.sym
3 {
4 T 31600 56400 5 10 1 1 0 0 1
5 refdes=R?
6 T 31700 56500 5 10 0 0 0 0 1
7 device=RESISTOR
8 }
9 C 33600 56100 1 0 0 resistor-1.sym
10 {
11 T 33800 56400 5 10 1 1 0 0 1
12 refdes=R?
13 T 33900 56500 5 10 0 0 0 0 1
14 device=RESISTOR
15 }
16 C 36200 54200 1 0 0 resistor-1.sym
17 {
18 T 36400 54500 5 10 1 1 0 0 1
19 refdes=R?
20 T 36500 54600 5 10 0 0 0 0 1
21 device=RESISTOR
22 }
23 C 33500 52600 1 0 0 resistor-1.sym
24 {
25 T 33700 52900 5 10 1 1 0 0 1
26 refdes=R?
27 T 33800 53000 5 10 0 0 0 0 1
28 device=RESISTOR
29 }
30 C 31200 53900 1 0 0 resistor-1.sym
31 {
32 T 31400 54200 5 10 1 1 0 0 1
33 refdes=R?
34 T 31500 54300 5 10 0 0 0 0 1
35 device=RESISTOR
36 }
37 C 31400 54900 1 0 0 resistor-1.sym
38 {
39 T 31600 55200 5 10 1 1 0 0 1
40 refdes=R?
41 T 31700 55300 5 10 0 0 0 0 1
42 device=RESISTOR
43 }
44 C 31400 54900 1 0 0 resistor-1.sym
45 {
46 T 31600 55200 5 10 1 1 0 0 1
47 refdes=R?
48 T 31700 55300 5 10 0 0 0 0 1
49 device=RESISTOR
50 }
51 C 33600 55200 1 0 0 resistor-1.sym
52 {
53 T 33800 55500 5 10 1 1 0 0 1
54 refdes=R?
55 T 33900 55600 5 10 0 0 0 0 1
56 device=RESISTOR
57 }
58 C 35400 54100 1 0 0 resistor-1.sym
59 {
60 T 35600 54400 5 10 1 1 0 0 1
61 refdes=R?
62 T 35700 54500 5 10 0 0 0 0 1
63 device=RESISTOR
64 }
65 C 35400 54100 1 0 0 resistor-1.sym
66 {
67 T 35600 54400 5 10 1 1 0 0 1
68 refdes=R?
69 T 35700 54500 5 10 0 0 0 0 1
70 device=RESISTOR
71 }
72 C 35900 51700 1 0 0 resistor-1.sym
73 {
74 T 36100 52000 5 10 1 1 0 0 1
75 refdes=R?
76 T 36200 52100 5 10 0 0 0 0 1
77 device=RESISTOR
78 }
79 C 33000 51000 1 0 0 resistor-1.sym
80 {
81 T 33200 51300 5 10 1 1 0 0 1
82 refdes=R?
83 T 33300 51400 5 10 0 0 0 0 1
84 device=RESISTOR
85 }
86 C 33000 51000 1 0 0 resistor-1.sym
87 {
88 T 33200 51300 5 10 1 1 0 0 1
89 refdes=R?
90 T 33300 51400 5 10 0 0 0 0 1
91 device=RESISTOR
92 }
93 C 31000 51800 1 0 0 resistor-1.sym
94 {
95 T 31200 52100 5 10 1 1 0 0 1
96 refdes=R?
97 T 31300 52200 5 10 0 0 0 0 1
98 device=RESISTOR
99 }
100 C 31000 51800 1 0 0 resistor-1.sym
101 {
102 T 31200 52100 5 10 1 1 0 0 1
103 refdes=R?
104 T 31300 52200 5 10 0 0 0 0 1
105 device=RESISTOR
106 }
107 C 32800 53400 1 0 0 resistor-1.sym
108 {
109 T 33000 53700 5 10 1 1 0 0 1
110 refdes=R?
111 T 33100 53800 5 10 0 0 0 0 1
112 device=RESISTOR
113 }
114 C 33600 54000 1 0 0 resistor-1.sym
115 {
116 T 33800 54300 5 10 1 1 0 0 1
117 refdes=R?
118 T 33900 54400 5 10 0 0 0 0 1
119 device=RESISTOR
120 }
121 C 33000 55100 1 0 0 resistor-1.sym
122 {
123 T 33200 55400 5 10 1 1 0 0 1
124 refdes=R?
125 T 33300 55500 5 10 0 0 0 0 1
126 device=RESISTOR
127 }
128 C 32500 56200 1 0 0 resistor-1.sym
129 {
130 T 32700 56500 5 10 1 1 0 0 1
131 refdes=R?
132 T 32800 56600 5 10 0 0 0 0 1
133 device=RESISTOR
134 }
135 C 32800 57200 1 0 0 resistor-1.sym
136 {
137 T 33000 57500 5 10 1 1 0 0 1
138 refdes=R?
139 T 33100 57600 5 10 0 0 0 0 1
140 device=RESISTOR
141 }
142 C 35300 57300 1 0 0 resistor-1.sym
143 {
144 T 35500 57600 5 10 1 1 0 0 1
145 refdes=R?
146 T 35600 57700 5 10 0 0 0 0 1
147 device=RESISTOR
148 }
149 C 36600 56100 1 0 0 resistor-1.sym
150 {
151 T 36800 56400 5 10 1 1 0 0 1
152 refdes=R?
153 T 36900 56500 5 10 0 0 0 0 1
154 device=RESISTOR
155 }
156 C 36600 56100 1 0 0 resistor-1.sym
157 {
158 T 36800 56400 5 10 1 1 0 0 1
159 refdes=R?
160 T 36900 56500 5 10 0 0 0 0 1
161 device=RESISTOR
162 }
163 C 35000 55600 1 0 0 resistor-1.sym
164 {
165 T 35200 55900 5 10 1 1 0 0 1
166 refdes=R?
167 T 35300 56000 5 10 0 0 0 0 1
168 device=RESISTOR
169 }
170 C 33800 57000 1 0 0 resistor-1.sym
171 {
172 T 34000 57300 5 10 1 1 0 0 1
173 refdes=R?
174 T 34100 57400 5 10 0 0 0 0 1
175 device=RESISTOR
176 }
177 C 31400 57600 1 0 0 resistor-1.sym
178 {
179 T 31600 57900 5 10 1 1 0 0 1
180 refdes=R?
181 T 31700 58000 5 10 0 0 0 0 1
182 device=RESISTOR
183 }
184 C 30500 57000 1 0 0 resistor-1.sym
185 {
186 T 30700 57300 5 10 1 1 0 0 1
187 refdes=R?
188 T 30800 57400 5 10 0 0 0 0 1
189 device=RESISTOR
190 }
191 C 30500 57000 1 0 0 resistor-1.sym
192 {
193 T 30700 57300 5 10 1 1 0 0 1
194 refdes=R?
195 T 30800 57400 5 10 0 0 0 0 1
196 device=RESISTOR
197 }
198 C 29400 55300 1 0 0 resistor-1.sym
199 {
200 T 29600 55600 5 10 1 1 0 0 1
201 refdes=R?
202 T 29700 55700 5 10 0 0 0 0 1
203 device=RESISTOR
204 }
205 C 30100 53100 1 0 0 resistor-1.sym
206 {
207 T 30300 53400 5 10 1 1 0 0 1
208 refdes=R?
209 T 30400 53500 5 10 0 0 0 0 1
210 device=RESISTOR
211 }
212 C 32200 52400 1 0 0 resistor-1.sym
213 {
214 T 32400 52700 5 10 1 1 0 0 1
215 refdes=R?
216 T 32500 52800 5 10 0 0 0 0 1
217 device=RESISTOR
218 }
219 C 33200 51900 1 0 0 resistor-1.sym
220 {
221 T 33400 52200 5 10 1 1 0 0 1
222 refdes=R?
223 T 33500 52300 5 10 0 0 0 0 1
224 device=RESISTOR
225 }
226 C 34800 52000 1 0 0 resistor-1.sym
227 {
228 T 35000 52300 5 10 1 1 0 0 1
229 refdes=R?
230 T 35100 52400 5 10 0 0 0 0 1
231 device=RESISTOR
232 }
233 C 34600 53400 1 0 0 resistor-1.sym
234 {
235 T 34800 53700 5 10 1 1 0 0 1
236 refdes=R?
237 T 34900 53800 5 10 0 0 0 0 1
238 device=RESISTOR
239 }
240 C 32000 54500 1 0 0 resistor-1.sym
241 {
242 T 32200 54800 5 10 1 1 0 0 1
243 refdes=R?
244 T 32300 54900 5 10 0 0 0 0 1
245 device=RESISTOR
246 }
247 C 31300 52800 1 0 0 resistor-1.sym
248 {
249 T 31500 53100 5 10 1 1 0 0 1
250 refdes=R?
251 T 31600 53200 5 10 0 0 0 0 1
252 device=RESISTOR
253 }
254 C 30000 53900 1 0 0 resistor-1.sym
255 {
256 T 30200 54200 5 10 1 1 0 0 1
257 refdes=R?
258 T 30300 54300 5 10 0 0 0 0 1
259 device=RESISTOR
260 }
261 C 30400 55200 1 0 0 resistor-1.sym
262 {
263 T 30600 55500 5 10 1 1 0 0 1
264 refdes=R?
265 T 30700 55600 5 10 0 0 0 0 1
266 device=RESISTOR
267 }
268 C 29900 56400 1 0 0 resistor-1.sym
269 {
270 T 30100 56700 5 10 1 1 0 0 1
271 refdes=R?
272 T 30200 56800 5 10 0 0 0 0 1
273 device=RESISTOR
274 }
275 C 31400 55600 1 0 0 resistor-1.sym
276 {
277 T 31600 55900 5 10 1 1 0 0 1
278 refdes=R?
279 T 31700 56000 5 10 0 0 0 0 1
280 device=RESISTOR
281 }
282 C 34300 54700 1 0 0 resistor-1.sym
283 {
284 T 34500 55000 5 10 1 1 0 0 1
285 refdes=R?
286 T 34600 55100 5 10 0 0 0 0 1
287 device=RESISTOR
288 }
289 C 36500 52600 1 0 0 resistor-1.sym
290 {
291 T 36700 52900 5 10 1 1 0 0 1
292 refdes=R?
293 T 36800 53000 5 10 0 0 0 0 1
294 device=RESISTOR
295 }
296 C 34800 51200 1 0 0 resistor-1.sym
297 {
298 T 35000 51500 5 10 1 1 0 0 1
299 refdes=R?
300 T 35100 51600 5 10 0 0 0 0 1
301 device=RESISTOR
302 }
303 C 32100 51500 1 0 0 resistor-1.sym
304 {
305 T 32300 51800 5 10 1 1 0 0 1
306 refdes=R?
307 T 32400 51900 5 10 0 0 0 0 1
308 device=RESISTOR
309 }
310 C 30200 52400 1 0 0 resistor-1.sym
311 {
312 T 30400 52700 5 10 1 1 0 0 1
313 refdes=R?
314 T 30500 52800 5 10 0 0 0 0 1
315 device=RESISTOR
316 }
317 C 35400 56400 1 0 0 capacitor-1.sym
318 {
319 T 35600 56900 5 10 1 1 0 0 1
320 refdes=C?
321 T 35600 57100 5 10 0 0 0 0 1
322 device=CAPACITOR
323 T 35600 57300 5 10 0 0 0 0 1
324 symversion=0.1
325 }
326 C 36300 57000 1 0 0 capacitor-1.sym
327 {
328 T 36500 57500 5 10 1 1 0 0 1
329 refdes=C?
330 T 36500 57700 5 10 0 0 0 0 1
331 device=CAPACITOR
332 T 36500 57900 5 10 0 0 0 0 1
333 symversion=0.1
334 }
335 C 36900 57800 1 0 0 capacitor-1.sym
336 {
337 T 37100 58300 5 10 1 1 0 0 1
338 refdes=C?
339 T 37100 58500 5 10 0 0 0 0 1
340 device=CAPACITOR
341 T 37100 58700 5 10 0 0 0 0 1
342 symversion=0.1
343 }
344 C 38100 57700 1 0 0 capacitor-1.sym
345 {
346 T 38300 58200 5 10 1 1 0 0 1
347 refdes=C?
348 T 38300 58400 5 10 0 0 0 0 1
349 device=CAPACITOR
350 T 38300 58600 5 10 0 0 0 0 1
351 symversion=0.1
352 }
353 C 38400 56600 1 0 0 capacitor-1.sym
354 {
355 T 38600 57100 5 10 1 1 0 0 1
356 refdes=C?
357 T 38600 57300 5 10 0 0 0 0 1
358 device=CAPACITOR
359 T 38600 57500 5 10 0 0 0 0 1
360 symversion=0.1
361 }
362 C 38200 54800 1 0 0 capacitor-1.sym
363 {
364 T 38400 55300 5 10 1 1 0 0 1
365 refdes=C?
366 T 38400 55500 5 10 0 0 0 0 1
367 device=CAPACITOR
368 T 38400 55700 5 10 0 0 0 0 1
369 symversion=0.1
370 }
371 C 37200 54600 1 0 0 capacitor-1.sym
372 {
373 T 37400 55100 5 10 1 1 0 0 1
374 refdes=C?
375 T 37400 55300 5 10 0 0 0 0 1
376 device=CAPACITOR
377 T 37400 55500 5 10 0 0 0 0 1
378 symversion=0.1
379 }
380 C 36000 54800 1 0 0 capacitor-1.sym
381 {
382 T 36200 55300 5 10 1 1 0 0 1
383 refdes=C?
384 T 36200 55500 5 10 0 0 0 0 1
385 device=CAPACITOR
386 T 36200 55700 5 10 0 0 0 0 1
387 symversion=0.1
388 }
389 C 35700 53400 1 0 0 capacitor-1.sym
390 {
391 T 35900 53900 5 10 1 1 0 0 1
392 refdes=C?
393 T 35900 54100 5 10 0 0 0 0 1
394 device=CAPACITOR
395 T 35900 54300 5 10 0 0 0 0 1
396 symversion=0.1
397 }
398 C 37100 53400 1 0 0 capacitor-1.sym
399 {
400 T 37300 53900 5 10 1 1 0 0 1
401 refdes=C?
402 T 37300 54100 5 10 0 0 0 0 1
403 device=CAPACITOR
404 T 37300 54300 5 10 0 0 0 0 1
405 symversion=0.1
406 }
407 C 38100 54100 1 0 0 capacitor-1.sym
408 {
409 T 38300 54600 5 10 1 1 0 0 1
410 refdes=C?
411 T 38300 54800 5 10 0 0 0 0 1
412 device=CAPACITOR
413 T 38300 55000 5 10 0 0 0 0 1
414 symversion=0.1
415 }
416 C 39100 53600 1 0 0 capacitor-1.sym
417 {
418 T 39300 54100 5 10 1 1 0 0 1
419 refdes=C?
420 T 39300 54300 5 10 0 0 0 0 1
421 device=CAPACITOR
422 T 39300 54500 5 10 0 0 0 0 1
423 symversion=0.1
424 }
425 C 38500 52600 1 0 0 capacitor-1.sym
426 {
427 T 38700 53100 5 10 1 1 0 0 1
428 refdes=C?
429 T 38700 53300 5 10 0 0 0 0 1
430 device=CAPACITOR
431 T 38700 53500 5 10 0 0 0 0 1
432 symversion=0.1
433 }
434 C 37800 51900 1 0 0 capacitor-1.sym
435 {
436 T 38000 52400 5 10 1 1 0 0 1
437 refdes=C?
438 T 38000 52600 5 10 0 0 0 0 1
439 device=CAPACITOR
440 T 38000 52800 5 10 0 0 0 0 1
441 symversion=0.1
442 }
443 C 35200 52600 1 0 0 capacitor-1.sym
444 {
445 T 35400 53100 5 10 1 1 0 0 1
446 refdes=C?
447 T 35400 53300 5 10 0 0 0 0 1
448 device=CAPACITOR
449 T 35400 53500 5 10 0 0 0 0 1
450 symversion=0.1
451 }
452 C 37100 51300 1 0 0 capacitor-1.sym
453 {
454 T 37300 51800 5 10 1 1 0 0 1
455 refdes=C?
456 T 37300 52000 5 10 0 0 0 0 1
457 device=CAPACITOR
458 T 37300 52200 5 10 0 0 0 0 1
459 symversion=0.1
460 }
461 C 36600 50600 1 0 0 capacitor-1.sym
462 {
463 T 36800 51100 5 10 1 1 0 0 1
464 refdes=C?
465 T 36800 51300 5 10 0 0 0 0 1
466 device=CAPACITOR
467 T 36800 51500 5 10 0 0 0 0 1
468 symversion=0.1
469 }
470 C 38600 50700 1 0 0 capacitor-1.sym
471 {
472 T 38800 51200 5 10 1 1 0 0 1
473 refdes=C?
474 T 38800 51400 5 10 0 0 0 0 1
475 device=CAPACITOR
476 T 38800 51600 5 10 0 0 0 0 1
477 symversion=0.1
478 }
479 C 39200 51900 1 0 0 capacitor-1.sym
480 {
481 T 39400 52400 5 10 1 1 0 0 1
482 refdes=C?
483 T 39400 52600 5 10 0 0 0 0 1
484 device=CAPACITOR
485 T 39400 52800 5 10 0 0 0 0 1
486 symversion=0.1
487 }
488 C 39900 52900 1 0 0 capacitor-1.sym
489 {
490 T 40100 53400 5 10 1 1 0 0 1
491 refdes=C?
492 T 40100 53600 5 10 0 0 0 0 1
493 device=CAPACITOR
494 T 40100 53800 5 10 0 0 0 0 1
495 symversion=0.1
496 }
497 C 40200 54100 1 0 0 capacitor-1.sym
498 {
499 T 40400 54600 5 10 1 1 0 0 1
500 refdes=C?
501 T 40400 54800 5 10 0 0 0 0 1
502 device=CAPACITOR
503 T 40400 55000 5 10 0 0 0 0 1
504 symversion=0.1
505 }
506 C 39400 55100 1 0 0 capacitor-1.sym
507 {
508 T 39600 55600 5 10 1 1 0 0 1
509 refdes=C?
510 T 39600 55800 5 10 0 0 0 0 1
511 device=CAPACITOR
512 T 39600 56000 5 10 0 0 0 0 1
513 symversion=0.1
514 }
515 C 39700 55900 1 0 0 capacitor-1.sym
516 {
517 T 39900 56400 5 10 1 1 0 0 1
518 refdes=C?
519 T 39900 56600 5 10 0 0 0 0 1
520 device=CAPACITOR
521 T 39900 56800 5 10 0 0 0 0 1
522 symversion=0.1
523 }
524 C 38000 55900 1 0 0 capacitor-1.sym
525 {
526 T 38200 56400 5 10 1 1 0 0 1
527 refdes=C?
528 T 38200 56600 5 10 0 0 0 0 1
529 device=CAPACITOR
530 T 38200 56800 5 10 0 0 0 0 1
531 symversion=0.1
532 }
533 C 37300 56800 1 0 0 capacitor-1.sym
534 {
535 T 37500 57300 5 10 1 1 0 0 1
536 refdes=C?
537 T 37500 57500 5 10 0 0 0 0 1
538 device=CAPACITOR
539 T 37500 57700 5 10 0 0 0 0 1
540 symversion=0.1
541 }
542 C 34300 57900 1 0 0 capacitor-1.sym
543 {
544 T 34500 58400 5 10 1 1 0 0 1
545 refdes=C?
546 T 34500 58600 5 10 0 0 0 0 1
547 device=CAPACITOR
548 T 34500 58800 5 10 0 0 0 0 1
549 symversion=0.1
550 }
551 C 32900 58000 1 0 0 capacitor-1.sym
552 {
553 T 33100 58500 5 10 1 1 0 0 1
554 refdes=C?
555 T 33100 58700 5 10 0 0 0 0 1
556 device=CAPACITOR
557 T 33100 58900 5 10 0 0 0 0 1
558 symversion=0.1
559 }
560 C 31500 58100 1 0 0 capacitor-1.sym
561 {
562 T 31700 58600 5 10 1 1 0 0 1
563 refdes=C?
564 T 31700 58800 5 10 0 0 0 0 1
565 device=CAPACITOR
566 T 31700 59000 5 10 0 0 0 0 1
567 symversion=0.1
568 }
569 C 30300 58100 1 0 0 capacitor-1.sym
570 {
571 T 30500 58600 5 10 1 1 0 0 1
572 refdes=C?
573 T 30500 58800 5 10 0 0 0 0 1
574 device=CAPACITOR
575 T 30500 59000 5 10 0 0 0 0 1
576 symversion=0.1
577 }
578 C 29900 57600 1 0 0 capacitor-1.sym
579 {
580 T 30100 58100 5 10 1 1 0 0 1
581 refdes=C?
582 T 30100 58300 5 10 0 0 0 0 1
583 device=CAPACITOR
584 T 30100 58500 5 10 0 0 0 0 1
585 symversion=0.1
586 }
587 C 28900 57700 1 0 0 capacitor-1.sym
588 {
589 T 29100 58200 5 10 1 1 0 0 1
590 refdes=C?
591 T 29100 58400 5 10 0 0 0 0 1
592 device=CAPACITOR
593 T 29100 58600 5 10 0 0 0 0 1
594 symversion=0.1
595 }
596 C 28900 56900 1 0 0 capacitor-1.sym
597 {
598 T 29100 57400 5 10 1 1 0 0 1
599 refdes=C?
600 T 29100 57600 5 10 0 0 0 0 1
601 device=CAPACITOR
602 T 29100 57800 5 10 0 0 0 0 1
603 symversion=0.1
604 }
605 C 28900 55800 1 0 0 capacitor-1.sym
606 {
607 T 29100 56300 5 10 1 1 0 0 1
608 refdes=C?
609 T 29100 56500 5 10 0 0 0 0 1
610 device=CAPACITOR
611 T 29100 56700 5 10 0 0 0 0 1
612 symversion=0.1
613 }
614 C 29000 54400 1 0 0 capacitor-1.sym
615 {
616 T 29200 54900 5 10 1 1 0 0 1
617 refdes=C?
618 T 29200 55100 5 10 0 0 0 0 1
619 device=CAPACITOR
620 T 29200 55300 5 10 0 0 0 0 1
621 symversion=0.1
622 }
623 C 28800 53200 1 0 0 capacitor-1.sym
624 {
625 T 29000 53700 5 10 1 1 0 0 1
626 refdes=C?
627 T 29000 53900 5 10 0 0 0 0 1
628 device=CAPACITOR
629 T 29000 54100 5 10 0 0 0 0 1
630 symversion=0.1
631 }
632 C 29100 52400 1 0 0 capacitor-1.sym
633 {
634 T 29300 52900 5 10 1 1 0 0 1
635 refdes=C?
636 T 29300 53100 5 10 0 0 0 0 1
637 device=CAPACITOR
638 T 29300 53300 5 10 0 0 0 0 1
639 symversion=0.1
640 }
641 C 29000 51600 1 0 0 capacitor-1.sym
642 {
643 T 29200 52100 5 10 1 1 0 0 1
644 refdes=C?
645 T 29200 52300 5 10 0 0 0 0 1
646 device=CAPACITOR
647 T 29200 52500 5 10 0 0 0 0 1
648 symversion=0.1
649 }
650 C 30300 51600 1 0 0 capacitor-1.sym
651 {
652 T 30500 52100 5 10 1 1 0 0 1
653 refdes=C?
654 T 30500 52300 5 10 0 0 0 0 1
655 device=CAPACITOR
656 T 30500 52500 5 10 0 0 0 0 1
657 symversion=0.1
658 }
659 C 29600 50600 1 0 0 capacitor-1.sym
660 {
661 T 29800 51100 5 10 1 1 0 0 1
662 refdes=C?
663 T 29800 51300 5 10 0 0 0 0 1
664 device=CAPACITOR
665 T 29800 51500 5 10 0 0 0 0 1
666 symversion=0.1
667 }
668 C 31400 50800 1 0 0 capacitor-1.sym
669 {
670 T 31600 51300 5 10 1 1 0 0 1
671 refdes=C?
672 T 31600 51500 5 10 0 0 0 0 1
673 device=CAPACITOR
674 T 31600 51700 5 10 0 0 0 0 1
675 symversion=0.1
676 }
677 C 40000 50900 1 0 0 capacitor-1.sym
678 {
679 T 40200 51400 5 10 1 1 0 0 1
680 refdes=C?
681 T 40200 51600 5 10 0 0 0 0 1
682 device=CAPACITOR
683 T 40200 51800 5 10 0 0 0 0 1
684 symversion=0.1
685 }
686 C 40400 51700 1 0 0 capacitor-1.sym
687 {
688 T 40600 52200 5 10 1 1 0 0 1
689 refdes=C?
690 T 40600 52400 5 10 0 0 0 0 1
691 device=CAPACITOR
692 T 40600 52600 5 10 0 0 0 0 1
693 symversion=0.1
694 }
695 C 40400 55200 1 0 0 capacitor-1.sym
696 {
697 T 40600 55700 5 10 1 1 0 0 1
698 refdes=C?
699 T 40600 55900 5 10 0 0 0 0 1
700 device=CAPACITOR
701 T 40600 56100 5 10 0 0 0 0 1
702 symversion=0.1
703 }
704 C 40300 56700 1 0 0 capacitor-1.sym
705 {
706 T 40500 57200 5 10 1 1 0 0 1
707 refdes=C?
708 T 40500 57400 5 10 0 0 0 0 1
709 device=CAPACITOR
710 T 40500 57600 5 10 0 0 0 0 1
711 symversion=0.1
712 }
713 C 40200 57700 1 0 0 capacitor-1.sym
714 {
715 T 40400 58200 5 10 1 1 0 0 1
716 refdes=C?
717 T 40400 58400 5 10 0 0 0 0 1
718 device=CAPACITOR
719 T 40400 58600 5 10 0 0 0 0 1
720 symversion=0.1
721 }
722 C 39100 57500 1 0 0 capacitor-1.sym
723 {
724 T 39300 58000 5 10 1 1 0 0 1
725 refdes=C?
726 T 39300 58200 5 10 0 0 0 0 1
727 device=CAPACITOR
728 T 39300 58400 5 10 0 0 0 0 1
729 symversion=0.1
730 }
731 C 39200 56500 1 0 0 capacitor-1.sym
732 {
733 T 39400 57000 5 10 1 1 0 0 1
734 refdes=C?
735 T 39400 57200 5 10 0 0 0 0 1
736 device=CAPACITOR
737 T 39400 57400 5 10 0 0 0 0 1
738 symversion=0.1
739 }