2 P 1400 700 1088 700 1 0 0
4 T 1200 750 5 8 1 1 0 0 1
6 T 1200 650 5 8 0 1 0 2 1
8 T 1050 700 5 8 0 1 0 8 1
10 T 1050 700 9 8 0 1 0 6 1
13 P 0 1300 300 1300 1 0 0
15 T 200 1350 5 8 1 1 0 6 1
17 T 200 1250 5 8 0 1 0 8 1
19 T 350 1300 5 8 0 1 0 2 1
21 T 350 1300 9 8 0 1 0 0 1
26 T 200 950 5 8 1 1 0 6 1
28 T 200 850 5 8 0 1 0 8 1
30 T 350 900 5 8 0 1 0 2 1
32 T 350 900 9 8 0 1 0 0 1
37 T 200 550 5 8 1 1 0 6 1
39 T 200 450 5 8 0 1 0 8 1
41 T 350 500 5 8 0 1 0 2 1
43 T 350 500 9 8 0 1 0 0 1
48 T 200 150 5 8 1 1 0 6 1
50 T 200 50 5 8 0 1 0 8 1
52 T 350 100 5 8 0 1 0 2 1
54 T 350 100 9 8 0 1 0 0 1
57 T 1050 1150 5 10 0 0 0 0 1
59 T 1050 1350 5 10 0 0 0 0 1
61 T 1050 2350 5 10 0 0 0 0 1
63 T 500 1100 8 10 1 1 0 0 1
65 T 1050 1750 5 10 0 0 0 0 1
67 T 1050 1950 5 10 0 0 0 0 1
69 T 1050 2150 5 10 0 0 0 0 1
70 slotdef=2:9,10,11,12,13
71 T 1050 1550 5 10 0 0 0 0 1
73 T 1050 2550 5 10 0 0 0 0 1
75 T 1050 2750 5 10 0 0 0 0 1
76 description=2 OR gates with 4 inputs
77 T 1050 2950 5 10 0 0 0 0 1
78 documentation=http://www.semiconductors.philips.com/acrobat/datasheets/HEF4072B_CNV_3.pdf
79 T 450 200 9 10 1 0 0 0 1
81 L 300 1000 650 1000 3 0 0 0 -1 -1
82 L 300 400 650 400 3 0 0 0 -1 -1
83 L 300 400 300 0 3 0 0 0 -1 -1
84 L 300 1400 300 1000 3 0 0 0 -1 -1
85 A 650 850 450 270 71 3 0 0 0 -1 -1
86 A 650 550 450 20 70 3 0 0 0 -1 -1
87 A 50 700 395 310 100 3 0 0 0 -1 -1