docs/wiki/geda-verilog_netlister_readme.html

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  13 <h1 id="verilognetlisterreadme">Verilog netlister README</h1>
  14 <div class="level1">
  15 <pre class="code">Verilog netlister readme.
  16
  17 THIS IS FREE SOFTWARE, see the included file COPYING for more info.
  18
  19 Latest README:
  20
  21         This is the fifth release of the Verilog netlister for gEDA.
  22
  23         New in this release:
  24
  25         1) Escaped Verilog identifiers.
  26
  27         To facilitate board level simulations, the Verilog netlister now
  28 outputs `escaped&#039; Verilog identifiers for any net, port or instance name
  29 that does not appear to be a valid Verilog identifier.  In this way,
  30 chips with numbered pins can be netlisted and models constructed to run
  31 digital simulations of complete circuits.
  32
  33
  34                 Mike Jarabek
  35
  36
  37 ----- OLDER README.verilog&#039;s -----
  38
  39         This is the fourth release of the Verilog netlister for gEDA.
  40
  41         New in this release:
  42
  43         1) Multiple width wires.
  44
  45 How to use: (mostly taken from a previous readme... )
  46
  47        Here&#039;s how to proceed to make a schematic that can be netlisted
  48 to verilog.
  49
  50            1) Create your modules by the standard method, keep in mind
  51               that you must supply a `pin#&#039; attribute for each port
  52               you want to create in the generated verilog.  gmk_sym is
  53               useful for this.
  54
  55            2) Place each of your newly created modules on the
  56               schematic.  You may also place primitives from the
  57               `verilog&#039; symbol library.  Be sure to give a _unique_
  58               `uref&#039; to every symbol you place on the schematic,
  59               unless two symbols are actually different parts of the
  60               same module, and the pins listed on each symbol do not
  61               have any names in common.  Otherwise they will not get
  62               netlisted.
  63
  64            3) Connect nets between the modules you want.  Remember, if
  65               you want legible Verilog later, don&#039;t forget to name all
  66               your nets by attaching `label&#039; attributes to them.  For
  67               Multiple bit wires just use standard Verilog notation.
  68               The netlister will figure out which bit ordering you
  69               want.  Be sure to have at least one net labeled with the
  70               complete range expression, otherwise the netlister will
  71               guess at whether you wanted net[15:0] or net[0:15] in
  72               your declarations.  Any inconsistent ranges will be
  73               reported as a warning.  Strings that appear to be
  74               invalid Verilog identifiers will be printed with a
  75               warning, but otherwise ignored. (If you get a warning
  76               for a valid Verilog identifier, please post a bug
  77               report!)
  78
  79            4) Insert IPAD&#039;s, OPAD&#039;s, and IOPAD&#039;s for all the nets you
  80               want to be visible in the module declaration statement.
  81               It is especially important to make sure that the nets
  82               you hook up to the pads are named, as the net names
  83               could change from run to run, that&#039;s a bad thing. (I/O
  84               pads would be a good place to put the aformentionned
  85               full range expressions.  Range expressions on I/O pads
  86               are ignored when outputting the module declaration, but
  87               they are used in figuring out the final bit ranges.)
  88               Every pad must have a unique uref, otherwise the
  89               netlister will get confused.
  90
  91            5) Add an unattached attribute `module_name=Your_Module&#039;
  92               somewhere on the schematic, near the title block is
  93               good.  This will name the generated Verilog module
  94               `Your_Module&#039;.
  95
  96            6) Save your design.
  97
  98            7) Run the schematic through the netlister:
  99
 100                   gnetlist -g verilog -o output.v schematic.sch
 101
 102            7a) Check the output for correctness, _especially_ if you got
 103                any warnings. (There should be no warnings.)
 104
 105            8) Feed the netlist to your favorite simulator/synthesis tool.
 106
 107
 108                                         Mike Jarabek
 109
 110
 111         This is the third release of the Verilog netlister for geda.
 112
 113         Fixed in this release:
 114
 115         1) Netlister no longer barfs if there are no
 116            Input/Output/InOut ports on the module.
 117
 118         2) Module instantiation code much improved/cleaned up, mostly
 119            due to g_netlist.c patch.
 120
 121         New in this release:
 122
 123         1) A whole wack-load of symbols, I created a C program that
 124            generates n-input versions of and, nand, or, nor, xor, and
 125            xnor symbols
 126
 127         2) Modules instantiated with positional port connections.
 128            Just add the attribute `VERILOG_PORTS=POSITIONAL&#039; to your
 129
 130           symbol file as an unattached attribute, or attach it to the
 131            symbol on the schematic.
 132
 133         3) Added bufif?, notif?, not and buf symbols.
 134
 135         4) Added example of positional port module instantiation to
 136            the example schematic
 137
 138         5) Added 7447 example schematic
 139
 140         Coming:
 141
 142         1) Module instantiation parameters. (probably by an attribute)
 143
 144
 145         Included in this tar-ball are three patch files against the
 146         19990705 version of gEDA.  Apply g_netlist.c.diff and
 147         g_register.c.diff to the files in gnetlist/src/ and
 148         gnetlist.scm.diff to gnetlist.scm in the gnetlist/scheme
 149         directory. You may have to regenerate prototype.h, or manually
 150         patch it. Replace the symbols in the sym/verilog directory
 151         with the symbols in this distribution. (I have modified all of
 152         the symbols to use the new unattached attribute convention for
 153         device et al.) (if you have applied the patch I sent to the
 154         mailing list that fixes netlisting a module with no ports, you
 155         may have trouble applying the gnetlist.scm.diff patch.) Don&#039;t
 156         forget to do a `make all install&#039; after applying the patches.
 157
 158         Once again, to netlist the example schematics to verilog type:
 159         (Assuming gnetlist has been patched and is properly installed.)
 160
 161         gnetlist -g verilog -o test.v examples/sch/test.sch
 162
 163         or
 164
 165         gnetlist -g verilog -o 7447.v examples/sch/7447.sch
 166
 167
 168 (This README was from 19990629)
 169 Verilog netlister readme.
 170
 171 THIS IS FREE SOFTWARE, see the included file COPYING for more info.
 172
 173         This is the second release of the Verilog netlister for geda.
 174
 175         Fixed in this release:
 176
 177         1) The last comma in the argument list to instantiations and
 178            module definitions is now suppressed
 179
 180         2) Better handling of `special&#039; components has been added
 181
 182         New in this release:
 183
 184         1) Continuous assignments to 1&#039;b0 and 1&#039;b1 can now be
 185            generated by connecting the `high&#039; or `low&#039; symbol to a
 186            net.
 187
 188                                 Mike Jarabek
 189                                 mjarabek@playground.net
 190
 191
 192
 193 --
 194
 195
 196         This the verilog netlister for gEDA.  Included in the tarball
 197 are several diff files against the 19990327 gEDA distribution.  All of
 198 the patches apply to the gnetlist subirectory.  You should be able to
 199 apply them with `patch -p1&#039;.
 200
 201       The netlister has its limitations:  (most of these will
 202 eventually get fixed, I hope..)
 203
 204            1) Components connected by reference, (i.e. by having named
 205               net stubs attached to pins, but not conected by a
 206               continuous line) create duplicate entries in the wire
 207               declaration section of the verilog code.
 208
 209            2) Multiple width wires don&#039;t work.  (Busses will help
 210               this)
 211
 212            3) There is no way to force a signal to 1,0,z,x (yet).
 213
 214            4) Some scheme code needs to be improved. (Mainly the
 215               classification code, it inserts `()&#039; elements into the
 216               output lists. (I should know how to fix this in a day or
 217               two.. too bad I never got a scheme course before..))
 218
 219            5) I don&#039;t know if this will work on multiple page schematics.
 220
 221            6) The top level module is outputted with the same name
 222               every time, I don&#039;t currently think there is a way to
 223               get at the name of the top level schematic.
 224
 225
 226       The netlister does some neat things:
 227
 228
 229            1) It outputs a verilog module with proper port
 230               declarations, outputs are declared as outputs, inputs
 231               are declared as inputs, and bidirectional signals are
 232               declared as inouts.
 233
 234            2) All nets that are found on the design are declared as
 235               wires. (This is to allow for net attributes later to
 236               declare wand&#039;s and such)
 237
 238            3) Any components placed on the schematic that are given
 239               uref attributes create a verilog instantiation for the
 240               name of the module as stored in the `device&#039; attribute,
 241               the instatiated name is given as the `uref&#039; attribute.
 242
 243            4) All connections into and out of instantiated modules are
 244               made by name, and not by order, because I can&#039;t be sure
 245               that the order will be right coming off the schematic.
 246               (anyway, that&#039;s better for the long run.)
 247
 248            5) A comment is inserted at the top of the module to say
 249               that the file was automatically generated.
 250
 251
 252
 253        Here&#039;s how to proceed to make a schematic that can be netlisted
 254 to verilog.
 255
 256            1) Create your modules by the standard method, keep in mind
 257               that you must supply a `pin#&#039; attribute for each port
 258               you want to create in the generated verilog.  gmk_sym is
 259               useful for this (with the patch to allow ascii pin names).
 260
 261            2) Place each of your newly created modules on the
 262               schematic
 263
 264            3) Connect nets between the modules you want.  Remember, if
 265               you want legible verilog later, don&#039;t forget to name all
 266               your nets by attaching `label&#039; attributes to them.
 267
 268            4) Insert IPAD&#039;s, OPAD&#039;s, and IOPAD&#039;s for all the nets you
 269               want to be visible in the module declaration statement.
 270               It is especially important to make sure that the nets
 271               you hook up to the pads are named, as the net names
 272               could change from run to run, that&#039;s a bad thing.
 273
 274            5) Save your design.
 275
 276            6) Run the schematic through the netlister:
 277
 278                   gnetlist -g verilog -o output.v schematic.sch
 279
 280            6a) Edit the output file to have the right module name, and
 281                to remove any duplicate wires.
 282
 283
 284     There is an example schematic in the schematic directory, and a
 285     copy of the verilog netlist generated.
 286
 287 The mechanics:
 288
 289     The I/O ports for the module are detected by enumerating all of
 290     the nets attached to any symbol bearing the device name of `IPAD&#039;,
 291     `OPAD&#039;, or `IOPAD&#039;.  If you name one of your blocks with that
 292     name, don&#039;t be surprised if you find `extra&#039; ports in the module
 293     declaration.
 294
 295     The wires are declared by walking through the list of nets
 296     returned by the function that I patched into gnetlist.  This is
 297     the source of the duplicate wire declarations.  This should
 298     probably get fixed when `net_is_duplicate&#039; gets set for
 299     connections made by reference.
 300
 301     Module instantiations are created by enumerating the pins found on
 302     a symbol and connecting the nets found to the pins.  If your block
 303     has spelling errors, then the module instantiation won&#039;t work.
 304     You will have to manually trace back to find the error.
 305
 306
 307                                 Mike Jarabek
 308
 309
 310
 311 ------------ Below is the previous version README -------------------
 312
 313 Verilog netlister readme.
 314
 315 THIS IS FREE SOFTWARE, see the included file COPYING for more info.
 316
 317
 318         This the verilog netlister for gEDA.  Included in the tarball
 319 are several diff files against the 19990327 gEDA distribution.  All of
 320 the patches apply to the gnetlist subirectory.  You should be able to
 321 apply them with `patch -p1&#039;.
 322
 323 [ editor&#039;s note, if you are reading this file in a gEDA dist, then all
 324   the required patching and integration is already done ]
 325
 326       The netlister has its limitations:  (most of these will
 327 eventually get fixed, I hope..)
 328
 329            1) Components connected by reference, (i.e. by having named
 330               net stubs attached to pins, but not conected by a
 331               continuous line) create duplicate entries in the wire
 332               declaration section of the verilog code.
 333
 334            2) Multiple width wires don&#039;t work.  (Busses will help
 335               this)
 336
 337            3) There is no way to force a signal to 1,0,z,x (yet).
 338
 339            4) Some scheme code needs to be improved. (Mainly the
 340               classification code, it inserts `()&#039; elements into the
 341               output lists. (I should know how to fix this in a day or
 342               two.. too bad I never got a scheme course before..))
 343
 344            5) I don&#039;t know if this will work on multiple page schematics.
 345
 346            6) The top level module is outputted with the same name
 347               every time, I don&#039;t currently think there is a way to
 348               get at the name of the top level schematic.
 349
 350
 351       The netlister does some neat things:
 352
 353
 354            1) It outputs a verilog module with proper port
 355               declarations, outputs are declared as outputs, inputs
 356               are declared as inputs, and bidirectional signals are
 357               declared as inouts.
 358
 359            2) All nets that are found on the design are declared as
 360               wires. (This is to allow for net attributes later to
 361               declare wand&#039;s and such)
 362
 363            3) Any components placed on the schematic that are given
 364               uref attributes create a verilog instantiation for the
 365               name of the module as stored in the `device&#039; attribute,
 366               the instatiated name is given as the `uref&#039; attribute.
 367
 368            4) All connections into and out of instantiated modules are
 369               made by name, and not by order, because I can&#039;t be sure
 370               that the order will be right coming off the schematic.
 371               (anyway, that&#039;s better for the long run.)
 372
 373            5) A comment is inserted at the top of the module to say
 374               that the file was automatically generated.
 375
 376
 377
 378        Here&#039;s how to proceed to make a schematic that can be netlisted
 379 to verilog.
 380
 381            1) Create your modules by the standard method, keep in mind
 382               that you must supply a `pin#&#039; attribute for each port
 383               you want to create in the generated verilog.  gmk_sym is
 384               useful for this (with the patch to allow ascii pin names).
 385
 386            2) Place each of your newly created modules on the
 387               schematic
 388
 389            3) Connect nets between the modules you want.  Remember, if
 390               you want legible verilog later, don&#039;t forget to name all
 391               your nets by attaching `label&#039; attributes to them.
 392
 393            4) Insert IPAD&#039;s, OPAD&#039;s, and IOPAD&#039;s for all the nets you
 394               want to be visible in the module declaration statement.
 395               It is especially important to make sure that the nets
 396               you hook up to the pads are named, as the net names
 397               could change from run to run, that&#039;s a bad thing.
 398
 399            5) Save your design.
 400
 401            6) Run the schematic through the netlister:
 402
 403                   gnetlist -g verilog -o output.v schematic.sch
 404
 405            6a) Edit the output file to have the right module name, and
 406                to remove any duplicate wires.
 407
 408
 409     There is an example schematic in the schematic directory, and a
 410     copy of the verilog netlist generated.
 411
 412 The mechanics:
 413
 414     The I/O ports for the module are detected by enumerating all of
 415     the nets attached to any symbol bearing the device name of `IPAD&#039;,
 416     `OPAD&#039;, or `IOPAD&#039;.  If you name one of your blocks with that
 417     name, don&#039;t be surprised if you find `extra&#039; ports in the module
 418     declaration.
 419
 420     The wires are declared by walking through the list of nets
 421     returned by the function that I patched into gnetlist.  This is
 422     the source of the duplicate wire declarations.  This should
 423     probably get fixed when `net_is_duplicate&#039; gets set for
 424     connections made by reference.
 425
 426     Module instantiations are created by enumerating the pins found on
 427     a symbol and connecting the nets found to the pins.  If your block
 428     has spelling errors, then the module instantiation won&#039;t work.
 429     You will have to manually trace back to find the error.
 430
 431
 432                                 Mike Jarabek</pre>
 433
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 435 </body>
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