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  28 <h1><a name="icarus_attribute_naming_conventions" id="icarus_attribute_naming_conventions">Icarus Attribute Naming Conventions</a></h1>
  29 <div class="level1">
  30 <pre class="code">ATTRIBUTE NAMING CONVENTIONS
  31
  32 Attributes that are specific to Icarus Verilog, and are intended to be
  33 of use to programmers, start with the prefix &quot;ivl_&quot;.
  34
  35 Attributes with the &quot;_ivl_&quot; prefix are set aside for internal
  36 use. They may be generated internally by the compiler. They need not
  37 be documented here.
  38
  39 ATTRIBUTES TO CONTROL SYNTHESIS
  40
  41 The following is a summary of Verilog attributes that Icarus Verilog
  42 understands within Verilog source files to control synthesis
  43 behavior. This section documents generic synthesis attributes. For
  44 target specific attributes, see target specific documentation.
  45
  46 These attributes only effect the behavior of the synthesizer. For
  47 example, the ivl_combinational will not generate an error message
  48 if the Verilog is being compiled for simulation. (It may generate a
  49 warning.)
  50
  51
  52 * Attributes for &quot;always&quot; and &quot;initial&quot; statements
  53
  54 (* ivl_combinational *)
  55
  56     This attribute tells the compiler that the statement models
  57     combinational logic. If the compiler finds that it cannot make
  58     combinational logic out of a marked always statement, it will
  59     report an error.
  60
  61     This attribute can be used to prevent accidentally inferring
  62     latches or flip-flops where the user intended combinational
  63     logic.
  64
  65 (* ivl_synthesis_on *)
  66
  67     This attribute tells the compiler that the marked always statement
  68     is synthesizable. The compiler will attempt to synthesize the
  69     code in the marked &quot;always&quot; statement. If it cannot in any way
  70     synthesize it, then it will report an error.
  71
  72 (* ivl_synthesis_off *)
  73
  74     If this value is attached to an &quot;always&quot; statement, then the
  75     compiler will *not* synthesize the &quot;always&quot; statement. This can be
  76     used, for example, to mark embedded test bench code.
  77
  78
  79 * Attributes for modules
  80
  81 (* ivl_synthesis_cell *)
  82
  83     If this value is attached to a module during synthesis, that
  84     module will be considered a target architecture primitive, and
  85     its interior will not be synthesized further.  The module can
  86     therefore hold a model for simulation purposes.
  87
  88
  89 * Attributes for signals (wire/reg/integer/tri/etc.)
  90
  91 (* PAD = &quot;&lt;pad assignment list&gt;&quot; *)
  92
  93     If this attribute is attached to a signal that happens to be a
  94     root module port, then targets that support it will use the string
  95     value as a list of pin assignments for the port/signal. The format
  96     is a comma separated list of location tokens, with the format of
  97     the token itself defined by the back-end tools in use.
  98
  99 * Other Attributes
 100
 101 [ none defined yet ]
 102
 103
 104 MISC
 105
 106 (* _ivl_schedule_push *)
 107
 108     If this attribute is attached to a thread object (always or
 109     initial statement) then the vvp code generator will generate code
 110     that causes the scheduler to push this thread at compile time. The
 111     compiler may internally add this attribute to always statements if
 112     it detects that it is combinational. This helps resolve time-0
 113     races.</pre>
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