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  15 <h1 class="sectionedit307"><a name="icarus_attribute_naming_conventions" id="icarus_attribute_naming_conventions">Icarus Attribute Naming Conventions</a></h1>
  16 <div class="level1">
  17 <pre class="code">ATTRIBUTE NAMING CONVENTIONS
  18
  19 Attributes that are specific to Icarus Verilog, and are intended to be
  20 of use to programmers, start with the prefix &quot;ivl_&quot;.
  21
  22 Attributes with the &quot;_ivl_&quot; prefix are set aside for internal
  23 use. They may be generated internally by the compiler. They need not
  24 be documented here.
  25
  26 ATTRIBUTES TO CONTROL SYNTHESIS
  27
  28 The following is a summary of Verilog attributes that Icarus Verilog
  29 understands within Verilog source files to control synthesis
  30 behavior. This section documents generic synthesis attributes. For
  31 target specific attributes, see target specific documentation.
  32
  33 These attributes only effect the behavior of the synthesizer. For
  34 example, the ivl_combinational will not generate an error message
  35 if the Verilog is being compiled for simulation. (It may generate a
  36 warning.)
  37
  38
  39 * Attributes for &quot;always&quot; and &quot;initial&quot; statements
  40
  41 (* ivl_combinational *)
  42
  43     This attribute tells the compiler that the statement models
  44     combinational logic. If the compiler finds that it cannot make
  45     combinational logic out of a marked always statement, it will
  46     report an error.
  47
  48     This attribute can be used to prevent accidentally inferring
  49     latches or flip-flops where the user intended combinational
  50     logic.
  51
  52 (* ivl_synthesis_on *)
  53
  54     This attribute tells the compiler that the marked always statement
  55     is synthesizable. The compiler will attempt to synthesize the
  56     code in the marked &quot;always&quot; statement. If it cannot in any way
  57     synthesize it, then it will report an error.
  58
  59 (* ivl_synthesis_off *)
  60
  61     If this value is attached to an &quot;always&quot; statement, then the
  62     compiler will *not* synthesize the &quot;always&quot; statement. This can be
  63     used, for example, to mark embedded test bench code.
  64
  65
  66 * Attributes for modules
  67
  68 (* ivl_synthesis_cell *)
  69
  70     If this value is attached to a module during synthesis, that
  71     module will be considered a target architecture primitive, and
  72     its interior will not be synthesized further.  The module can
  73     therefore hold a model for simulation purposes.
  74
  75
  76 * Attributes for signals (wire/reg/integer/tri/etc.)
  77
  78 (* PAD = &quot;&lt;pad assignment list&gt;&quot; *)
  79
  80     If this attribute is attached to a signal that happens to be a
  81     root module port, then targets that support it will use the string
  82     value as a list of pin assignments for the port/signal. The format
  83     is a comma separated list of location tokens, with the format of
  84     the token itself defined by the back-end tools in use.
  85
  86 * Other Attributes
  87
  88 [ none defined yet ]
  89
  90
  91 MISC
  92
  93 (* _ivl_schedule_push *)
  94
  95     If this attribute is attached to a thread object (always or
  96     initial statement) then the vvp code generator will generate code
  97     that causes the scheduler to push this thread at compile time. The
  98     compiler may internally add this attribute to always statements if
  99     it detects that it is combinational. This helps resolve time-0
 100     races.</pre>
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