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34 NAME
35 Covered - Verilog Code Coverage Analyzer
37 SYNTAX
43 DESCRIPTION
44 Covered is a Verilog code coverage analysis tool that can be useful for
45 determining how well a diagnostic test suite is covering the design
46 under test. Covered reads in the Verilog design files and a VCD or LXT
47 formatted dumpfile from a diagnostic run and generates a database file
48 called a Coverage Description Database (CDD) file, using the score com-
49 mand. This file can be merged with other CDD files from the same
50 design to create accummulated coverage, using the merge command. Once
51 a CDD file is created, the user can use Covered to generate various
52 human-readable coverage reports in an ASCII format or use Covered’s GUI
53 to interactively look at coverage results, using the report command.
54 Additionally, as part of Covered’s score command, race condition possi-
55 bilities are found in the design files and can be either ignored,
56 flagged as warnings or flagged as errors. By specifying race condi-
57 tions as errors, Covered can also be used as a race condition checker.
59 GLOBAL OPTIONS
60 These options are placed immediately after the keyword covered in the
61 command-line. They can be used for any command (with the exception of
62 -v and -h) and have the same effect in each case.
64 -D Debug. Display information helpful for debugging tool problems.
65 Note: This option is now only available when covered is built
66 with the --enable-debug configuration option.
68 -h Help. Display this usage information.
70 -Q Quiet mode. Causes all output to be suppressed.
72 -v Version. Display current Covered version.
74 COMMANDS
75 score Parses Verilog files and VCD/LXT dumpfiles to create database
76 file used for merging and reporting.
78 merge Merges two database files into one.
80 report Generates human-readable coverage reports from database file or
81 starts the coverage report GUI.
83 SCORE COMMAND
84 The following options are valid for the score command:
86 -D define_name
87 Defines the specified name to 1.
89 -D define_name=value
90 Defines the specified name to the specified value.
92 -e block_name
93 Name of module, task, function or named begin/end block to not
94 score. Causes all subblocks in the Verilog tree under this
95 block to also not be scored.
97 -ea Excludes all always blocks from being considered for coverage.
99 -ec Excludes all continuous assignments from being considered for
100 coverage.
102 -ei Excludes all initial blocks from being considered for coverage.
104 -F module_name=(in_expr,)out_expr
105 Indicates to the parser where to find the FSM located in module
106 module_name which has an input state expression called in_expr
107 and output state expression called out_expr. If in_expr is not
108 specified, out_expr is used as both the input and output state
109 expression.
111 -f filename
112 Name of file containing additional arguments to parse.
114 -h Displays this help information.
116 -I directory
117 Directory to find included Verilog files.
119 -i instance_name
120 Verilog hierarchical reference to the module that is at the top
121 of the tree to be scored. This option is necessary if module to
122 verify coverage is not the top-level module in the design. If
123 not specified, -t value is used.
125 -lxt filename
126 Name of LXT/LXT2 dumpfile to score design with. If this or the
127 -vcd option is not used, Covered will only create an initial CDD
128 file from the design and will not attempt to score the design.
130 -o database
131 Name of database to write coverage information to. If not spec-
134 -p filename
135 Overrides default filename used to store intermediate preproces-
136 sor output.
138 -P parameter_scope=value
139 Performs a defparam on the specified parameter with value.
141 -r(S|W|E)
142 Specifies action to take when race condition checking finds
143 problems in design (-rS = Silent, -rW = Warning, -rE = Error).
145 -S Outputs simulation statistics after simulation has completed.
146 This information is currently only useful for the developers of
147 Covered.
149 -t top-level module
150 Specifies the module name of the top-most module that will be
151 measured. Note that this module does not need to be the
152 top-most module in the simulator. This field is required for
153 all calls to the score command.
155 -ts number
156 When scoring occurs, this option allows the user to see how far
157 the simulator has progressed by outputting the current timestep
158 to standard output. The value of number specifies how many
159 timesteps are allowed to be simulated before outputting the cur-
160 rent timestep (results in less calls to output stream).
162 -T min|typ|max
163 Specifies which value to use when encountering a delay expres-
164 sion in the form: min:typ:max. If this option is not speci-
165 fied, ’typ’ select is used by default.
167 -v filename
168 Name of specific Verilog file to score.
170 -vcd filename
171 Name of VCD dumpfile to score design with. If this or the -lxt
172 option is not used, Covered will only create an initial CDD file
173 from the design and will not attempt to score the design.
175 -y directory
176 Directory to find unspecified Verilog files.
178 +libext+.extension(+.extension)*+
179 Extensions of Verilog files to allow in scoring.
181 MERGE COMMAND
182 The following options are valid for the merge command:
184 -h Displays this help information.
186 -o filename
187 File to output new database to. If this argument is not speci-
188 fied, the existing_database is used as the output database name.
190 REPORT COMMAND
191 The following options are valid with the report command:
193 -c If -v is specified, displays covered line, toggle and combina-
194 tional cases. Default is to display uncovered information.
196 -d (s|d|v)
197 Level of detail to provide in coverage report information (s =
198 summary, d = detailed, v = verbose). Default is summary.
200 -h Displays this help information.
202 -i Provides coverage information for instances instead of module.
204 -m [l][t][c][f][r]
205 Type(s) of metrics to report. Default is ltcf.
207 -o filename
208 File to output report information to. Default is standard out-
209 put.
211 -v Deprecated. Replaced by ’-d d’ or ’-d v’.
213 -view Starts the GUI interface for interactive coverage reporting.
215 -w (number)
216 Specifies the maximum line width (in characters) that can be
217 used to output Verilog information. If this option is not spec-
218 ified, all Verilog code in the report will retain the same for-
219 matting as was specified in the original Verilog code. If this
220 option is specified, Verilog code will be formatted to use as
221 much of the current line as possible, wrapping text when the
222 line reaches the maximum line width. The default maximum line
223 width is 115 characters (this value is used if no number is
224 specified with the -w option). If a number is specified with
225 the -w option, this value is used for the maximum line width.
227 AUTHORS
232 SEE ALSO
233 For more information on how to use the Covered code coverage tool,
234 please consult the on-line User’s Guide at http://covered.source-
235 forge.net/user/index.html.
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