2 T 300 900 8 10 1 1 0 0 1
4 T 600 2900 5 10 0 0 0 0 1
6 T 600 2700 5 10 0 0 0 0 1
8 T 600 2500 5 10 0 0 0 0 1
10 T 600 2300 5 10 0 0 0 0 1
12 T 600 2100 5 10 0 0 0 0 1
14 T 600 1900 5 10 0 0 0 0 1
16 T 600 1700 5 10 0 0 0 0 1
18 T 600 1500 5 10 0 0 0 0 1
20 T 600 1300 5 10 0 0 0 0 1
22 T 600 1100 5 10 0 0 0 0 1
26 T 200 750 5 8 1 1 0 6 1
28 T 200 650 5 8 0 1 0 8 1
30 T 350 700 9 8 0 1 0 0 1
32 T 350 700 5 8 0 1 0 2 1
37 T 200 350 5 8 1 1 0 6 1
39 T 200 250 5 8 0 1 0 8 1
41 T 350 300 9 8 0 1 0 0 1
43 T 350 300 5 8 0 1 0 2 1
46 P 1100 500 1300 500 1 0 1
48 T 1100 550 5 8 1 1 0 0 1
50 T 1100 450 5 8 0 1 0 2 1
52 T 950 500 9 8 0 1 0 6 1
54 T 950 500 5 8 0 1 0 8 1
57 A 700 500 300 270 180 3 0 0 0 -1 -1
58 L 300 800 700 800 3 0 0 0 -1 -1
59 L 300 200 300 800 3 0 0 0 -1 -1
60 L 300 200 700 200 3 0 0 0 -1 -1
61 V 1050 500 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
62 T 600 3100 5 10 0 0 0 0 1
63 description=4 NAND gates with 2 inputs and open collector output
66 T 600 3300 5 10 0 0 0 0 1
67 documentation=http://www.semiconductors.philips.com/acrobat/datasheets/74HC_HCT03_CNV_2.pdf