2 P 1300 600 1000 600 1 0 0
4 T 1100 650 5 8 1 1 0 0 1
6 T 1100 550 5 8 0 1 0 2 1
8 T 950 600 5 8 0 1 0 8 1
10 T 950 600 9 8 0 1 0 6 1
13 P 0 1100 300 1100 1 0 0
15 T 200 1150 5 8 1 1 0 6 1
17 T 200 1050 5 8 0 1 0 8 1
19 T 350 1100 5 8 0 1 0 2 1
21 T 350 1100 9 8 0 1 0 0 1
26 T 200 850 5 8 1 1 0 6 1
28 T 200 750 5 8 0 1 0 8 1
30 T 350 800 5 8 0 1 0 2 1
32 T 350 800 9 8 0 1 0 0 1
37 T 200 450 5 8 1 1 0 6 1
39 T 200 350 5 8 0 1 0 8 1
41 T 350 400 5 8 0 1 0 2 1
43 T 350 400 9 8 0 1 0 0 1
48 T 200 150 5 8 1 1 0 6 1
50 T 200 50 5 8 0 1 0 8 1
52 T 350 100 5 8 0 1 0 2 1
54 T 350 100 9 8 0 1 0 0 1
57 T 1000 1100 5 10 0 0 0 0 1
59 T 1000 1300 5 10 0 0 0 0 1
61 T 400 1000 8 10 1 1 0 0 1
63 T 1000 1700 5 10 0 0 0 0 1
65 T 1000 1900 5 10 0 0 0 0 1
67 T 1000 2100 5 10 0 0 0 0 1
68 slotdef=2:9,10,11,12,13
69 T 1000 2300 5 10 0 0 0 0 1
71 T 1000 1500 5 10 0 0 0 0 1
73 T 1900 1750 5 10 0 0 0 0 1
75 T 1000 2500 5 10 0 0 0 0 1
76 description=2 AND gates with 4 inputs
77 T 1000 2700 5 10 0 0 0 0 1
78 documentation=http://www.semiconductors.philips.com/acrobat/datasheets/HEF4082B_CNV_3.pdf
79 T 400 100 9 8 1 0 0 0 1
81 L 300 300 300 900 3 0 0 0 -1 -1
82 L 300 900 700 900 3 0 0 0 -1 -1
83 L 300 300 700 300 3 0 0 0 -1 -1
84 A 700 600 300 270 180 3 0 0 0 -1 -1
85 L 300 300 300 100 3 0 0 0 -1 -1
86 L 300 1100 300 900 3 0 0 0 -1 -1
87 L 300 1100 300 1200 3 0 0 0 -1 -1
88 L 300 0 300 100 3 0 0 0 -1 -1
89 T 1000 2900 5 10 0 0 0 0 1