verilog: add sv_maps iterators
[ghdl-vlg.git] / testsuite / sanity / 004all08 / testsuite.sh
blob81d2961b9854ed03664e2b6ec114112e28e41e07
1 #!/bin/sh
3 . ../../testenv.sh
5 GHDL_STD_FLAGS="--std=08"
6 analyze all08.vhdl
8 # Test reprint
9 $GHDL --reprint --std=08 all08.vhdl > all08.out
10 $GHDL --compare-tokens --std=08 all08.out all08.vhdl
12 # Test reprint --no-sem
13 $GHDL --reprint --std=08 --no-sem all08.vhdl > all08.out
14 $GHDL --compare-tokens --std=08 all08.vhdl all08.out
16 rm -f all08.out
18 # Test reprint ams (no-sem)
19 $GHDL --reprint --ams --no-sem ams08.vhdl > ams08.out
20 $GHDL --compare-tokens --ams ams08.out ams08.vhdl
22 rm -f ams08.out
24 clean
26 echo "test successful"