testsuite/synth/assign01/tb_assign02.v

   1 module tb_assign02;
   2    wire [7:0] a;
   3    reg [7:0] v;
   4
   5    assign02 dut (.r(a), .v(v));
   6
   7    initial begin
   8       v <= 8'he4;
   9       # 1;
  10       $display("a=%b", a);
  11       if (a !== 8'he4)
  12         $fatal(1, "FAILURE");
  13
  14       v <= 8'h38;
  15       # 1;
  16       $display("a=%b", a);
  17       if (a !== 8'h38)
  18         $fatal(1, "FAILURE");
  19
  20       $display("PASS");
  21       $finish;
  22    end
  23 endmodule