testsuite/synth/assign01/tb_mem02.v

   1 module tb_mem02;
   2    wire [7:0] r;
   3    reg [7:0] v;
   4    reg [3:0] addr;
   5    reg       clk;
   6
   7    mem02 dut (.r(r), .v(v), .addr(addr), .clk(clk));
   8
   9    initial begin
  10       //  Write 0xe4 at 3
  11       addr <= 4'h3;
  12       v <= 8'he4;
  13       clk <= 0;
  14       #1;
  15
  16       clk <= 1;
  17       # 1;
  18
  19       //  Write 0x83 at 8
  20       addr <= 4'h8;
  21       v <= 8'h83;
  22       clk <= 0;
  23       #1;
  24
  25       clk <= 1;
  26       # 1;
  27
  28       //  Read at 3 (async)
  29       addr <= 4'h3;
  30       clk <= 0;
  31       #1;
  32
  33       $display("r=%b", r);
  34       if (r !== 8'he4)
  35         $fatal(1, "FAILURE");
  36
  37       $display("PASS");
  38       $finish;
  39    end
  40 endmodule