testsuite/synth/blackbox01/blackbox1_adder.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 entity blackbox1_adder is
   6   port (a, b : in std_logic_vector(7 downto 0);
   7         r : out std_logic_vector(7 downto 0));
   8 end blackbox1_adder;
   9
  10 architecture behav of blackbox1_adder is
  11 begin
  12   r <= std_logic_vector(unsigned(a) + unsigned(b));
  13 end behav;