verilog: add sv_maps iterators

[ghdl-vlg.git] / testsuite / synth / dff03 / testsuite.sh

#! /bin/sh

. ../../testenv.sh

for t in dff01 dff02 dff03 dff04 dff05 dff06 dff07; do
    synth_tb $t
done

echo "Test successful"