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verilog: add sv_maps iterators
[ghdl-vlg.git]
/
testsuite
/
synth
/
dff04
/
dff05.v
blob
839b57b8b5b20783164206204b47f36839f098d5
1
module
dff05
(
input
clk
,
2
input
rst
,
3
input
[
7
:
0
]
din
,
4
output reg
[
7
:
0
]
dout
);
5
always
@(
posedge
clk
or posedge
rst
)
6
if
(
rst
)
7
dout
<=
0
;
8
else
9
dout
<=
din
;
10
endmodule