testsuite/synth/dff04/tb_dff05.v

   1 module tb_dff05;
   2
   3    reg clk;
   4    reg rst;
   5    reg [7:0] din;
   6    reg [7:0] dout;
   7
   8    dff05 dut (clk, rst, din, dout);
   9
  10    initial begin
  11       clk <= 0;
  12       rst <= 0;
  13       # 1;
  14       din <= 8'ha7;
  15       clk <= 1;
  16       # 1;
  17       if (dout != 8'ha7)
  18         $fatal(1, "failure");
  19       clk <= 0;
  20       #1;
  21       din <= 8'hb8;
  22       clk <= 1;
  23       # 1;
  24       if (dout != 8'hb8)
  25         $fatal(1, "failure");
  26
  27       rst <= 1;
  28       din <= 8'h23;
  29       # 1;
  30       if (dout != 8'h00)
  31         $fatal(1, "failure");
  32       clk <= 0;
  33       rst <= 0;
  34       #1;
  35       clk <= 1;
  36       # 1;
  37       if (dout != 8'h23)
  38         $fatal(1, "failure");
  39
  40       $finish;
  41    end
  42 endmodule