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verilog: add sv_maps iterators
[ghdl-vlg.git]
/
testsuite
/
synth
/
iassoc01
/
iassoc01.vhdl
blob
6a0a46bd0a635104f0c7d16f7ff6b440ce7808e1
1
use work.pkg.all;
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entity riassoc01 is
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port (v : nat_rec;
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res : out natural);
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end riassoc01;
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architecture behav of riassoc01 is
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begin
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res <= v.a + v.b;
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end behav;
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entity iassoc01 is
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port (a, b : natural;
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res : out natural);
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end iassoc01;
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architecture behav of iassoc01 is
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begin
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inst : entity work.riassoc01
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port map (v.a => a, v.b => b, res => res);
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end behav;