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verilog: add sv_maps iterators
[ghdl-vlg.git]
/
testsuite
/
synth
/
iassoc01
/
iassoc02.vhdl
blob
69064375ab8da18a8f8f15b287a8e25bac71507b
1
use work.pkg.all;
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entity riassoc02 is
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port (v : natural;
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res : out nat_rec);
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end riassoc02;
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architecture behav of riassoc02 is
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begin
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res.a <= v + 1;
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res.b <= v + 2;
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end behav;
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entity iassoc02 is
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port (v : natural;
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a, b : out natural);
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end iassoc02;
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architecture behav of iassoc02 is
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begin
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inst : entity work.riassoc02
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port map (v => v, res.a => a, res.b => b);
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end behav;