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verilog: add sv_maps iterators
[ghdl-vlg.git]
/
testsuite
/
synth
/
iassoc01
/
iassoc12.vhdl
blob
f7b7f54a094be64569f4db3a533d253a0ae6b1e3
1
use work.pkg.all;
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entity riassoc12 is
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port (v : natural;
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res : out nat_rec);
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end riassoc12;
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architecture behav of riassoc12 is
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begin
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res.a <= v + 1;
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res.b <= v + 2;
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end behav;
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entity iassoc12 is
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port (v : natural;
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a, b : out natural);
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end iassoc12;
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use work.pkg.all;
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architecture behav of iassoc12 is
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component riassoc12 is
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port (v : natural;
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res : out nat_rec);
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end component;
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begin
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inst : riassoc12
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port map (v => v, res.a => a, res.b => b);
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end behav;