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verilog: add sv_maps iterators
[ghdl-vlg.git]
/
testsuite
/
synth
/
issue1014
/
tb_record_test.vhdl
blob
e9fd6e06d9e7737430a4ad0661a4244fcdb8ef00
1
entity tb_record_test is
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end tb_record_test;
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library ieee;
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use ieee.std_logic_1164.all;
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architecture behav of tb_record_test is
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signal v : integer;
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begin
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dut: entity work.record_test
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port map (o => v);
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process
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begin
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wait for 1 ns;
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assert v = 333 severity failure;
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wait;
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end process;
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end behav;