verilog: add sv_maps iterators

[ghdl-vlg.git] / testsuite / synth / issue1039 / testsuite.sh

#! /bin/sh

. ../../testenv.sh

for t in ent; do
  synth $t.vhdl -e $t > syn_$t.vhdl
  analyze syn_$t.vhdl
done

clean

echo "Test successful"