testsuite/synth/issue1041/ent.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 entity ent is
   5         port (
   6                 reset : in std_logic;
   7                 clk : in std_logic
   8         );
   9 end ent;
  10
  11 architecture rtl of ent is
  12         function const return natural is
  13         begin
  14                 return 1;
  15         end const;
  16
  17         constant MAX_COUNT : natural := const;
  18         signal countdown : natural;
  19
  20         signal x : std_logic;
  21         signal y : std_logic;
  22 begin
  23         x <= '1';
  24         y <= '1';
  25
  26         process(reset, clk)
  27         begin
  28                 if reset then
  29                         countdown <= MAX_COUNT;
  30                 elsif rising_edge(clk) then
  31                         if x then
  32                                 if y then
  33                                         countdown <= MAX_COUNT;
  34                                 end if;
  35                         end if;
  36                 end if;
  37         end process;
  38 end rtl;