testsuite/synth/issue1077/ent.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all,
   3     ieee.numeric_std.all;
   4
   5 entity ent is
   6         port (
   7                 clk : in std_logic;
   8                 i : in std_logic_vector(7 downto 0);
   9
  10                 amount : in integer range 0 to 7;
  11
  12                 const_half : out signed(7 downto 0);
  13                 async_ror  : out std_logic_vector(7 downto 0);
  14                 clocked_left : out unsigned(7 downto 0)
  15         );
  16 end;
  17
  18 architecture a of ent is
  19         constant ONE : unsigned(3 downto 0) := x"4" srl 2;
  20 begin
  21         const_half <= signed(i) sra to_integer(ONE);
  22         async_ror  <= i ror amount;
  23
  24         process(clk)
  25         begin
  26                 if rising_edge(clk) then
  27                         clocked_left <= unsigned(i) sll amount;
  28                 end if;
  29         end process;
  30 end;