testsuite/synth/issue1114/ent.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 entity ent is
   5         port (
   6                 clk : in std_logic;
   7                 i : in std_logic_vector(7 downto 0);
   8                 o : out std_logic_vector(3 downto 0)
   9         );
  10 end;
  11
  12 architecture a of ent is
  13         function invert(x : std_logic_vector) return std_logic_vector is
  14         begin
  15                 return not x;
  16         end function;
  17 begin
  18         process(clk)
  19         begin
  20                 if rising_edge(clk) then
  21                         o <= invert(i)(3 downto 0);
  22                 end if;
  23         end process;
  24 end;