verilog: add sv_maps iterators
[ghdl-vlg.git] / testsuite / synth / issue1117 / testsuite.sh
blobad9d5418c7d6907a9c7d23bdf03d943804ed02f3
1 #! /bin/sh
3 . ../../testenv.sh
5 analyze ent.vhdl tb_ent.vhdl
6 elab_simulate tb_ent
7 clean
9 synth '-gg=x"ff_ff_00_01"' ent.vhdl -e ent > syn_ent.vhdl
10 analyze syn_ent.vhdl tb_ent.vhdl
11 elab_simulate tb_ent --ieee-asserts=disable-at-0
12 clean
14 echo "Test successful"