testsuite/synth/issue1155/tb_ent.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 entity tb_ent is
   5 end;
   6
   7 architecture a of tb_ent is
   8         component ent is
   9                 port (
  10                         clk   : in std_logic;
  11                         write : in std_logic;
  12
  13                         addr       : in std_logic_vector(1 downto 0);
  14                         data_write : in std_logic_vector(3 downto 0);
  15
  16                         x0 : out std_logic_vector(3 downto 0);
  17                         x1 : out std_logic_vector(3 downto 0);
  18                         x2 : out std_logic_vector(3 downto 0);
  19                         x3 : out std_logic_vector(3 downto 0)
  20                 );
  21         end component;
  22
  23         signal clk, write : std_logic;
  24         signal addr       : std_logic_vector(1 downto 0);
  25         signal data_write : std_logic_vector(3 downto 0);
  26         signal x0, x1, x2, x3 : std_logic_vector(3 downto 0);
  27 begin
  28         uut_inst: ent
  29                 port map (
  30                         clk   => clk,
  31                         write => write,
  32
  33                         addr => addr,
  34                         data_write => data_write,
  35
  36                         x0 => x0,
  37                         x1 => x1,
  38                         x2 => x2,
  39                         x3 => x3
  40                 );
  41
  42         process
  43                 procedure pulse is
  44                 begin
  45                         clk <= '0';
  46                         wait for 10 ns;
  47                         clk <= '1';
  48                         wait for 10 ns;
  49                 end;
  50         begin
  51                 write <= '0';
  52                 addr <= "00";
  53
  54                 pulse;
  55
  56                 write <= '1';
  57                 data_write <= "1111";
  58
  59                 pulse;
  60
  61                 assert x0 = "1111";
  62
  63                 write <= '0';
  64                 data_write <= "0001";
  65
  66                 pulse;
  67
  68                 assert x0 = "1111";
  69
  70                 wait for 20 ns;
  71
  72                 wait;
  73         end process;
  74 end;