testsuite/synth/issue1167/bug.vhdl

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 entity bug is
   6         generic(
   7                 LEN : positive := 32
   8         );
   9         port(
  10                 input1  :  in unsigned(LEN-1 downto 0);
  11                 output1 : out unsigned(LEN-1 downto 0)
  12         );
  13 end bug;
  14
  15 architecture behav of bug is
  16 begin
  17         output1 <= input1 and not to_unsigned(4096-1, input1'length);
  18 end architecture;