testsuite/synth/issue1168/bug.vhdl

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5 entity bug is
   6         generic(
   7                 LEN : positive := 32
   8         );
   9         port(
  10                 input_a :  in unsigned(LEN-1 downto 0);
  11                 input_b :  in unsigned(LEN-1 downto 0);
  12                 output1  : out unsigned(LEN-1 downto 0)
  13         );
  14 end bug;
  15
  16 architecture behav of bug is
  17 begin
  18         output1 <= minimum(input_a, input_b);
  19 end architecture;