verilog: add sv_maps iterators
[ghdl-vlg.git] / testsuite / synth / issue1239 / testsuite.sh
blob40b97d0fc42811902124d3eb47f5999066040ab1
1 #! /bin/sh
3 . ../../testenv.sh
5 GHDL_STD_FLAGS=-fsynopsys
6 synth repro.vhdl -e > syn_repro.vhdl
8 synth_failure repro2.vhdl -e
9 synth_failure repro3.vhdl -e
11 echo "Test successful"