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verilog: add sv_maps iterators
[ghdl-vlg.git]
/
testsuite
/
synth
/
issue1239
/
testsuite.sh
blob
40b97d0fc42811902124d3eb47f5999066040ab1
1
#! /bin/sh
2
3
. ..
/
..
/
testenv.sh
4
5
GHDL_STD_FLAGS
=
-fsynopsys
6
synth repro.vhdl
-e
>
syn_repro.vhdl
7
8
synth_failure repro2.vhdl
-e
9
synth_failure repro3.vhdl
-e
10
11
echo
"Test successful"