testsuite/synth/issue1283/issue1.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 entity issue1 is
   5 end issue1;
   6
   7 architecture beh of issue1 is
   8     type t_rec is
   9         record
  10             elem : std_logic_vector;
  11         end record;
  12 begin
  13     assert t_rec'(elem => "000") = t_rec'(elem => "000");
  14     assert t_rec'(elem => "001") = t_rec'(elem => "000") severity note;
  15 end architecture beh;