verilog: add sv_maps iterators
[ghdl-vlg.git] / testsuite / synth / issue1310 / issue2.vhdl
blob9d583d524a584862f5bd979feb6ed8132e8e7e71
1 library ieee;
2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
5 entity issue2 is
6 end issue2;
8 architecture beh of issue2 is
9 begin
10     assert (unsigned'("1111") >  unsigned'("0111"));
11     assert (unsigned'("1111") >= unsigned'("0111"));
12     assert (unsigned'("0111") <  unsigned'("1111"));
13     assert (unsigned'("0111") <= unsigned'("1111"));
15     assert (signed'("0111") >  signed'("1111"));
16     assert (signed'("0111") >= signed'("1111"));
17     assert (signed'("1111") <  signed'("0111"));
18     assert (signed'("1111") <= signed'("0111"));
20     assert signed'("1111") = -1;
21 end architecture beh;