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verilog: add sv_maps iterators
[ghdl-vlg.git] / testsuite / synth / issue1310 / testsuite.sh
blobbe51264d6fd70564b33c80229f32f18b432b6489
1 #! /bin/sh
2
3 . ../../testenv.sh
4
5 synth_analyze issue
6 synth_analyze issue2
7 clean
8
9 echo "Test successful"
Experimental work