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verilog: add sv_maps iterators
[ghdl-vlg.git] / testsuite / synth / issue1319 / testsuite.sh
blob78f25565d092aca2d28f613db969e97a80d313cc
1 #! /bin/sh
2
3 . ../../testenv.sh
4
5 GHDL_STD_FLAGS=--std=08
6 synth_tb ent
7
8 echo "Test successful"
Experimental work