verilog: add sv_maps iterators
[ghdl-vlg.git] / testsuite / synth / issue1414 / Makefile
blobe8033ac60fd2b80f869e099b543a2f0050d1c5cc
1 GHDL=ghdl
2 GHDLFLAGS=--ieee=synopsys -O2
4 MODULES= \
5 test.vhd \
7 .PHONY:
8 all: elaboration.done
9 ./tb --ieee-asserts=disable --dump-rti
11 elaboration.done: analyse.done
12 $(GHDL) -e $(GHDLFLAGS) -o tb tb
13 touch $@
15 analyse.done: $(MODULES)
16 echo Building rofl...
17 $(GHDL) -a $(GHDLFLAGS) $^
18 touch $@
20 .PHONY:
21 clean:
22 echo "Cleaning up..."
23 rm -f *.o *.cf *.done *.ghw tb