testsuite/synth/issue1414/cover_overlap_misparse.vhdl

   1 library IEEE;
   2 use IEEE.STD_LOGIC_1164.ALL;
   3 use IEEE.NUMERIC_STD.ALL;
   4
   5 entity cover_overlap_misparse is
   6     Port (
   7         clk: in STD_LOGIC;
   8         counter_val: out STD_LOGIC_VECTOR(3 downto 0)
   9     );
  10 end entity;
  11
  12 architecture Behavioral of cover_overlap_misparse is
  13     signal ctr_internal: UNSIGNED(3 downto 0) := x"0";
  14 begin
  15     process(clk) is
  16     begin
  17         ctr_internal <= ctr_internal + 1;
  18     end process;
  19     counter_val <= STD_LOGIC_VECTOR(ctr_internal);
  20
  21     -- psl default clock is rising_edge(clk);
  22     --psl assert always ctr_internal = 0 |-> ctr_internal = 0;
  23 end Behavioral;