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verilog: add sv_maps iterators
[ghdl-vlg.git]
/
testsuite
/
synth
/
issue1421
/
repro3.vhdl
blob
4fa0f4738baffa37276665ab6f7137f657d9d989
1
entity repro3 is
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port (clk : bit;
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v : bit_vector (1 downto 0);
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res : out bit_vector(1 downto 0));
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end;
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architecture behav of repro3 is
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begin
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process (clk)
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begin
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if clk'event and clk = '1' then
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res <= v;
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end if;
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res (0) <= '0';
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end process;
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end behav;